1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/FunctionLoweringInfo.h"
24 #include "llvm/CodeGen/GCMetadata.h"
25 #include "llvm/CodeGen/GCStrategy.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
32 #include "llvm/CodeGen/SchedulerRegistry.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/DebugInfo.h"
35 #include "llvm/IR/Constants.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/InlineAsm.h"
38 #include "llvm/IR/Instructions.h"
39 #include "llvm/IR/IntrinsicInst.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/IR/Module.h"
43 #include "llvm/Support/Compiler.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/Timer.h"
47 #include "llvm/Support/raw_ostream.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetIntrinsicInfo.h"
50 #include "llvm/Target/TargetLibraryInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetMachine.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "llvm/Target/TargetRegisterInfo.h"
55 #include "llvm/Target/TargetSubtargetInfo.h"
56 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
60 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
61 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
62 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
63 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
64 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
68 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
69 cl::desc("Enable extra verbose messages in the \"fast\" "
70 "instruction selector"));
72 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
73 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
74 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
75 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
76 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
77 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
78 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
80 // Standard binary operators...
81 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
82 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
83 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
84 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
85 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
86 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
87 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
88 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
89 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
90 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
91 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
92 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
94 // Logical operators...
95 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
96 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
97 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
99 // Memory instructions...
100 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
101 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
102 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
103 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
104 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
105 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
106 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
108 // Convert instructions...
109 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
110 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
111 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
112 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
113 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
114 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
115 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
116 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
117 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
118 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
119 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
120 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
122 // Other instructions...
123 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
124 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
125 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
126 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
127 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
128 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
129 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
130 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
131 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
132 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
133 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
134 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
135 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
136 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
137 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
141 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
142 cl::desc("Enable verbose messages in the \"fast\" "
143 "instruction selector"));
145 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
146 cl::desc("Enable abort calls when \"fast\" instruction fails"));
150 cl::desc("use Machine Branch Probability Info"),
151 cl::init(true), cl::Hidden);
155 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
156 cl::desc("Pop up a window to show dags before the first "
157 "dag combine pass"));
159 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
160 cl::desc("Pop up a window to show dags before legalize types"));
162 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
163 cl::desc("Pop up a window to show dags before legalize"));
165 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
166 cl::desc("Pop up a window to show dags before the second "
167 "dag combine pass"));
169 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
170 cl::desc("Pop up a window to show dags before the post legalize types"
171 " dag combine pass"));
173 ViewISelDAGs("view-isel-dags", cl::Hidden,
174 cl::desc("Pop up a window to show isel dags as they are selected"));
176 ViewSchedDAGs("view-sched-dags", cl::Hidden,
177 cl::desc("Pop up a window to show sched dags as they are processed"));
179 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
180 cl::desc("Pop up a window to show SUnit dags after they are processed"));
182 static const bool ViewDAGCombine1 = false,
183 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
184 ViewDAGCombine2 = false,
185 ViewDAGCombineLT = false,
186 ViewISelDAGs = false, ViewSchedDAGs = false,
187 ViewSUnitDAGs = false;
190 //===---------------------------------------------------------------------===//
192 /// RegisterScheduler class - Track the registration of instruction schedulers.
194 //===---------------------------------------------------------------------===//
195 MachinePassRegistry RegisterScheduler::Registry;
197 //===---------------------------------------------------------------------===//
199 /// ISHeuristic command line option for instruction schedulers.
201 //===---------------------------------------------------------------------===//
202 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
203 RegisterPassParser<RegisterScheduler> >
204 ISHeuristic("pre-RA-sched",
205 cl::init(&createDefaultScheduler),
206 cl::desc("Instruction schedulers available (before register"
209 static RegisterScheduler
210 defaultListDAGScheduler("default", "Best scheduler for the target",
211 createDefaultScheduler);
214 //===--------------------------------------------------------------------===//
215 /// createDefaultScheduler - This creates an instruction scheduler appropriate
217 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
218 CodeGenOpt::Level OptLevel) {
219 const TargetLowering &TLI = IS->getTargetLowering();
220 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
222 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
223 TLI.getSchedulingPreference() == Sched::Source)
224 return createSourceListDAGScheduler(IS, OptLevel);
225 if (TLI.getSchedulingPreference() == Sched::RegPressure)
226 return createBURRListDAGScheduler(IS, OptLevel);
227 if (TLI.getSchedulingPreference() == Sched::Hybrid)
228 return createHybridListDAGScheduler(IS, OptLevel);
229 if (TLI.getSchedulingPreference() == Sched::VLIW)
230 return createVLIWDAGScheduler(IS, OptLevel);
231 assert(TLI.getSchedulingPreference() == Sched::ILP &&
232 "Unknown sched type!");
233 return createILPListDAGScheduler(IS, OptLevel);
237 // EmitInstrWithCustomInserter - This method should be implemented by targets
238 // that mark instructions with the 'usesCustomInserter' flag. These
239 // instructions are special in various ways, which require special support to
240 // insert. The specified MachineInstr is created but not inserted into any
241 // basic blocks, and this method is called to expand it into a sequence of
242 // instructions, potentially also creating new basic blocks and control flow.
243 // When new basic blocks are inserted and the edges from MBB to its successors
244 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
247 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
248 MachineBasicBlock *MBB) const {
250 dbgs() << "If a target marks an instruction with "
251 "'usesCustomInserter', it must implement "
252 "TargetLowering::EmitInstrWithCustomInserter!";
257 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
258 SDNode *Node) const {
259 assert(!MI->hasPostISelHook() &&
260 "If a target marks an instruction with 'hasPostISelHook', "
261 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
264 //===----------------------------------------------------------------------===//
265 // SelectionDAGISel code
266 //===----------------------------------------------------------------------===//
268 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
269 CodeGenOpt::Level OL) :
270 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
271 FuncInfo(new FunctionLoweringInfo(TLI)),
272 CurDAG(new SelectionDAG(tm, OL)),
273 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
277 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
278 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
279 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
280 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
283 SelectionDAGISel::~SelectionDAGISel() {
289 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
290 AU.addRequired<AliasAnalysis>();
291 AU.addPreserved<AliasAnalysis>();
292 AU.addRequired<GCModuleInfo>();
293 AU.addPreserved<GCModuleInfo>();
294 AU.addRequired<TargetLibraryInfo>();
295 if (UseMBPI && OptLevel != CodeGenOpt::None)
296 AU.addRequired<BranchProbabilityInfo>();
297 MachineFunctionPass::getAnalysisUsage(AU);
300 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
301 /// may trap on it. In this case we have to split the edge so that the path
302 /// through the predecessor block that doesn't go to the phi block doesn't
303 /// execute the possibly trapping instruction.
305 /// This is required for correctness, so it must be done at -O0.
307 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
308 // Loop for blocks with phi nodes.
309 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
310 PHINode *PN = dyn_cast<PHINode>(BB->begin());
311 if (PN == 0) continue;
314 // For each block with a PHI node, check to see if any of the input values
315 // are potentially trapping constant expressions. Constant expressions are
316 // the only potentially trapping value that can occur as the argument to a
318 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
319 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
320 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
321 if (CE == 0 || !CE->canTrap()) continue;
323 // The only case we have to worry about is when the edge is critical.
324 // Since this block has a PHI Node, we assume it has multiple input
325 // edges: check to see if the pred has multiple successors.
326 BasicBlock *Pred = PN->getIncomingBlock(i);
327 if (Pred->getTerminator()->getNumSuccessors() == 1)
330 // Okay, we have to split this edge.
331 SplitCriticalEdge(Pred->getTerminator(),
332 GetSuccessorNumber(Pred, BB), SDISel, true);
338 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
339 // Do some sanity-checking on the command-line options.
340 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
341 "-fast-isel-verbose requires -fast-isel");
342 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
343 "-fast-isel-abort requires -fast-isel");
345 const Function &Fn = *mf.getFunction();
346 const TargetInstrInfo &TII = *TM.getInstrInfo();
347 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
350 RegInfo = &MF->getRegInfo();
351 AA = &getAnalysis<AliasAnalysis>();
352 LibInfo = &getAnalysis<TargetLibraryInfo>();
353 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
355 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
357 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
360 FuncInfo->set(Fn, *MF);
362 if (UseMBPI && OptLevel != CodeGenOpt::None)
363 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
367 SDB->init(GFI, *AA, LibInfo);
369 SelectAllBasicBlocks(Fn);
371 // If the first basic block in the function has live ins that need to be
372 // copied into vregs, emit the copies into the top of the block before
373 // emitting the code for the block.
374 MachineBasicBlock *EntryMBB = MF->begin();
375 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
377 DenseMap<unsigned, unsigned> LiveInMap;
378 if (!FuncInfo->ArgDbgValues.empty())
379 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
380 E = RegInfo->livein_end(); LI != E; ++LI)
382 LiveInMap.insert(std::make_pair(LI->first, LI->second));
384 // Insert DBG_VALUE instructions for function arguments to the entry block.
385 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
386 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
387 unsigned Reg = MI->getOperand(0).getReg();
388 if (TargetRegisterInfo::isPhysicalRegister(Reg))
389 EntryMBB->insert(EntryMBB->begin(), MI);
391 MachineInstr *Def = RegInfo->getVRegDef(Reg);
392 MachineBasicBlock::iterator InsertPos = Def;
393 // FIXME: VR def may not be in entry block.
394 Def->getParent()->insert(llvm::next(InsertPos), MI);
397 // If Reg is live-in then update debug info to track its copy in a vreg.
398 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
399 if (LDI != LiveInMap.end()) {
400 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
401 MachineBasicBlock::iterator InsertPos = Def;
402 const MDNode *Variable =
403 MI->getOperand(MI->getNumOperands()-1).getMetadata();
404 unsigned Offset = MI->getOperand(1).getImm();
405 // Def is never a terminator here, so it is ok to increment InsertPos.
406 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
407 TII.get(TargetOpcode::DBG_VALUE))
408 .addReg(LDI->second, RegState::Debug)
409 .addImm(Offset).addMetadata(Variable);
411 // If this vreg is directly copied into an exported register then
412 // that COPY instructions also need DBG_VALUE, if it is the only
413 // user of LDI->second.
414 MachineInstr *CopyUseMI = NULL;
415 for (MachineRegisterInfo::use_iterator
416 UI = RegInfo->use_begin(LDI->second);
417 MachineInstr *UseMI = UI.skipInstruction();) {
418 if (UseMI->isDebugValue()) continue;
419 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
420 CopyUseMI = UseMI; continue;
422 // Otherwise this is another use or second copy use.
423 CopyUseMI = NULL; break;
426 MachineInstr *NewMI =
427 BuildMI(*MF, CopyUseMI->getDebugLoc(),
428 TII.get(TargetOpcode::DBG_VALUE))
429 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
430 .addImm(Offset).addMetadata(Variable);
431 MachineBasicBlock::iterator Pos = CopyUseMI;
432 EntryMBB->insertAfter(Pos, NewMI);
437 // Determine if there are any calls in this machine function.
438 MachineFrameInfo *MFI = MF->getFrameInfo();
439 if (!MFI->hasCalls()) {
440 for (MachineFunction::const_iterator
441 I = MF->begin(), E = MF->end(); I != E; ++I) {
442 const MachineBasicBlock *MBB = I;
443 for (MachineBasicBlock::const_iterator
444 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
445 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
447 if ((MCID.isCall() && !MCID.isReturn()) ||
448 II->isStackAligningInlineAsm()) {
449 MFI->setHasCalls(true);
457 // Determine if there is a call to setjmp in the machine function.
458 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
460 // Replace forward-declared registers with the registers containing
461 // the desired value.
462 MachineRegisterInfo &MRI = MF->getRegInfo();
463 for (DenseMap<unsigned, unsigned>::iterator
464 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
466 unsigned From = I->first;
467 unsigned To = I->second;
468 // If To is also scheduled to be replaced, find what its ultimate
471 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
476 MRI.replaceRegWith(From, To);
479 // Freeze the set of reserved registers now that MachineFrameInfo has been
480 // set up. All the information required by getReservedRegs() should be
482 MRI.freezeReservedRegs(*MF);
484 // Release function-specific state. SDB and CurDAG are already cleared
491 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
492 BasicBlock::const_iterator End,
494 // Lower all of the non-terminator instructions. If a call is emitted
495 // as a tail call, cease emitting nodes for this block. Terminators
496 // are handled below.
497 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
500 // Make sure the root of the DAG is up-to-date.
501 CurDAG->setRoot(SDB->getControlRoot());
502 HadTailCall = SDB->HasTailCall;
505 // Final step, emit the lowered DAG as machine code.
509 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
510 SmallPtrSet<SDNode*, 128> VisitedNodes;
511 SmallVector<SDNode*, 128> Worklist;
513 Worklist.push_back(CurDAG->getRoot().getNode());
519 SDNode *N = Worklist.pop_back_val();
521 // If we've already seen this node, ignore it.
522 if (!VisitedNodes.insert(N))
525 // Otherwise, add all chain operands to the worklist.
526 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
527 if (N->getOperand(i).getValueType() == MVT::Other)
528 Worklist.push_back(N->getOperand(i).getNode());
530 // If this is a CopyToReg with a vreg dest, process it.
531 if (N->getOpcode() != ISD::CopyToReg)
534 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
535 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
538 // Ignore non-scalar or non-integer values.
539 SDValue Src = N->getOperand(2);
540 EVT SrcVT = Src.getValueType();
541 if (!SrcVT.isInteger() || SrcVT.isVector())
544 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
545 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
546 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
547 } while (!Worklist.empty());
550 void SelectionDAGISel::CodeGenAndEmitDAG() {
551 std::string GroupName;
552 if (TimePassesIsEnabled)
553 GroupName = "Instruction Selection and Scheduling";
554 std::string BlockName;
555 int BlockNumber = -1;
558 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
559 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
563 BlockNumber = FuncInfo->MBB->getNumber();
564 BlockName = MF->getName().str() + ":" +
565 FuncInfo->MBB->getBasicBlock()->getName().str();
567 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
568 << " '" << BlockName << "'\n"; CurDAG->dump());
570 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
572 // Run the DAG combiner in pre-legalize mode.
574 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
575 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
578 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
579 << " '" << BlockName << "'\n"; CurDAG->dump());
581 // Second step, hack on the DAG until it only uses operations and types that
582 // the target supports.
583 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
588 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
589 Changed = CurDAG->LegalizeTypes();
592 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
593 << " '" << BlockName << "'\n"; CurDAG->dump());
596 if (ViewDAGCombineLT)
597 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
599 // Run the DAG combiner in post-type-legalize mode.
601 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
602 TimePassesIsEnabled);
603 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
606 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
607 << " '" << BlockName << "'\n"; CurDAG->dump());
611 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
612 Changed = CurDAG->LegalizeVectors();
617 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
618 CurDAG->LegalizeTypes();
621 if (ViewDAGCombineLT)
622 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
624 // Run the DAG combiner in post-type-legalize mode.
626 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
627 TimePassesIsEnabled);
628 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
631 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
632 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
635 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
638 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
642 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
643 << " '" << BlockName << "'\n"; CurDAG->dump());
645 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
647 // Run the DAG combiner in post-legalize mode.
649 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
650 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
653 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
654 << " '" << BlockName << "'\n"; CurDAG->dump());
656 if (OptLevel != CodeGenOpt::None)
657 ComputeLiveOutVRegInfo();
659 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
661 // Third, instruction select all of the operations to machine code, adding the
662 // code to the MachineBasicBlock.
664 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
665 DoInstructionSelection();
668 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
669 << " '" << BlockName << "'\n"; CurDAG->dump());
671 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
673 // Schedule machine code.
674 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
676 NamedRegionTimer T("Instruction Scheduling", GroupName,
677 TimePassesIsEnabled);
678 Scheduler->Run(CurDAG, FuncInfo->MBB);
681 if (ViewSUnitDAGs) Scheduler->viewGraph();
683 // Emit machine code to BB. This can change 'BB' to the last block being
685 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
687 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
689 // FuncInfo->InsertPt is passed by reference and set to the end of the
690 // scheduled instructions.
691 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
694 // If the block was split, make sure we update any references that are used to
695 // update PHI nodes later on.
696 if (FirstMBB != LastMBB)
697 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
699 // Free the scheduler state.
701 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
702 TimePassesIsEnabled);
706 // Free the SelectionDAG state, now that we're finished with it.
711 /// ISelUpdater - helper class to handle updates of the instruction selection
713 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
714 SelectionDAG::allnodes_iterator &ISelPosition;
716 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
717 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
719 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
720 /// deleted is the current ISelPosition node, update ISelPosition.
722 virtual void NodeDeleted(SDNode *N, SDNode *E) {
723 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
727 } // end anonymous namespace
729 void SelectionDAGISel::DoInstructionSelection() {
730 DEBUG(errs() << "===== Instruction selection begins: BB#"
731 << FuncInfo->MBB->getNumber()
732 << " '" << FuncInfo->MBB->getName() << "'\n");
736 // Select target instructions for the DAG.
738 // Number all nodes with a topological order and set DAGSize.
739 DAGSize = CurDAG->AssignTopologicalOrder();
741 // Create a dummy node (which is not added to allnodes), that adds
742 // a reference to the root node, preventing it from being deleted,
743 // and tracking any changes of the root.
744 HandleSDNode Dummy(CurDAG->getRoot());
745 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
748 // Make sure that ISelPosition gets properly updated when nodes are deleted
749 // in calls made from this function.
750 ISelUpdater ISU(*CurDAG, ISelPosition);
752 // The AllNodes list is now topological-sorted. Visit the
753 // nodes by starting at the end of the list (the root of the
754 // graph) and preceding back toward the beginning (the entry
756 while (ISelPosition != CurDAG->allnodes_begin()) {
757 SDNode *Node = --ISelPosition;
758 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
759 // but there are currently some corner cases that it misses. Also, this
760 // makes it theoretically possible to disable the DAGCombiner.
761 if (Node->use_empty())
764 SDNode *ResNode = Select(Node);
766 // FIXME: This is pretty gross. 'Select' should be changed to not return
767 // anything at all and this code should be nuked with a tactical strike.
769 // If node should not be replaced, continue with the next one.
770 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
774 ReplaceUses(Node, ResNode);
776 // If after the replacement this node is not used any more,
777 // remove this dead node.
778 if (Node->use_empty()) // Don't delete EntryToken, etc.
779 CurDAG->RemoveDeadNode(Node);
782 CurDAG->setRoot(Dummy.getValue());
785 DEBUG(errs() << "===== Instruction selection ends:\n");
787 PostprocessISelDAG();
790 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
791 /// do other setup for EH landing-pad blocks.
792 void SelectionDAGISel::PrepareEHLandingPad() {
793 MachineBasicBlock *MBB = FuncInfo->MBB;
795 // Add a label to mark the beginning of the landing pad. Deletion of the
796 // landing pad can thus be detected via the MachineModuleInfo.
797 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
799 // Assign the call site to the landing pad's begin label.
800 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
802 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
803 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
806 // Mark exception register as live in.
807 unsigned Reg = TLI.getExceptionPointerRegister();
808 if (Reg) MBB->addLiveIn(Reg);
810 // Mark exception selector register as live in.
811 Reg = TLI.getExceptionSelectorRegister();
812 if (Reg) MBB->addLiveIn(Reg);
815 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
816 /// load into the specified FoldInst. Note that we could have a sequence where
817 /// multiple LLVM IR instructions are folded into the same machineinstr. For
818 /// example we could have:
819 /// A: x = load i32 *P
820 /// B: y = icmp A, 42
823 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
824 /// any other folded instructions) because it is between A and C.
826 /// If we succeed in folding the load into the operation, return true.
828 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
829 const Instruction *FoldInst,
831 // We know that the load has a single use, but don't know what it is. If it
832 // isn't one of the folded instructions, then we can't succeed here. Handle
833 // this by scanning the single-use users of the load until we get to FoldInst.
834 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
836 const Instruction *TheUser = LI->use_back();
837 while (TheUser != FoldInst && // Scan up until we find FoldInst.
838 // Stay in the right block.
839 TheUser->getParent() == FoldInst->getParent() &&
840 --MaxUsers) { // Don't scan too far.
841 // If there are multiple or no uses of this instruction, then bail out.
842 if (!TheUser->hasOneUse())
845 TheUser = TheUser->use_back();
848 // If we didn't find the fold instruction, then we failed to collapse the
850 if (TheUser != FoldInst)
853 // Don't try to fold volatile loads. Target has to deal with alignment
855 if (LI->isVolatile()) return false;
857 // Figure out which vreg this is going into. If there is no assigned vreg yet
858 // then there actually was no reference to it. Perhaps the load is referenced
859 // by a dead instruction.
860 unsigned LoadReg = FastIS->getRegForValue(LI);
864 // Check to see what the uses of this vreg are. If it has no uses, or more
865 // than one use (at the machine instr level) then we can't fold it.
866 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
867 if (RI == RegInfo->reg_end())
870 // See if there is exactly one use of the vreg. If there are multiple uses,
871 // then the instruction got lowered to multiple machine instructions or the
872 // use of the loaded value ended up being multiple operands of the result, in
873 // either case, we can't fold this.
874 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
875 if (PostRI != RegInfo->reg_end())
878 assert(RI.getOperand().isUse() &&
879 "The only use of the vreg must be a use, we haven't emitted the def!");
881 MachineInstr *User = &*RI;
883 // Set the insertion point properly. Folding the load can cause generation of
884 // other random instructions (like sign extends) for addressing modes, make
885 // sure they get inserted in a logical place before the new instruction.
886 FuncInfo->InsertPt = User;
887 FuncInfo->MBB = User->getParent();
889 // Ask the target to try folding the load.
890 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
893 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
894 /// side-effect free and is either dead or folded into a generated instruction.
895 /// Return false if it needs to be emitted.
896 static bool isFoldedOrDeadInstruction(const Instruction *I,
897 FunctionLoweringInfo *FuncInfo) {
898 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
899 !isa<TerminatorInst>(I) && // Terminators aren't folded.
900 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
901 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
902 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
906 // Collect per Instruction statistics for fast-isel misses. Only those
907 // instructions that cause the bail are accounted for. It does not account for
908 // instructions higher in the block. Thus, summing the per instructions stats
909 // will not add up to what is reported by NumFastIselFailures.
910 static void collectFailStats(const Instruction *I) {
911 switch (I->getOpcode()) {
912 default: assert (0 && "<Invalid operator> ");
915 case Instruction::Ret: NumFastIselFailRet++; return;
916 case Instruction::Br: NumFastIselFailBr++; return;
917 case Instruction::Switch: NumFastIselFailSwitch++; return;
918 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
919 case Instruction::Invoke: NumFastIselFailInvoke++; return;
920 case Instruction::Resume: NumFastIselFailResume++; return;
921 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
923 // Standard binary operators...
924 case Instruction::Add: NumFastIselFailAdd++; return;
925 case Instruction::FAdd: NumFastIselFailFAdd++; return;
926 case Instruction::Sub: NumFastIselFailSub++; return;
927 case Instruction::FSub: NumFastIselFailFSub++; return;
928 case Instruction::Mul: NumFastIselFailMul++; return;
929 case Instruction::FMul: NumFastIselFailFMul++; return;
930 case Instruction::UDiv: NumFastIselFailUDiv++; return;
931 case Instruction::SDiv: NumFastIselFailSDiv++; return;
932 case Instruction::FDiv: NumFastIselFailFDiv++; return;
933 case Instruction::URem: NumFastIselFailURem++; return;
934 case Instruction::SRem: NumFastIselFailSRem++; return;
935 case Instruction::FRem: NumFastIselFailFRem++; return;
937 // Logical operators...
938 case Instruction::And: NumFastIselFailAnd++; return;
939 case Instruction::Or: NumFastIselFailOr++; return;
940 case Instruction::Xor: NumFastIselFailXor++; return;
942 // Memory instructions...
943 case Instruction::Alloca: NumFastIselFailAlloca++; return;
944 case Instruction::Load: NumFastIselFailLoad++; return;
945 case Instruction::Store: NumFastIselFailStore++; return;
946 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
947 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
948 case Instruction::Fence: NumFastIselFailFence++; return;
949 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
951 // Convert instructions...
952 case Instruction::Trunc: NumFastIselFailTrunc++; return;
953 case Instruction::ZExt: NumFastIselFailZExt++; return;
954 case Instruction::SExt: NumFastIselFailSExt++; return;
955 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
956 case Instruction::FPExt: NumFastIselFailFPExt++; return;
957 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
958 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
959 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
960 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
961 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
962 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
963 case Instruction::BitCast: NumFastIselFailBitCast++; return;
965 // Other instructions...
966 case Instruction::ICmp: NumFastIselFailICmp++; return;
967 case Instruction::FCmp: NumFastIselFailFCmp++; return;
968 case Instruction::PHI: NumFastIselFailPHI++; return;
969 case Instruction::Select: NumFastIselFailSelect++; return;
970 case Instruction::Call: NumFastIselFailCall++; return;
971 case Instruction::Shl: NumFastIselFailShl++; return;
972 case Instruction::LShr: NumFastIselFailLShr++; return;
973 case Instruction::AShr: NumFastIselFailAShr++; return;
974 case Instruction::VAArg: NumFastIselFailVAArg++; return;
975 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
976 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
977 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
978 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
979 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
980 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
985 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
986 // Initialize the Fast-ISel state, if needed.
987 FastISel *FastIS = 0;
988 if (TM.Options.EnableFastISel)
989 FastIS = TLI.createFastISel(*FuncInfo, LibInfo);
991 // Iterate over all basic blocks in the function.
992 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
993 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
994 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
995 const BasicBlock *LLVMBB = *I;
997 if (OptLevel != CodeGenOpt::None) {
998 bool AllPredsVisited = true;
999 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1001 if (!FuncInfo->VisitedBBs.count(*PI)) {
1002 AllPredsVisited = false;
1007 if (AllPredsVisited) {
1008 for (BasicBlock::const_iterator I = LLVMBB->begin();
1009 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1010 FuncInfo->ComputePHILiveOutRegInfo(PN);
1012 for (BasicBlock::const_iterator I = LLVMBB->begin();
1013 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1014 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1017 FuncInfo->VisitedBBs.insert(LLVMBB);
1020 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1021 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1023 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1024 BasicBlock::const_iterator const End = LLVMBB->end();
1025 BasicBlock::const_iterator BI = End;
1027 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1029 // Setup an EH landing-pad block.
1030 if (FuncInfo->MBB->isLandingPad())
1031 PrepareEHLandingPad();
1033 // Lower any arguments needed in this block if this is the entry block.
1034 if (LLVMBB == &Fn.getEntryBlock())
1035 LowerArguments(LLVMBB);
1037 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1039 FastIS->startNewBlock();
1041 // Emit code for any incoming arguments. This must happen before
1042 // beginning FastISel on the entry block.
1043 if (LLVMBB == &Fn.getEntryBlock()) {
1044 CurDAG->setRoot(SDB->getControlRoot());
1046 CodeGenAndEmitDAG();
1048 // If we inserted any instructions at the beginning, make a note of
1049 // where they are, so we can be sure to emit subsequent instructions
1051 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1052 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1054 FastIS->setLastLocalValue(0);
1057 unsigned NumFastIselRemaining = std::distance(Begin, End);
1058 // Do FastISel on as many instructions as possible.
1059 for (; BI != Begin; --BI) {
1060 const Instruction *Inst = llvm::prior(BI);
1062 // If we no longer require this instruction, skip it.
1063 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1064 --NumFastIselRemaining;
1068 // Bottom-up: reset the insert pos at the top, after any local-value
1070 FastIS->recomputeInsertPt();
1072 // Try to select the instruction with FastISel.
1073 if (FastIS->SelectInstruction(Inst)) {
1074 --NumFastIselRemaining;
1075 ++NumFastIselSuccess;
1076 // If fast isel succeeded, skip over all the folded instructions, and
1077 // then see if there is a load right before the selected instructions.
1078 // Try to fold the load if so.
1079 const Instruction *BeforeInst = Inst;
1080 while (BeforeInst != Begin) {
1081 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1082 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1085 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1086 BeforeInst->hasOneUse() &&
1087 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
1088 // If we succeeded, don't re-select the load.
1089 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1090 --NumFastIselRemaining;
1091 ++NumFastIselSuccess;
1097 if (EnableFastISelVerbose2)
1098 collectFailStats(Inst);
1101 // Then handle certain instructions as single-LLVM-Instruction blocks.
1102 if (isa<CallInst>(Inst)) {
1104 if (EnableFastISelVerbose || EnableFastISelAbort) {
1105 dbgs() << "FastISel missed call: ";
1109 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1110 unsigned &R = FuncInfo->ValueMap[Inst];
1112 R = FuncInfo->CreateRegs(Inst->getType());
1115 bool HadTailCall = false;
1116 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1117 SelectBasicBlock(Inst, BI, HadTailCall);
1119 // If the call was emitted as a tail call, we're done with the block.
1120 // We also need to delete any previously emitted instructions.
1122 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1127 // Recompute NumFastIselRemaining as Selection DAG instruction
1128 // selection may have handled the call, input args, etc.
1129 unsigned RemainingNow = std::distance(Begin, BI);
1130 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1131 NumFastIselRemaining = RemainingNow;
1135 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1136 // Don't abort, and use a different message for terminator misses.
1137 NumFastIselFailures += NumFastIselRemaining;
1138 if (EnableFastISelVerbose || EnableFastISelAbort) {
1139 dbgs() << "FastISel missed terminator: ";
1143 NumFastIselFailures += NumFastIselRemaining;
1144 if (EnableFastISelVerbose || EnableFastISelAbort) {
1145 dbgs() << "FastISel miss: ";
1148 if (EnableFastISelAbort)
1149 // The "fast" selector couldn't handle something and bailed.
1150 // For the purpose of debugging, just abort.
1151 llvm_unreachable("FastISel didn't select the entire block");
1156 FastIS->recomputeInsertPt();
1162 ++NumFastIselBlocks;
1165 // Run SelectionDAG instruction selection on the remainder of the block
1166 // not handled by FastISel. If FastISel is not run, this is the entire
1169 SelectBasicBlock(Begin, BI, HadTailCall);
1173 FuncInfo->PHINodesToUpdate.clear();
1177 SDB->clearDanglingDebugInfo();
1181 SelectionDAGISel::FinishBasicBlock() {
1183 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1184 << FuncInfo->PHINodesToUpdate.size() << "\n";
1185 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1186 dbgs() << "Node " << i << " : ("
1187 << FuncInfo->PHINodesToUpdate[i].first
1188 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1190 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1191 // PHI nodes in successors.
1192 if (SDB->SwitchCases.empty() &&
1193 SDB->JTCases.empty() &&
1194 SDB->BitTestCases.empty()) {
1195 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1196 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1197 assert(PHI->isPHI() &&
1198 "This is not a machine PHI node that we are updating!");
1199 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1201 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1206 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1207 // Lower header first, if it wasn't already lowered
1208 if (!SDB->BitTestCases[i].Emitted) {
1209 // Set the current basic block to the mbb we wish to insert the code into
1210 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1211 FuncInfo->InsertPt = FuncInfo->MBB->end();
1213 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1214 CurDAG->setRoot(SDB->getRoot());
1216 CodeGenAndEmitDAG();
1219 uint32_t UnhandledWeight = 0;
1220 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1221 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1223 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1224 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1225 // Set the current basic block to the mbb we wish to insert the code into
1226 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1227 FuncInfo->InsertPt = FuncInfo->MBB->end();
1230 SDB->visitBitTestCase(SDB->BitTestCases[i],
1231 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1233 SDB->BitTestCases[i].Reg,
1234 SDB->BitTestCases[i].Cases[j],
1237 SDB->visitBitTestCase(SDB->BitTestCases[i],
1238 SDB->BitTestCases[i].Default,
1240 SDB->BitTestCases[i].Reg,
1241 SDB->BitTestCases[i].Cases[j],
1245 CurDAG->setRoot(SDB->getRoot());
1247 CodeGenAndEmitDAG();
1251 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1253 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1254 MachineBasicBlock *PHIBB = PHI->getParent();
1255 assert(PHI->isPHI() &&
1256 "This is not a machine PHI node that we are updating!");
1257 // This is "default" BB. We have two jumps to it. From "header" BB and
1258 // from last "case" BB.
1259 if (PHIBB == SDB->BitTestCases[i].Default)
1260 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1261 .addMBB(SDB->BitTestCases[i].Parent)
1262 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1263 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1264 // One of "cases" BB.
1265 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1267 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1268 if (cBB->isSuccessor(PHIBB))
1269 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1273 SDB->BitTestCases.clear();
1275 // If the JumpTable record is filled in, then we need to emit a jump table.
1276 // Updating the PHI nodes is tricky in this case, since we need to determine
1277 // whether the PHI is a successor of the range check MBB or the jump table MBB
1278 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1279 // Lower header first, if it wasn't already lowered
1280 if (!SDB->JTCases[i].first.Emitted) {
1281 // Set the current basic block to the mbb we wish to insert the code into
1282 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1283 FuncInfo->InsertPt = FuncInfo->MBB->end();
1285 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1287 CurDAG->setRoot(SDB->getRoot());
1289 CodeGenAndEmitDAG();
1292 // Set the current basic block to the mbb we wish to insert the code into
1293 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1294 FuncInfo->InsertPt = FuncInfo->MBB->end();
1296 SDB->visitJumpTable(SDB->JTCases[i].second);
1297 CurDAG->setRoot(SDB->getRoot());
1299 CodeGenAndEmitDAG();
1302 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1304 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1305 MachineBasicBlock *PHIBB = PHI->getParent();
1306 assert(PHI->isPHI() &&
1307 "This is not a machine PHI node that we are updating!");
1308 // "default" BB. We can go there only from header BB.
1309 if (PHIBB == SDB->JTCases[i].second.Default)
1310 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1311 .addMBB(SDB->JTCases[i].first.HeaderBB);
1312 // JT BB. Just iterate over successors here
1313 if (FuncInfo->MBB->isSuccessor(PHIBB))
1314 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1317 SDB->JTCases.clear();
1319 // If the switch block involved a branch to one of the actual successors, we
1320 // need to update PHI nodes in that block.
1321 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1322 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1323 assert(PHI->isPHI() &&
1324 "This is not a machine PHI node that we are updating!");
1325 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1326 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1329 // If we generated any switch lowering information, build and codegen any
1330 // additional DAGs necessary.
1331 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1332 // Set the current basic block to the mbb we wish to insert the code into
1333 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1334 FuncInfo->InsertPt = FuncInfo->MBB->end();
1336 // Determine the unique successors.
1337 SmallVector<MachineBasicBlock *, 2> Succs;
1338 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1339 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1340 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1342 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1343 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1344 CurDAG->setRoot(SDB->getRoot());
1346 CodeGenAndEmitDAG();
1348 // Remember the last block, now that any splitting is done, for use in
1349 // populating PHI nodes in successors.
1350 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1352 // Handle any PHI nodes in successors of this chunk, as if we were coming
1353 // from the original BB before switch expansion. Note that PHI nodes can
1354 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1355 // handle them the right number of times.
1356 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1357 FuncInfo->MBB = Succs[i];
1358 FuncInfo->InsertPt = FuncInfo->MBB->end();
1359 // FuncInfo->MBB may have been removed from the CFG if a branch was
1361 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1362 for (MachineBasicBlock::iterator
1363 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1364 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1365 MachineInstrBuilder PHI(*MF, MBBI);
1366 // This value for this PHI node is recorded in PHINodesToUpdate.
1367 for (unsigned pn = 0; ; ++pn) {
1368 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1369 "Didn't find PHI entry!");
1370 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1371 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1379 SDB->SwitchCases.clear();
1383 /// Create the scheduler. If a specific scheduler was specified
1384 /// via the SchedulerRegistry, use it, otherwise select the
1385 /// one preferred by the target.
1387 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1388 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1392 RegisterScheduler::setDefault(Ctor);
1395 return Ctor(this, OptLevel);
1398 //===----------------------------------------------------------------------===//
1399 // Helper functions used by the generated instruction selector.
1400 //===----------------------------------------------------------------------===//
1401 // Calls to these methods are generated by tblgen.
1403 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1404 /// the dag combiner simplified the 255, we still want to match. RHS is the
1405 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1406 /// specified in the .td file (e.g. 255).
1407 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1408 int64_t DesiredMaskS) const {
1409 const APInt &ActualMask = RHS->getAPIntValue();
1410 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1412 // If the actual mask exactly matches, success!
1413 if (ActualMask == DesiredMask)
1416 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1417 if (ActualMask.intersects(~DesiredMask))
1420 // Otherwise, the DAG Combiner may have proven that the value coming in is
1421 // either already zero or is not demanded. Check for known zero input bits.
1422 APInt NeededMask = DesiredMask & ~ActualMask;
1423 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1426 // TODO: check to see if missing bits are just not demanded.
1428 // Otherwise, this pattern doesn't match.
1432 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1433 /// the dag combiner simplified the 255, we still want to match. RHS is the
1434 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1435 /// specified in the .td file (e.g. 255).
1436 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1437 int64_t DesiredMaskS) const {
1438 const APInt &ActualMask = RHS->getAPIntValue();
1439 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1441 // If the actual mask exactly matches, success!
1442 if (ActualMask == DesiredMask)
1445 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1446 if (ActualMask.intersects(~DesiredMask))
1449 // Otherwise, the DAG Combiner may have proven that the value coming in is
1450 // either already zero or is not demanded. Check for known zero input bits.
1451 APInt NeededMask = DesiredMask & ~ActualMask;
1453 APInt KnownZero, KnownOne;
1454 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1456 // If all the missing bits in the or are already known to be set, match!
1457 if ((NeededMask & KnownOne) == NeededMask)
1460 // TODO: check to see if missing bits are just not demanded.
1462 // Otherwise, this pattern doesn't match.
1467 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1468 /// by tblgen. Others should not call it.
1469 void SelectionDAGISel::
1470 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1471 std::vector<SDValue> InOps;
1472 std::swap(InOps, Ops);
1474 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1475 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1476 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1477 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1479 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1480 if (InOps[e-1].getValueType() == MVT::Glue)
1481 --e; // Don't process a glue operand if it is here.
1484 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1485 if (!InlineAsm::isMemKind(Flags)) {
1486 // Just skip over this operand, copying the operands verbatim.
1487 Ops.insert(Ops.end(), InOps.begin()+i,
1488 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1489 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1491 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1492 "Memory operand with multiple values?");
1493 // Otherwise, this is a memory operand. Ask the target to select it.
1494 std::vector<SDValue> SelOps;
1495 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1496 report_fatal_error("Could not match memory address. Inline asm"
1499 // Add this to the output node.
1501 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1502 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1503 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1508 // Add the glue input back if present.
1509 if (e != InOps.size())
1510 Ops.push_back(InOps.back());
1513 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1516 static SDNode *findGlueUse(SDNode *N) {
1517 unsigned FlagResNo = N->getNumValues()-1;
1518 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1519 SDUse &Use = I.getUse();
1520 if (Use.getResNo() == FlagResNo)
1521 return Use.getUser();
1526 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1527 /// This function recursively traverses up the operand chain, ignoring
1529 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1530 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1531 bool IgnoreChains) {
1532 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1533 // greater than all of its (recursive) operands. If we scan to a point where
1534 // 'use' is smaller than the node we're scanning for, then we know we will
1537 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1538 // happen because we scan down to newly selected nodes in the case of glue
1540 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1543 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1544 // won't fail if we scan it again.
1545 if (!Visited.insert(Use))
1548 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1549 // Ignore chain uses, they are validated by HandleMergeInputChains.
1550 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1553 SDNode *N = Use->getOperand(i).getNode();
1555 if (Use == ImmedUse || Use == Root)
1556 continue; // We are not looking for immediate use.
1561 // Traverse up the operand chain.
1562 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1568 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1569 /// operand node N of U during instruction selection that starts at Root.
1570 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1571 SDNode *Root) const {
1572 if (OptLevel == CodeGenOpt::None) return false;
1573 return N.hasOneUse();
1576 /// IsLegalToFold - Returns true if the specific operand node N of
1577 /// U can be folded during instruction selection that starts at Root.
1578 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1579 CodeGenOpt::Level OptLevel,
1580 bool IgnoreChains) {
1581 if (OptLevel == CodeGenOpt::None) return false;
1583 // If Root use can somehow reach N through a path that that doesn't contain
1584 // U then folding N would create a cycle. e.g. In the following
1585 // diagram, Root can reach N through X. If N is folded into into Root, then
1586 // X is both a predecessor and a successor of U.
1597 // * indicates nodes to be folded together.
1599 // If Root produces glue, then it gets (even more) interesting. Since it
1600 // will be "glued" together with its glue use in the scheduler, we need to
1601 // check if it might reach N.
1620 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1621 // (call it Fold), then X is a predecessor of GU and a successor of
1622 // Fold. But since Fold and GU are glued together, this will create
1623 // a cycle in the scheduling graph.
1625 // If the node has glue, walk down the graph to the "lowest" node in the
1627 EVT VT = Root->getValueType(Root->getNumValues()-1);
1628 while (VT == MVT::Glue) {
1629 SDNode *GU = findGlueUse(Root);
1633 VT = Root->getValueType(Root->getNumValues()-1);
1635 // If our query node has a glue result with a use, we've walked up it. If
1636 // the user (which has already been selected) has a chain or indirectly uses
1637 // the chain, our WalkChainUsers predicate will not consider it. Because of
1638 // this, we cannot ignore chains in this predicate.
1639 IgnoreChains = false;
1643 SmallPtrSet<SDNode*, 16> Visited;
1644 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1647 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1648 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1649 SelectInlineAsmMemoryOperands(Ops);
1651 std::vector<EVT> VTs;
1652 VTs.push_back(MVT::Other);
1653 VTs.push_back(MVT::Glue);
1654 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1655 VTs, &Ops[0], Ops.size());
1657 return New.getNode();
1660 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1661 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1664 /// GetVBR - decode a vbr encoding whose top bit is set.
1665 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1666 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1667 assert(Val >= 128 && "Not a VBR");
1668 Val &= 127; // Remove first vbr bit.
1673 NextBits = MatcherTable[Idx++];
1674 Val |= (NextBits&127) << Shift;
1676 } while (NextBits & 128);
1682 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1683 /// interior glue and chain results to use the new glue and chain results.
1684 void SelectionDAGISel::
1685 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1686 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1688 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1689 bool isMorphNodeTo) {
1690 SmallVector<SDNode*, 4> NowDeadNodes;
1692 // Now that all the normal results are replaced, we replace the chain and
1693 // glue results if present.
1694 if (!ChainNodesMatched.empty()) {
1695 assert(InputChain.getNode() != 0 &&
1696 "Matched input chains but didn't produce a chain");
1697 // Loop over all of the nodes we matched that produced a chain result.
1698 // Replace all the chain results with the final chain we ended up with.
1699 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1700 SDNode *ChainNode = ChainNodesMatched[i];
1702 // If this node was already deleted, don't look at it.
1703 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1706 // Don't replace the results of the root node if we're doing a
1708 if (ChainNode == NodeToMatch && isMorphNodeTo)
1711 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1712 if (ChainVal.getValueType() == MVT::Glue)
1713 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1714 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1715 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1717 // If the node became dead and we haven't already seen it, delete it.
1718 if (ChainNode->use_empty() &&
1719 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1720 NowDeadNodes.push_back(ChainNode);
1724 // If the result produces glue, update any glue results in the matched
1725 // pattern with the glue result.
1726 if (InputGlue.getNode() != 0) {
1727 // Handle any interior nodes explicitly marked.
1728 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1729 SDNode *FRN = GlueResultNodesMatched[i];
1731 // If this node was already deleted, don't look at it.
1732 if (FRN->getOpcode() == ISD::DELETED_NODE)
1735 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1736 "Doesn't have a glue result");
1737 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1740 // If the node became dead and we haven't already seen it, delete it.
1741 if (FRN->use_empty() &&
1742 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1743 NowDeadNodes.push_back(FRN);
1747 if (!NowDeadNodes.empty())
1748 CurDAG->RemoveDeadNodes(NowDeadNodes);
1750 DEBUG(errs() << "ISEL: Match complete!\n");
1756 CR_LeadsToInteriorNode
1759 /// WalkChainUsers - Walk down the users of the specified chained node that is
1760 /// part of the pattern we're matching, looking at all of the users we find.
1761 /// This determines whether something is an interior node, whether we have a
1762 /// non-pattern node in between two pattern nodes (which prevent folding because
1763 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1764 /// between pattern nodes (in which case the TF becomes part of the pattern).
1766 /// The walk we do here is guaranteed to be small because we quickly get down to
1767 /// already selected nodes "below" us.
1769 WalkChainUsers(const SDNode *ChainedNode,
1770 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1771 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1772 ChainResult Result = CR_Simple;
1774 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1775 E = ChainedNode->use_end(); UI != E; ++UI) {
1776 // Make sure the use is of the chain, not some other value we produce.
1777 if (UI.getUse().getValueType() != MVT::Other) continue;
1781 // If we see an already-selected machine node, then we've gone beyond the
1782 // pattern that we're selecting down into the already selected chunk of the
1784 if (User->isMachineOpcode() ||
1785 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1788 unsigned UserOpcode = User->getOpcode();
1789 if (UserOpcode == ISD::CopyToReg ||
1790 UserOpcode == ISD::CopyFromReg ||
1791 UserOpcode == ISD::INLINEASM ||
1792 UserOpcode == ISD::EH_LABEL ||
1793 UserOpcode == ISD::LIFETIME_START ||
1794 UserOpcode == ISD::LIFETIME_END) {
1795 // If their node ID got reset to -1 then they've already been selected.
1796 // Treat them like a MachineOpcode.
1797 if (User->getNodeId() == -1)
1801 // If we have a TokenFactor, we handle it specially.
1802 if (User->getOpcode() != ISD::TokenFactor) {
1803 // If the node isn't a token factor and isn't part of our pattern, then it
1804 // must be a random chained node in between two nodes we're selecting.
1805 // This happens when we have something like:
1810 // Because we structurally match the load/store as a read/modify/write,
1811 // but the call is chained between them. We cannot fold in this case
1812 // because it would induce a cycle in the graph.
1813 if (!std::count(ChainedNodesInPattern.begin(),
1814 ChainedNodesInPattern.end(), User))
1815 return CR_InducesCycle;
1817 // Otherwise we found a node that is part of our pattern. For example in:
1821 // This would happen when we're scanning down from the load and see the
1822 // store as a user. Record that there is a use of ChainedNode that is
1823 // part of the pattern and keep scanning uses.
1824 Result = CR_LeadsToInteriorNode;
1825 InteriorChainedNodes.push_back(User);
1829 // If we found a TokenFactor, there are two cases to consider: first if the
1830 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1831 // uses of the TF are in our pattern) we just want to ignore it. Second,
1832 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1838 // | \ DAG's like cheese
1841 // [TokenFactor] [Op]
1848 // In this case, the TokenFactor becomes part of our match and we rewrite it
1849 // as a new TokenFactor.
1851 // To distinguish these two cases, do a recursive walk down the uses.
1852 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1854 // If the uses of the TokenFactor are just already-selected nodes, ignore
1855 // it, it is "below" our pattern.
1857 case CR_InducesCycle:
1858 // If the uses of the TokenFactor lead to nodes that are not part of our
1859 // pattern that are not selected, folding would turn this into a cycle,
1861 return CR_InducesCycle;
1862 case CR_LeadsToInteriorNode:
1863 break; // Otherwise, keep processing.
1866 // Okay, we know we're in the interesting interior case. The TokenFactor
1867 // is now going to be considered part of the pattern so that we rewrite its
1868 // uses (it may have uses that are not part of the pattern) with the
1869 // ultimate chain result of the generated code. We will also add its chain
1870 // inputs as inputs to the ultimate TokenFactor we create.
1871 Result = CR_LeadsToInteriorNode;
1872 ChainedNodesInPattern.push_back(User);
1873 InteriorChainedNodes.push_back(User);
1880 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1881 /// operation for when the pattern matched at least one node with a chains. The
1882 /// input vector contains a list of all of the chained nodes that we match. We
1883 /// must determine if this is a valid thing to cover (i.e. matching it won't
1884 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1885 /// be used as the input node chain for the generated nodes.
1887 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1888 SelectionDAG *CurDAG) {
1889 // Walk all of the chained nodes we've matched, recursively scanning down the
1890 // users of the chain result. This adds any TokenFactor nodes that are caught
1891 // in between chained nodes to the chained and interior nodes list.
1892 SmallVector<SDNode*, 3> InteriorChainedNodes;
1893 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1894 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1895 InteriorChainedNodes) == CR_InducesCycle)
1896 return SDValue(); // Would induce a cycle.
1899 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1900 // that we are interested in. Form our input TokenFactor node.
1901 SmallVector<SDValue, 3> InputChains;
1902 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1903 // Add the input chain of this node to the InputChains list (which will be
1904 // the operands of the generated TokenFactor) if it's not an interior node.
1905 SDNode *N = ChainNodesMatched[i];
1906 if (N->getOpcode() != ISD::TokenFactor) {
1907 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1910 // Otherwise, add the input chain.
1911 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1912 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1913 InputChains.push_back(InChain);
1917 // If we have a token factor, we want to add all inputs of the token factor
1918 // that are not part of the pattern we're matching.
1919 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1920 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1921 N->getOperand(op).getNode()))
1922 InputChains.push_back(N->getOperand(op));
1927 if (InputChains.size() == 1)
1928 return InputChains[0];
1929 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1930 MVT::Other, &InputChains[0], InputChains.size());
1933 /// MorphNode - Handle morphing a node in place for the selector.
1934 SDNode *SelectionDAGISel::
1935 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1936 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1937 // It is possible we're using MorphNodeTo to replace a node with no
1938 // normal results with one that has a normal result (or we could be
1939 // adding a chain) and the input could have glue and chains as well.
1940 // In this case we need to shift the operands down.
1941 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1942 // than the old isel though.
1943 int OldGlueResultNo = -1, OldChainResultNo = -1;
1945 unsigned NTMNumResults = Node->getNumValues();
1946 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1947 OldGlueResultNo = NTMNumResults-1;
1948 if (NTMNumResults != 1 &&
1949 Node->getValueType(NTMNumResults-2) == MVT::Other)
1950 OldChainResultNo = NTMNumResults-2;
1951 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1952 OldChainResultNo = NTMNumResults-1;
1954 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1955 // that this deletes operands of the old node that become dead.
1956 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1958 // MorphNodeTo can operate in two ways: if an existing node with the
1959 // specified operands exists, it can just return it. Otherwise, it
1960 // updates the node in place to have the requested operands.
1962 // If we updated the node in place, reset the node ID. To the isel,
1963 // this should be just like a newly allocated machine node.
1967 unsigned ResNumResults = Res->getNumValues();
1968 // Move the glue if needed.
1969 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1970 (unsigned)OldGlueResultNo != ResNumResults-1)
1971 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1972 SDValue(Res, ResNumResults-1));
1974 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1977 // Move the chain reference if needed.
1978 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1979 (unsigned)OldChainResultNo != ResNumResults-1)
1980 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1981 SDValue(Res, ResNumResults-1));
1983 // Otherwise, no replacement happened because the node already exists. Replace
1984 // Uses of the old node with the new one.
1986 CurDAG->ReplaceAllUsesWith(Node, Res);
1991 /// CheckSame - Implements OP_CheckSame.
1992 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1993 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1995 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1996 // Accept if it is exactly the same as a previously recorded node.
1997 unsigned RecNo = MatcherTable[MatcherIndex++];
1998 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1999 return N == RecordedNodes[RecNo].first;
2002 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2003 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2004 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2005 const SelectionDAGISel &SDISel) {
2006 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2009 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2010 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2011 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2012 const SelectionDAGISel &SDISel, SDNode *N) {
2013 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2016 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2017 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2019 uint16_t Opc = MatcherTable[MatcherIndex++];
2020 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2021 return N->getOpcode() == Opc;
2024 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2025 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2026 SDValue N, const TargetLowering &TLI) {
2027 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2028 if (N.getValueType() == VT) return true;
2030 // Handle the case when VT is iPTR.
2031 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
2034 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2035 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2036 SDValue N, const TargetLowering &TLI,
2038 if (ChildNo >= N.getNumOperands())
2039 return false; // Match fails if out of range child #.
2040 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2044 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2045 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2047 return cast<CondCodeSDNode>(N)->get() ==
2048 (ISD::CondCode)MatcherTable[MatcherIndex++];
2051 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2052 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2053 SDValue N, const TargetLowering &TLI) {
2054 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2055 if (cast<VTSDNode>(N)->getVT() == VT)
2058 // Handle the case when VT is iPTR.
2059 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
2062 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2063 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2065 int64_t Val = MatcherTable[MatcherIndex++];
2067 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2069 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2070 return C != 0 && C->getSExtValue() == Val;
2073 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2074 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2075 SDValue N, const SelectionDAGISel &SDISel) {
2076 int64_t Val = MatcherTable[MatcherIndex++];
2078 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2080 if (N->getOpcode() != ISD::AND) return false;
2082 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2083 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2086 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2087 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2088 SDValue N, const SelectionDAGISel &SDISel) {
2089 int64_t Val = MatcherTable[MatcherIndex++];
2091 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2093 if (N->getOpcode() != ISD::OR) return false;
2095 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2096 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2099 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2100 /// scope, evaluate the current node. If the current predicate is known to
2101 /// fail, set Result=true and return anything. If the current predicate is
2102 /// known to pass, set Result=false and return the MatcherIndex to continue
2103 /// with. If the current predicate is unknown, set Result=false and return the
2104 /// MatcherIndex to continue with.
2105 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2106 unsigned Index, SDValue N,
2108 const SelectionDAGISel &SDISel,
2109 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2110 switch (Table[Index++]) {
2113 return Index-1; // Could not evaluate this predicate.
2114 case SelectionDAGISel::OPC_CheckSame:
2115 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2117 case SelectionDAGISel::OPC_CheckPatternPredicate:
2118 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2120 case SelectionDAGISel::OPC_CheckPredicate:
2121 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2123 case SelectionDAGISel::OPC_CheckOpcode:
2124 Result = !::CheckOpcode(Table, Index, N.getNode());
2126 case SelectionDAGISel::OPC_CheckType:
2127 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2129 case SelectionDAGISel::OPC_CheckChild0Type:
2130 case SelectionDAGISel::OPC_CheckChild1Type:
2131 case SelectionDAGISel::OPC_CheckChild2Type:
2132 case SelectionDAGISel::OPC_CheckChild3Type:
2133 case SelectionDAGISel::OPC_CheckChild4Type:
2134 case SelectionDAGISel::OPC_CheckChild5Type:
2135 case SelectionDAGISel::OPC_CheckChild6Type:
2136 case SelectionDAGISel::OPC_CheckChild7Type:
2137 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2138 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2140 case SelectionDAGISel::OPC_CheckCondCode:
2141 Result = !::CheckCondCode(Table, Index, N);
2143 case SelectionDAGISel::OPC_CheckValueType:
2144 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2146 case SelectionDAGISel::OPC_CheckInteger:
2147 Result = !::CheckInteger(Table, Index, N);
2149 case SelectionDAGISel::OPC_CheckAndImm:
2150 Result = !::CheckAndImm(Table, Index, N, SDISel);
2152 case SelectionDAGISel::OPC_CheckOrImm:
2153 Result = !::CheckOrImm(Table, Index, N, SDISel);
2161 /// FailIndex - If this match fails, this is the index to continue with.
2164 /// NodeStack - The node stack when the scope was formed.
2165 SmallVector<SDValue, 4> NodeStack;
2167 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2168 unsigned NumRecordedNodes;
2170 /// NumMatchedMemRefs - The number of matched memref entries.
2171 unsigned NumMatchedMemRefs;
2173 /// InputChain/InputGlue - The current chain/glue
2174 SDValue InputChain, InputGlue;
2176 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2177 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2182 SDNode *SelectionDAGISel::
2183 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2184 unsigned TableSize) {
2185 // FIXME: Should these even be selected? Handle these cases in the caller?
2186 switch (NodeToMatch->getOpcode()) {
2189 case ISD::EntryToken: // These nodes remain the same.
2190 case ISD::BasicBlock:
2192 case ISD::RegisterMask:
2193 //case ISD::VALUETYPE:
2194 //case ISD::CONDCODE:
2195 case ISD::HANDLENODE:
2196 case ISD::MDNODE_SDNODE:
2197 case ISD::TargetConstant:
2198 case ISD::TargetConstantFP:
2199 case ISD::TargetConstantPool:
2200 case ISD::TargetFrameIndex:
2201 case ISD::TargetExternalSymbol:
2202 case ISD::TargetBlockAddress:
2203 case ISD::TargetJumpTable:
2204 case ISD::TargetGlobalTLSAddress:
2205 case ISD::TargetGlobalAddress:
2206 case ISD::TokenFactor:
2207 case ISD::CopyFromReg:
2208 case ISD::CopyToReg:
2210 case ISD::LIFETIME_START:
2211 case ISD::LIFETIME_END:
2212 NodeToMatch->setNodeId(-1); // Mark selected.
2214 case ISD::AssertSext:
2215 case ISD::AssertZext:
2216 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2217 NodeToMatch->getOperand(0));
2219 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2220 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2223 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2225 // Set up the node stack with NodeToMatch as the only node on the stack.
2226 SmallVector<SDValue, 8> NodeStack;
2227 SDValue N = SDValue(NodeToMatch, 0);
2228 NodeStack.push_back(N);
2230 // MatchScopes - Scopes used when matching, if a match failure happens, this
2231 // indicates where to continue checking.
2232 SmallVector<MatchScope, 8> MatchScopes;
2234 // RecordedNodes - This is the set of nodes that have been recorded by the
2235 // state machine. The second value is the parent of the node, or null if the
2236 // root is recorded.
2237 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2239 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2241 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2243 // These are the current input chain and glue for use when generating nodes.
2244 // Various Emit operations change these. For example, emitting a copytoreg
2245 // uses and updates these.
2246 SDValue InputChain, InputGlue;
2248 // ChainNodesMatched - If a pattern matches nodes that have input/output
2249 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2250 // which ones they are. The result is captured into this list so that we can
2251 // update the chain results when the pattern is complete.
2252 SmallVector<SDNode*, 3> ChainNodesMatched;
2253 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2255 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2256 NodeToMatch->dump(CurDAG);
2259 // Determine where to start the interpreter. Normally we start at opcode #0,
2260 // but if the state machine starts with an OPC_SwitchOpcode, then we
2261 // accelerate the first lookup (which is guaranteed to be hot) with the
2262 // OpcodeOffset table.
2263 unsigned MatcherIndex = 0;
2265 if (!OpcodeOffset.empty()) {
2266 // Already computed the OpcodeOffset table, just index into it.
2267 if (N.getOpcode() < OpcodeOffset.size())
2268 MatcherIndex = OpcodeOffset[N.getOpcode()];
2269 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2271 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2272 // Otherwise, the table isn't computed, but the state machine does start
2273 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2274 // is the first time we're selecting an instruction.
2277 // Get the size of this case.
2278 unsigned CaseSize = MatcherTable[Idx++];
2280 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2281 if (CaseSize == 0) break;
2283 // Get the opcode, add the index to the table.
2284 uint16_t Opc = MatcherTable[Idx++];
2285 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2286 if (Opc >= OpcodeOffset.size())
2287 OpcodeOffset.resize((Opc+1)*2);
2288 OpcodeOffset[Opc] = Idx;
2292 // Okay, do the lookup for the first opcode.
2293 if (N.getOpcode() < OpcodeOffset.size())
2294 MatcherIndex = OpcodeOffset[N.getOpcode()];
2298 assert(MatcherIndex < TableSize && "Invalid index");
2300 unsigned CurrentOpcodeIndex = MatcherIndex;
2302 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2305 // Okay, the semantics of this operation are that we should push a scope
2306 // then evaluate the first child. However, pushing a scope only to have
2307 // the first check fail (which then pops it) is inefficient. If we can
2308 // determine immediately that the first check (or first several) will
2309 // immediately fail, don't even bother pushing a scope for them.
2313 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2314 if (NumToSkip & 128)
2315 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2316 // Found the end of the scope with no match.
2317 if (NumToSkip == 0) {
2322 FailIndex = MatcherIndex+NumToSkip;
2324 unsigned MatcherIndexOfPredicate = MatcherIndex;
2325 (void)MatcherIndexOfPredicate; // silence warning.
2327 // If we can't evaluate this predicate without pushing a scope (e.g. if
2328 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2329 // push the scope and evaluate the full predicate chain.
2331 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2332 Result, *this, RecordedNodes);
2336 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2337 << "index " << MatcherIndexOfPredicate
2338 << ", continuing at " << FailIndex << "\n");
2339 ++NumDAGIselRetries;
2341 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2342 // move to the next case.
2343 MatcherIndex = FailIndex;
2346 // If the whole scope failed to match, bail.
2347 if (FailIndex == 0) break;
2349 // Push a MatchScope which indicates where to go if the first child fails
2351 MatchScope NewEntry;
2352 NewEntry.FailIndex = FailIndex;
2353 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2354 NewEntry.NumRecordedNodes = RecordedNodes.size();
2355 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2356 NewEntry.InputChain = InputChain;
2357 NewEntry.InputGlue = InputGlue;
2358 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2359 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2360 MatchScopes.push_back(NewEntry);
2363 case OPC_RecordNode: {
2364 // Remember this node, it may end up being an operand in the pattern.
2366 if (NodeStack.size() > 1)
2367 Parent = NodeStack[NodeStack.size()-2].getNode();
2368 RecordedNodes.push_back(std::make_pair(N, Parent));
2372 case OPC_RecordChild0: case OPC_RecordChild1:
2373 case OPC_RecordChild2: case OPC_RecordChild3:
2374 case OPC_RecordChild4: case OPC_RecordChild5:
2375 case OPC_RecordChild6: case OPC_RecordChild7: {
2376 unsigned ChildNo = Opcode-OPC_RecordChild0;
2377 if (ChildNo >= N.getNumOperands())
2378 break; // Match fails if out of range child #.
2380 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2384 case OPC_RecordMemRef:
2385 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2388 case OPC_CaptureGlueInput:
2389 // If the current node has an input glue, capture it in InputGlue.
2390 if (N->getNumOperands() != 0 &&
2391 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2392 InputGlue = N->getOperand(N->getNumOperands()-1);
2395 case OPC_MoveChild: {
2396 unsigned ChildNo = MatcherTable[MatcherIndex++];
2397 if (ChildNo >= N.getNumOperands())
2398 break; // Match fails if out of range child #.
2399 N = N.getOperand(ChildNo);
2400 NodeStack.push_back(N);
2404 case OPC_MoveParent:
2405 // Pop the current node off the NodeStack.
2406 NodeStack.pop_back();
2407 assert(!NodeStack.empty() && "Node stack imbalance!");
2408 N = NodeStack.back();
2412 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2414 case OPC_CheckPatternPredicate:
2415 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2417 case OPC_CheckPredicate:
2418 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2422 case OPC_CheckComplexPat: {
2423 unsigned CPNum = MatcherTable[MatcherIndex++];
2424 unsigned RecNo = MatcherTable[MatcherIndex++];
2425 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2426 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2427 RecordedNodes[RecNo].first, CPNum,
2432 case OPC_CheckOpcode:
2433 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2437 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2440 case OPC_SwitchOpcode: {
2441 unsigned CurNodeOpcode = N.getOpcode();
2442 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2445 // Get the size of this case.
2446 CaseSize = MatcherTable[MatcherIndex++];
2448 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2449 if (CaseSize == 0) break;
2451 uint16_t Opc = MatcherTable[MatcherIndex++];
2452 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2454 // If the opcode matches, then we will execute this case.
2455 if (CurNodeOpcode == Opc)
2458 // Otherwise, skip over this case.
2459 MatcherIndex += CaseSize;
2462 // If no cases matched, bail out.
2463 if (CaseSize == 0) break;
2465 // Otherwise, execute the case we found.
2466 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2467 << " to " << MatcherIndex << "\n");
2471 case OPC_SwitchType: {
2472 MVT CurNodeVT = N.getValueType().getSimpleVT();
2473 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2476 // Get the size of this case.
2477 CaseSize = MatcherTable[MatcherIndex++];
2479 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2480 if (CaseSize == 0) break;
2482 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2483 if (CaseVT == MVT::iPTR)
2484 CaseVT = TLI.getPointerTy();
2486 // If the VT matches, then we will execute this case.
2487 if (CurNodeVT == CaseVT)
2490 // Otherwise, skip over this case.
2491 MatcherIndex += CaseSize;
2494 // If no cases matched, bail out.
2495 if (CaseSize == 0) break;
2497 // Otherwise, execute the case we found.
2498 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2499 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2502 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2503 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2504 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2505 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2506 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2507 Opcode-OPC_CheckChild0Type))
2510 case OPC_CheckCondCode:
2511 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2513 case OPC_CheckValueType:
2514 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2516 case OPC_CheckInteger:
2517 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2519 case OPC_CheckAndImm:
2520 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2522 case OPC_CheckOrImm:
2523 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2526 case OPC_CheckFoldableChainNode: {
2527 assert(NodeStack.size() != 1 && "No parent node");
2528 // Verify that all intermediate nodes between the root and this one have
2530 bool HasMultipleUses = false;
2531 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2532 if (!NodeStack[i].hasOneUse()) {
2533 HasMultipleUses = true;
2536 if (HasMultipleUses) break;
2538 // Check to see that the target thinks this is profitable to fold and that
2539 // we can fold it without inducing cycles in the graph.
2540 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2542 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2543 NodeToMatch, OptLevel,
2544 true/*We validate our own chains*/))
2549 case OPC_EmitInteger: {
2550 MVT::SimpleValueType VT =
2551 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2552 int64_t Val = MatcherTable[MatcherIndex++];
2554 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2555 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2556 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2559 case OPC_EmitRegister: {
2560 MVT::SimpleValueType VT =
2561 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2562 unsigned RegNo = MatcherTable[MatcherIndex++];
2563 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2564 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2567 case OPC_EmitRegister2: {
2568 // For targets w/ more than 256 register names, the register enum
2569 // values are stored in two bytes in the matcher table (just like
2571 MVT::SimpleValueType VT =
2572 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2573 unsigned RegNo = MatcherTable[MatcherIndex++];
2574 RegNo |= MatcherTable[MatcherIndex++] << 8;
2575 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2576 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2580 case OPC_EmitConvertToTarget: {
2581 // Convert from IMM/FPIMM to target version.
2582 unsigned RecNo = MatcherTable[MatcherIndex++];
2583 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2584 SDValue Imm = RecordedNodes[RecNo].first;
2586 if (Imm->getOpcode() == ISD::Constant) {
2587 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2588 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2589 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2590 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2591 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2594 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2598 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2599 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2600 // These are space-optimized forms of OPC_EmitMergeInputChains.
2601 assert(InputChain.getNode() == 0 &&
2602 "EmitMergeInputChains should be the first chain producing node");
2603 assert(ChainNodesMatched.empty() &&
2604 "Should only have one EmitMergeInputChains per match");
2606 // Read all of the chained nodes.
2607 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2608 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2609 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2611 // FIXME: What if other value results of the node have uses not matched
2613 if (ChainNodesMatched.back() != NodeToMatch &&
2614 !RecordedNodes[RecNo].first.hasOneUse()) {
2615 ChainNodesMatched.clear();
2619 // Merge the input chains if they are not intra-pattern references.
2620 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2622 if (InputChain.getNode() == 0)
2623 break; // Failed to merge.
2627 case OPC_EmitMergeInputChains: {
2628 assert(InputChain.getNode() == 0 &&
2629 "EmitMergeInputChains should be the first chain producing node");
2630 // This node gets a list of nodes we matched in the input that have
2631 // chains. We want to token factor all of the input chains to these nodes
2632 // together. However, if any of the input chains is actually one of the
2633 // nodes matched in this pattern, then we have an intra-match reference.
2634 // Ignore these because the newly token factored chain should not refer to
2636 unsigned NumChains = MatcherTable[MatcherIndex++];
2637 assert(NumChains != 0 && "Can't TF zero chains");
2639 assert(ChainNodesMatched.empty() &&
2640 "Should only have one EmitMergeInputChains per match");
2642 // Read all of the chained nodes.
2643 for (unsigned i = 0; i != NumChains; ++i) {
2644 unsigned RecNo = MatcherTable[MatcherIndex++];
2645 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2646 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2648 // FIXME: What if other value results of the node have uses not matched
2650 if (ChainNodesMatched.back() != NodeToMatch &&
2651 !RecordedNodes[RecNo].first.hasOneUse()) {
2652 ChainNodesMatched.clear();
2657 // If the inner loop broke out, the match fails.
2658 if (ChainNodesMatched.empty())
2661 // Merge the input chains if they are not intra-pattern references.
2662 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2664 if (InputChain.getNode() == 0)
2665 break; // Failed to merge.
2670 case OPC_EmitCopyToReg: {
2671 unsigned RecNo = MatcherTable[MatcherIndex++];
2672 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2673 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2675 if (InputChain.getNode() == 0)
2676 InputChain = CurDAG->getEntryNode();
2678 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2679 DestPhysReg, RecordedNodes[RecNo].first,
2682 InputGlue = InputChain.getValue(1);
2686 case OPC_EmitNodeXForm: {
2687 unsigned XFormNo = MatcherTable[MatcherIndex++];
2688 unsigned RecNo = MatcherTable[MatcherIndex++];
2689 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2690 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2691 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2696 case OPC_MorphNodeTo: {
2697 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2698 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2699 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2700 // Get the result VT list.
2701 unsigned NumVTs = MatcherTable[MatcherIndex++];
2702 SmallVector<EVT, 4> VTs;
2703 for (unsigned i = 0; i != NumVTs; ++i) {
2704 MVT::SimpleValueType VT =
2705 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2706 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2710 if (EmitNodeInfo & OPFL_Chain)
2711 VTs.push_back(MVT::Other);
2712 if (EmitNodeInfo & OPFL_GlueOutput)
2713 VTs.push_back(MVT::Glue);
2715 // This is hot code, so optimize the two most common cases of 1 and 2
2718 if (VTs.size() == 1)
2719 VTList = CurDAG->getVTList(VTs[0]);
2720 else if (VTs.size() == 2)
2721 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2723 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2725 // Get the operand list.
2726 unsigned NumOps = MatcherTable[MatcherIndex++];
2727 SmallVector<SDValue, 8> Ops;
2728 for (unsigned i = 0; i != NumOps; ++i) {
2729 unsigned RecNo = MatcherTable[MatcherIndex++];
2731 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2733 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2734 Ops.push_back(RecordedNodes[RecNo].first);
2737 // If there are variadic operands to add, handle them now.
2738 if (EmitNodeInfo & OPFL_VariadicInfo) {
2739 // Determine the start index to copy from.
2740 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2741 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2742 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2743 "Invalid variadic node");
2744 // Copy all of the variadic operands, not including a potential glue
2746 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2748 SDValue V = NodeToMatch->getOperand(i);
2749 if (V.getValueType() == MVT::Glue) break;
2754 // If this has chain/glue inputs, add them.
2755 if (EmitNodeInfo & OPFL_Chain)
2756 Ops.push_back(InputChain);
2757 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2758 Ops.push_back(InputGlue);
2762 if (Opcode != OPC_MorphNodeTo) {
2763 // If this is a normal EmitNode command, just create the new node and
2764 // add the results to the RecordedNodes list.
2765 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2766 VTList, Ops.data(), Ops.size());
2768 // Add all the non-glue/non-chain results to the RecordedNodes list.
2769 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2770 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2771 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2775 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2776 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2779 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2780 // We will visit the equivalent node later.
2781 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2785 // If the node had chain/glue results, update our notion of the current
2787 if (EmitNodeInfo & OPFL_GlueOutput) {
2788 InputGlue = SDValue(Res, VTs.size()-1);
2789 if (EmitNodeInfo & OPFL_Chain)
2790 InputChain = SDValue(Res, VTs.size()-2);
2791 } else if (EmitNodeInfo & OPFL_Chain)
2792 InputChain = SDValue(Res, VTs.size()-1);
2794 // If the OPFL_MemRefs glue is set on this node, slap all of the
2795 // accumulated memrefs onto it.
2797 // FIXME: This is vastly incorrect for patterns with multiple outputs
2798 // instructions that access memory and for ComplexPatterns that match
2800 if (EmitNodeInfo & OPFL_MemRefs) {
2801 // Only attach load or store memory operands if the generated
2802 // instruction may load or store.
2803 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2804 bool mayLoad = MCID.mayLoad();
2805 bool mayStore = MCID.mayStore();
2807 unsigned NumMemRefs = 0;
2808 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2809 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2810 if ((*I)->isLoad()) {
2813 } else if ((*I)->isStore()) {
2821 MachineSDNode::mmo_iterator MemRefs =
2822 MF->allocateMemRefsArray(NumMemRefs);
2824 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2825 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2826 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2827 if ((*I)->isLoad()) {
2830 } else if ((*I)->isStore()) {
2838 cast<MachineSDNode>(Res)
2839 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2843 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2844 << " node: "; Res->dump(CurDAG); errs() << "\n");
2846 // If this was a MorphNodeTo then we're completely done!
2847 if (Opcode == OPC_MorphNodeTo) {
2848 // Update chain and glue uses.
2849 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2850 InputGlue, GlueResultNodesMatched, true);
2857 case OPC_MarkGlueResults: {
2858 unsigned NumNodes = MatcherTable[MatcherIndex++];
2860 // Read and remember all the glue-result nodes.
2861 for (unsigned i = 0; i != NumNodes; ++i) {
2862 unsigned RecNo = MatcherTable[MatcherIndex++];
2864 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2866 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2867 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2872 case OPC_CompleteMatch: {
2873 // The match has been completed, and any new nodes (if any) have been
2874 // created. Patch up references to the matched dag to use the newly
2876 unsigned NumResults = MatcherTable[MatcherIndex++];
2878 for (unsigned i = 0; i != NumResults; ++i) {
2879 unsigned ResSlot = MatcherTable[MatcherIndex++];
2881 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2883 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2884 SDValue Res = RecordedNodes[ResSlot].first;
2886 assert(i < NodeToMatch->getNumValues() &&
2887 NodeToMatch->getValueType(i) != MVT::Other &&
2888 NodeToMatch->getValueType(i) != MVT::Glue &&
2889 "Invalid number of results to complete!");
2890 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2891 NodeToMatch->getValueType(i) == MVT::iPTR ||
2892 Res.getValueType() == MVT::iPTR ||
2893 NodeToMatch->getValueType(i).getSizeInBits() ==
2894 Res.getValueType().getSizeInBits()) &&
2895 "invalid replacement");
2896 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2899 // If the root node defines glue, add it to the glue nodes to update list.
2900 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2901 GlueResultNodesMatched.push_back(NodeToMatch);
2903 // Update chain and glue uses.
2904 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2905 InputGlue, GlueResultNodesMatched, false);
2907 assert(NodeToMatch->use_empty() &&
2908 "Didn't replace all uses of the node?");
2910 // FIXME: We just return here, which interacts correctly with SelectRoot
2911 // above. We should fix this to not return an SDNode* anymore.
2916 // If the code reached this point, then the match failed. See if there is
2917 // another child to try in the current 'Scope', otherwise pop it until we
2918 // find a case to check.
2919 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2920 ++NumDAGIselRetries;
2922 if (MatchScopes.empty()) {
2923 CannotYetSelect(NodeToMatch);
2927 // Restore the interpreter state back to the point where the scope was
2929 MatchScope &LastScope = MatchScopes.back();
2930 RecordedNodes.resize(LastScope.NumRecordedNodes);
2932 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2933 N = NodeStack.back();
2935 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2936 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2937 MatcherIndex = LastScope.FailIndex;
2939 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2941 InputChain = LastScope.InputChain;
2942 InputGlue = LastScope.InputGlue;
2943 if (!LastScope.HasChainNodesMatched)
2944 ChainNodesMatched.clear();
2945 if (!LastScope.HasGlueResultNodesMatched)
2946 GlueResultNodesMatched.clear();
2948 // Check to see what the offset is at the new MatcherIndex. If it is zero
2949 // we have reached the end of this scope, otherwise we have another child
2950 // in the current scope to try.
2951 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2952 if (NumToSkip & 128)
2953 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2955 // If we have another child in this scope to match, update FailIndex and
2957 if (NumToSkip != 0) {
2958 LastScope.FailIndex = MatcherIndex+NumToSkip;
2962 // End of this scope, pop it and try the next child in the containing
2964 MatchScopes.pop_back();
2971 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2973 raw_string_ostream Msg(msg);
2974 Msg << "Cannot select: ";
2976 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2977 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2978 N->getOpcode() != ISD::INTRINSIC_VOID) {
2979 N->printrFull(Msg, CurDAG);
2980 Msg << "\nIn function: " << MF->getName();
2982 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2984 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2985 if (iid < Intrinsic::num_intrinsics)
2986 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2987 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2988 Msg << "target intrinsic %" << TII->getName(iid);
2990 Msg << "unknown intrinsic #" << iid;
2992 report_fatal_error(Msg.str());
2995 char SelectionDAGISel::ID = 0;