1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/IntrinsicInst.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/GCStrategy.h"
33 #include "llvm/CodeGen/GCMetadata.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineJumpTableInfo.h"
39 #include "llvm/CodeGen/MachineModuleInfo.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
42 #include "llvm/CodeGen/SchedulerRegistry.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/CodeGen/DwarfWriter.h"
45 #include "llvm/Target/TargetRegisterInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameInfo.h"
48 #include "llvm/Target/TargetIntrinsicInfo.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetLowering.h"
51 #include "llvm/Target/TargetMachine.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/Timer.h"
58 #include "llvm/Support/raw_ostream.h"
63 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
64 cl::desc("Enable verbose messages in the \"fast\" "
65 "instruction selector"));
67 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
68 cl::desc("Enable abort calls when \"fast\" instruction fails"));
70 SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
71 cl::desc("Schedule copies of livein registers"),
76 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
77 cl::desc("Pop up a window to show dags before the first "
80 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before legalize types"));
83 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before legalize"));
86 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
87 cl::desc("Pop up a window to show dags before the second "
90 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
91 cl::desc("Pop up a window to show dags before the post legalize types"
92 " dag combine pass"));
94 ViewISelDAGs("view-isel-dags", cl::Hidden,
95 cl::desc("Pop up a window to show isel dags as they are selected"));
97 ViewSchedDAGs("view-sched-dags", cl::Hidden,
98 cl::desc("Pop up a window to show sched dags as they are processed"));
100 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
101 cl::desc("Pop up a window to show SUnit dags after they are processed"));
103 static const bool ViewDAGCombine1 = false,
104 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
105 ViewDAGCombine2 = false,
106 ViewDAGCombineLT = false,
107 ViewISelDAGs = false, ViewSchedDAGs = false,
108 ViewSUnitDAGs = false;
111 //===---------------------------------------------------------------------===//
113 /// RegisterScheduler class - Track the registration of instruction schedulers.
115 //===---------------------------------------------------------------------===//
116 MachinePassRegistry RegisterScheduler::Registry;
118 //===---------------------------------------------------------------------===//
120 /// ISHeuristic command line option for instruction schedulers.
122 //===---------------------------------------------------------------------===//
123 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
124 RegisterPassParser<RegisterScheduler> >
125 ISHeuristic("pre-RA-sched",
126 cl::init(&createDefaultScheduler),
127 cl::desc("Instruction schedulers available (before register"
130 static RegisterScheduler
131 defaultListDAGScheduler("default", "Best scheduler for the target",
132 createDefaultScheduler);
135 //===--------------------------------------------------------------------===//
136 /// createDefaultScheduler - This creates an instruction scheduler appropriate
138 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
139 CodeGenOpt::Level OptLevel) {
140 const TargetLowering &TLI = IS->getTargetLowering();
142 if (OptLevel == CodeGenOpt::None)
143 return createFastDAGScheduler(IS, OptLevel);
144 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
145 return createTDListDAGScheduler(IS, OptLevel);
146 assert(TLI.getSchedulingPreference() ==
147 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
148 return createBURRListDAGScheduler(IS, OptLevel);
152 // EmitInstrWithCustomInserter - This method should be implemented by targets
153 // that mark instructions with the 'usesCustomInserter' flag. These
154 // instructions are special in various ways, which require special support to
155 // insert. The specified MachineInstr is created but not inserted into any
156 // basic blocks, and this method is called to expand it into a sequence of
157 // instructions, potentially also creating new basic blocks and control flow.
158 // When new basic blocks are inserted and the edges from MBB to its successors
159 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
161 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
162 MachineBasicBlock *MBB,
163 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
165 errs() << "If a target marks an instruction with "
166 "'usesCustomInserter', it must implement "
167 "TargetLowering::EmitInstrWithCustomInserter!";
173 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
174 /// physical register has only a single copy use, then coalesced the copy
176 static void EmitLiveInCopy(MachineBasicBlock *MBB,
177 MachineBasicBlock::iterator &InsertPos,
178 unsigned VirtReg, unsigned PhysReg,
179 const TargetRegisterClass *RC,
180 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
181 const MachineRegisterInfo &MRI,
182 const TargetRegisterInfo &TRI,
183 const TargetInstrInfo &TII) {
184 unsigned NumUses = 0;
185 MachineInstr *UseMI = NULL;
186 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
187 UE = MRI.use_end(); UI != UE; ++UI) {
193 // If the number of uses is not one, or the use is not a move instruction,
194 // don't coalesce. Also, only coalesce away a virtual register to virtual
196 bool Coalesced = false;
197 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
199 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
200 TargetRegisterInfo::isVirtualRegister(DstReg)) {
205 // Now find an ideal location to insert the copy.
206 MachineBasicBlock::iterator Pos = InsertPos;
207 while (Pos != MBB->begin()) {
208 MachineInstr *PrevMI = prior(Pos);
209 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
210 // copyRegToReg might emit multiple instructions to do a copy.
211 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
212 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
213 // This is what the BB looks like right now:
218 // We want to insert "r1025 = mov r1". Inserting this copy below the
219 // move to r1024 makes it impossible for that move to be coalesced.
226 break; // Woot! Found a good location.
230 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
231 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
234 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
236 if (&*InsertPos == UseMI) ++InsertPos;
241 /// EmitLiveInCopies - If this is the first basic block in the function,
242 /// and if it has live ins that need to be copied into vregs, emit the
243 /// copies into the block.
244 static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
245 const MachineRegisterInfo &MRI,
246 const TargetRegisterInfo &TRI,
247 const TargetInstrInfo &TII) {
248 if (SchedLiveInCopies) {
249 // Emit the copies at a heuristically-determined location in the block.
250 DenseMap<MachineInstr*, unsigned> CopyRegMap;
251 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
252 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
253 E = MRI.livein_end(); LI != E; ++LI)
255 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
256 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
257 RC, CopyRegMap, MRI, TRI, TII);
260 // Emit the copies into the top of the block.
261 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
262 E = MRI.livein_end(); LI != E; ++LI)
264 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
265 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
266 LI->second, LI->first, RC, RC);
267 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
273 //===----------------------------------------------------------------------===//
274 // SelectionDAGISel code
275 //===----------------------------------------------------------------------===//
277 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
278 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
279 FuncInfo(new FunctionLoweringInfo(TLI)),
280 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
281 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
287 SelectionDAGISel::~SelectionDAGISel() {
293 unsigned SelectionDAGISel::MakeReg(EVT VT) {
294 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
297 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
298 AU.addRequired<AliasAnalysis>();
299 AU.addPreserved<AliasAnalysis>();
300 AU.addRequired<GCModuleInfo>();
301 AU.addPreserved<GCModuleInfo>();
302 AU.addRequired<DwarfWriter>();
303 AU.addPreserved<DwarfWriter>();
304 MachineFunctionPass::getAnalysisUsage(AU);
307 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
308 Function &Fn = *mf.getFunction();
310 // Do some sanity-checking on the command-line options.
311 assert((!EnableFastISelVerbose || EnableFastISel) &&
312 "-fast-isel-verbose requires -fast-isel");
313 assert((!EnableFastISelAbort || EnableFastISel) &&
314 "-fast-isel-abort requires -fast-isel");
316 // Get alias analysis for load/store combining.
317 AA = &getAnalysis<AliasAnalysis>();
320 const TargetInstrInfo &TII = *TM.getInstrInfo();
321 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
324 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn);
327 RegInfo = &MF->getRegInfo();
328 DEBUG(errs() << "\n\n\n=== " << Fn.getName() << "\n");
330 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>();
331 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>();
332 CurDAG->init(*MF, MMI, DW);
333 FuncInfo->set(Fn, *MF, EnableFastISel);
336 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
337 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
339 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
341 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII);
343 // If the first basic block in the function has live ins that need to be
344 // copied into vregs, emit the copies into the top of the block before
345 // emitting the code for the block.
346 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII);
348 // Add function live-ins to entry block live-in set.
349 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
350 E = RegInfo->livein_end(); I != E; ++I)
351 MF->begin()->addLiveIn(I->first);
354 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
355 "Not all catch info was assigned to a landing pad!");
363 /// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
364 /// attached with this instruction.
365 static void SetDebugLoc(unsigned MDDbgKind,
366 MetadataContext &TheMetadata,
368 SelectionDAGBuilder *SDB,
370 MachineFunction *MF) {
371 if (!isa<DbgInfoIntrinsic>(I))
372 if (MDNode *Dbg = TheMetadata.getMD(MDDbgKind, I)) {
373 DILocation DILoc(Dbg);
374 DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo());
376 SDB->setCurDebugLoc(Loc);
379 FastIS->setCurDebugLoc(Loc);
381 // If the function doesn't have a default debug location yet, set
382 // it. This is kind of a hack.
383 if (MF->getDefaultDebugLoc().isUnknown())
384 MF->setDefaultDebugLoc(Loc);
388 /// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
389 static void ResetDebugLoc(SelectionDAGBuilder *SDB,
391 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc());
393 SDB->setCurDebugLoc(DebugLoc::getUnknownLoc());
396 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
397 BasicBlock::iterator Begin,
398 BasicBlock::iterator End,
400 SDB->setCurrentBasicBlock(BB);
401 MetadataContext &TheMetadata = LLVMBB->getParent()->getContext().getMetadata();
402 unsigned MDDbgKind = TheMetadata.getMDKind("dbg");
404 // Lower all of the non-terminator instructions. If a call is emitted
405 // as a tail call, cease emitting nodes for this block.
406 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
408 SetDebugLoc(MDDbgKind, TheMetadata, I, SDB, 0, MF);
410 if (!isa<TerminatorInst>(I)) {
413 // Set the current debug location back to "unknown" so that it doesn't
414 // spuriously apply to subsequent instructions.
415 ResetDebugLoc(SDB, 0);
419 if (!SDB->HasTailCall) {
420 // Ensure that all instructions which are used outside of their defining
421 // blocks are available as virtual registers. Invoke is handled elsewhere.
422 for (BasicBlock::iterator I = Begin; I != End; ++I)
423 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
424 SDB->CopyToExportRegsIfNeeded(I);
426 // Handle PHI nodes in successor blocks.
427 if (End == LLVMBB->end()) {
428 HandlePHINodesInSuccessorBlocks(LLVMBB);
430 // Lower the terminator after the copies are emitted.
431 SetDebugLoc(MDDbgKind, TheMetadata, LLVMBB->getTerminator(), SDB, 0, MF);
432 SDB->visit(*LLVMBB->getTerminator());
433 ResetDebugLoc(SDB, 0);
437 // Make sure the root of the DAG is up-to-date.
438 CurDAG->setRoot(SDB->getControlRoot());
440 // Final step, emit the lowered DAG as machine code.
442 HadTailCall = SDB->HasTailCall;
446 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
447 SmallPtrSet<SDNode*, 128> VisitedNodes;
448 SmallVector<SDNode*, 128> Worklist;
450 Worklist.push_back(CurDAG->getRoot().getNode());
456 while (!Worklist.empty()) {
457 SDNode *N = Worklist.back();
460 // If we've already seen this node, ignore it.
461 if (!VisitedNodes.insert(N))
464 // Otherwise, add all chain operands to the worklist.
465 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
466 if (N->getOperand(i).getValueType() == MVT::Other)
467 Worklist.push_back(N->getOperand(i).getNode());
469 // If this is a CopyToReg with a vreg dest, process it.
470 if (N->getOpcode() != ISD::CopyToReg)
473 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
474 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
477 // Ignore non-scalar or non-integer values.
478 SDValue Src = N->getOperand(2);
479 EVT SrcVT = Src.getValueType();
480 if (!SrcVT.isInteger() || SrcVT.isVector())
483 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
484 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
485 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
487 // Only install this information if it tells us something.
488 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
489 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
490 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
491 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
492 FunctionLoweringInfo::LiveOutInfo &LOI =
493 FuncInfo->LiveOutRegInfo[DestReg];
494 LOI.NumSignBits = NumSignBits;
495 LOI.KnownOne = KnownOne;
496 LOI.KnownZero = KnownZero;
501 void SelectionDAGISel::CodeGenAndEmitDAG() {
502 std::string GroupName;
503 if (TimePassesIsEnabled)
504 GroupName = "Instruction Selection and Scheduling";
505 std::string BlockName;
506 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
507 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
509 BlockName = MF->getFunction()->getNameStr() + ":" +
510 BB->getBasicBlock()->getNameStr();
512 DEBUG(errs() << "Initial selection DAG:\n");
513 DEBUG(CurDAG->dump());
515 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
517 // Run the DAG combiner in pre-legalize mode.
518 if (TimePassesIsEnabled) {
519 NamedRegionTimer T("DAG Combining 1", GroupName);
520 CurDAG->Combine(Unrestricted, *AA, OptLevel);
522 CurDAG->Combine(Unrestricted, *AA, OptLevel);
525 DEBUG(errs() << "Optimized lowered selection DAG:\n");
526 DEBUG(CurDAG->dump());
528 // Second step, hack on the DAG until it only uses operations and types that
529 // the target supports.
530 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
534 if (TimePassesIsEnabled) {
535 NamedRegionTimer T("Type Legalization", GroupName);
536 Changed = CurDAG->LegalizeTypes();
538 Changed = CurDAG->LegalizeTypes();
541 DEBUG(errs() << "Type-legalized selection DAG:\n");
542 DEBUG(CurDAG->dump());
545 if (ViewDAGCombineLT)
546 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
548 // Run the DAG combiner in post-type-legalize mode.
549 if (TimePassesIsEnabled) {
550 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
551 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
553 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
556 DEBUG(errs() << "Optimized type-legalized selection DAG:\n");
557 DEBUG(CurDAG->dump());
560 if (TimePassesIsEnabled) {
561 NamedRegionTimer T("Vector Legalization", GroupName);
562 Changed = CurDAG->LegalizeVectors();
564 Changed = CurDAG->LegalizeVectors();
568 if (TimePassesIsEnabled) {
569 NamedRegionTimer T("Type Legalization 2", GroupName);
570 Changed = CurDAG->LegalizeTypes();
572 Changed = CurDAG->LegalizeTypes();
575 if (ViewDAGCombineLT)
576 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
578 // Run the DAG combiner in post-type-legalize mode.
579 if (TimePassesIsEnabled) {
580 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
581 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
583 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
586 DEBUG(errs() << "Optimized vector-legalized selection DAG:\n");
587 DEBUG(CurDAG->dump());
590 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
592 if (TimePassesIsEnabled) {
593 NamedRegionTimer T("DAG Legalization", GroupName);
594 CurDAG->Legalize(OptLevel);
596 CurDAG->Legalize(OptLevel);
599 DEBUG(errs() << "Legalized selection DAG:\n");
600 DEBUG(CurDAG->dump());
602 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
604 // Run the DAG combiner in post-legalize mode.
605 if (TimePassesIsEnabled) {
606 NamedRegionTimer T("DAG Combining 2", GroupName);
607 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
609 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
612 DEBUG(errs() << "Optimized legalized selection DAG:\n");
613 DEBUG(CurDAG->dump());
615 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
617 if (OptLevel != CodeGenOpt::None)
618 ComputeLiveOutVRegInfo();
620 // Third, instruction select all of the operations to machine code, adding the
621 // code to the MachineBasicBlock.
622 if (TimePassesIsEnabled) {
623 NamedRegionTimer T("Instruction Selection", GroupName);
629 DEBUG(errs() << "Selected selection DAG:\n");
630 DEBUG(CurDAG->dump());
632 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
634 // Schedule machine code.
635 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
636 if (TimePassesIsEnabled) {
637 NamedRegionTimer T("Instruction Scheduling", GroupName);
638 Scheduler->Run(CurDAG, BB, BB->end());
640 Scheduler->Run(CurDAG, BB, BB->end());
643 if (ViewSUnitDAGs) Scheduler->viewGraph();
645 // Emit machine code to BB. This can change 'BB' to the last block being
647 if (TimePassesIsEnabled) {
648 NamedRegionTimer T("Instruction Creation", GroupName);
649 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
651 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
654 // Free the scheduler state.
655 if (TimePassesIsEnabled) {
656 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
662 DEBUG(errs() << "Selected machine code:\n");
666 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
668 MachineModuleInfo *MMI,
670 const TargetInstrInfo &TII) {
671 // Initialize the Fast-ISel state, if needed.
672 FastISel *FastIS = 0;
674 FastIS = TLI.createFastISel(MF, MMI, DW,
677 FuncInfo->StaticAllocaMap
679 , FuncInfo->CatchInfoLost
683 MetadataContext &TheMetadata = Fn.getContext().getMetadata();
684 unsigned MDDbgKind = TheMetadata.getMDKind("dbg");
686 // Iterate over all basic blocks in the function.
687 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
688 BasicBlock *LLVMBB = &*I;
689 BB = FuncInfo->MBBMap[LLVMBB];
691 BasicBlock::iterator const Begin = LLVMBB->begin();
692 BasicBlock::iterator const End = LLVMBB->end();
693 BasicBlock::iterator BI = Begin;
695 // Lower any arguments needed in this block if this is the entry block.
696 bool SuppressFastISel = false;
697 if (LLVMBB == &Fn.getEntryBlock()) {
698 LowerArguments(LLVMBB);
700 // If any of the arguments has the byval attribute, forgo
701 // fast-isel in the entry block.
704 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
706 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
707 if (EnableFastISelVerbose || EnableFastISelAbort)
708 errs() << "FastISel skips entry block due to byval argument\n";
709 SuppressFastISel = true;
715 if (MMI && BB->isLandingPad()) {
716 // Add a label to mark the beginning of the landing pad. Deletion of the
717 // landing pad can thus be detected via the MachineModuleInfo.
718 unsigned LabelID = MMI->addLandingPad(BB);
720 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL);
721 BuildMI(BB, SDB->getCurDebugLoc(), II).addImm(LabelID);
723 // Mark exception register as live in.
724 unsigned Reg = TLI.getExceptionAddressRegister();
725 if (Reg) BB->addLiveIn(Reg);
727 // Mark exception selector register as live in.
728 Reg = TLI.getExceptionSelectorRegister();
729 if (Reg) BB->addLiveIn(Reg);
731 // FIXME: Hack around an exception handling flaw (PR1508): the personality
732 // function and list of typeids logically belong to the invoke (or, if you
733 // like, the basic block containing the invoke), and need to be associated
734 // with it in the dwarf exception handling tables. Currently however the
735 // information is provided by an intrinsic (eh.selector) that can be moved
736 // to unexpected places by the optimizers: if the unwind edge is critical,
737 // then breaking it can result in the intrinsics being in the successor of
738 // the landing pad, not the landing pad itself. This results in exceptions
739 // not being caught because no typeids are associated with the invoke.
740 // This may not be the only way things can go wrong, but it is the only way
741 // we try to work around for the moment.
742 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
744 if (Br && Br->isUnconditional()) { // Critical edge?
745 BasicBlock::iterator I, E;
746 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
747 if (isa<EHSelectorInst>(I))
751 // No catch info found - try to extract some from the successor.
752 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
756 // Before doing SelectionDAG ISel, see if FastISel has been requested.
757 if (FastIS && !SuppressFastISel) {
758 // Emit code for any incoming arguments. This must happen before
759 // beginning FastISel on the entry block.
760 if (LLVMBB == &Fn.getEntryBlock()) {
761 CurDAG->setRoot(SDB->getControlRoot());
765 FastIS->startNewBlock(BB);
766 // Do FastISel on as many instructions as possible.
767 for (; BI != End; ++BI) {
768 // Just before the terminator instruction, insert instructions to
769 // feed PHI nodes in successor blocks.
770 if (isa<TerminatorInst>(BI))
771 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
772 ResetDebugLoc(SDB, FastIS);
773 if (EnableFastISelVerbose || EnableFastISelAbort) {
774 errs() << "FastISel miss: ";
777 assert(!EnableFastISelAbort &&
778 "FastISel didn't handle a PHI in a successor");
783 SetDebugLoc(MDDbgKind, TheMetadata, BI, SDB, FastIS, &MF);
785 // First try normal tablegen-generated "fast" selection.
786 if (FastIS->SelectInstruction(BI)) {
787 ResetDebugLoc(SDB, FastIS);
791 // Clear out the debug location so that it doesn't carry over to
792 // unrelated instructions.
793 ResetDebugLoc(SDB, FastIS);
795 // Then handle certain instructions as single-LLVM-Instruction blocks.
796 if (isa<CallInst>(BI)) {
797 if (EnableFastISelVerbose || EnableFastISelAbort) {
798 errs() << "FastISel missed call: ";
802 if (BI->getType() != Type::getVoidTy(*CurDAG->getContext())) {
803 unsigned &R = FuncInfo->ValueMap[BI];
805 R = FuncInfo->CreateRegForValue(BI);
808 bool HadTailCall = false;
809 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall);
811 // If the call was emitted as a tail call, we're done with the block.
817 // If the instruction was codegen'd with multiple blocks,
818 // inform the FastISel object where to resume inserting.
819 FastIS->setCurrentBlock(BB);
823 // Otherwise, give up on FastISel for the rest of the block.
824 // For now, be a little lenient about non-branch terminators.
825 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
826 if (EnableFastISelVerbose || EnableFastISelAbort) {
827 errs() << "FastISel miss: ";
830 if (EnableFastISelAbort)
831 // The "fast" selector couldn't handle something and bailed.
832 // For the purpose of debugging, just abort.
833 llvm_unreachable("FastISel didn't select the entire block");
839 // Run SelectionDAG instruction selection on the remainder of the block
840 // not handled by FastISel. If FastISel is not run, this is the entire
844 SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
854 SelectionDAGISel::FinishBasicBlock() {
856 DEBUG(errs() << "Target-post-processed machine code:\n");
859 DEBUG(errs() << "Total amount of phi nodes to update: "
860 << SDB->PHINodesToUpdate.size() << "\n");
861 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
862 errs() << "Node " << i << " : ("
863 << SDB->PHINodesToUpdate[i].first
864 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
866 // Next, now that we know what the last MBB the LLVM BB expanded is, update
867 // PHI nodes in successors.
868 if (SDB->SwitchCases.empty() &&
869 SDB->JTCases.empty() &&
870 SDB->BitTestCases.empty()) {
871 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
872 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
873 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
874 "This is not a machine PHI node that we are updating!");
875 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
877 PHI->addOperand(MachineOperand::CreateMBB(BB));
879 SDB->PHINodesToUpdate.clear();
883 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
884 // Lower header first, if it wasn't already lowered
885 if (!SDB->BitTestCases[i].Emitted) {
886 // Set the current basic block to the mbb we wish to insert the code into
887 BB = SDB->BitTestCases[i].Parent;
888 SDB->setCurrentBasicBlock(BB);
890 SDB->visitBitTestHeader(SDB->BitTestCases[i]);
891 CurDAG->setRoot(SDB->getRoot());
896 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
897 // Set the current basic block to the mbb we wish to insert the code into
898 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
899 SDB->setCurrentBasicBlock(BB);
902 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
903 SDB->BitTestCases[i].Reg,
904 SDB->BitTestCases[i].Cases[j]);
906 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
907 SDB->BitTestCases[i].Reg,
908 SDB->BitTestCases[i].Cases[j]);
911 CurDAG->setRoot(SDB->getRoot());
917 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
918 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
919 MachineBasicBlock *PHIBB = PHI->getParent();
920 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
921 "This is not a machine PHI node that we are updating!");
922 // This is "default" BB. We have two jumps to it. From "header" BB and
923 // from last "case" BB.
924 if (PHIBB == SDB->BitTestCases[i].Default) {
925 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second,
927 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
928 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second,
930 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
933 // One of "cases" BB.
934 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
936 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
937 if (cBB->succ_end() !=
938 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
939 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second,
941 PHI->addOperand(MachineOperand::CreateMBB(cBB));
946 SDB->BitTestCases.clear();
948 // If the JumpTable record is filled in, then we need to emit a jump table.
949 // Updating the PHI nodes is tricky in this case, since we need to determine
950 // whether the PHI is a successor of the range check MBB or the jump table MBB
951 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
952 // Lower header first, if it wasn't already lowered
953 if (!SDB->JTCases[i].first.Emitted) {
954 // Set the current basic block to the mbb we wish to insert the code into
955 BB = SDB->JTCases[i].first.HeaderBB;
956 SDB->setCurrentBasicBlock(BB);
958 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
959 CurDAG->setRoot(SDB->getRoot());
964 // Set the current basic block to the mbb we wish to insert the code into
965 BB = SDB->JTCases[i].second.MBB;
966 SDB->setCurrentBasicBlock(BB);
968 SDB->visitJumpTable(SDB->JTCases[i].second);
969 CurDAG->setRoot(SDB->getRoot());
974 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
975 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
976 MachineBasicBlock *PHIBB = PHI->getParent();
977 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
978 "This is not a machine PHI node that we are updating!");
979 // "default" BB. We can go there only from header BB.
980 if (PHIBB == SDB->JTCases[i].second.Default) {
982 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
984 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
986 // JT BB. Just iterate over successors here
987 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
989 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
990 PHI->addOperand(MachineOperand::CreateMBB(BB));
994 SDB->JTCases.clear();
996 // If the switch block involved a branch to one of the actual successors, we
997 // need to update PHI nodes in that block.
998 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
999 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1000 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
1001 "This is not a machine PHI node that we are updating!");
1002 if (BB->isSuccessor(PHI->getParent())) {
1003 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1005 PHI->addOperand(MachineOperand::CreateMBB(BB));
1009 // If we generated any switch lowering information, build and codegen any
1010 // additional DAGs necessary.
1011 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1012 // Set the current basic block to the mbb we wish to insert the code into
1013 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1014 SDB->setCurrentBasicBlock(BB);
1017 SDB->visitSwitchCase(SDB->SwitchCases[i]);
1018 CurDAG->setRoot(SDB->getRoot());
1019 CodeGenAndEmitDAG();
1021 // Handle any PHI nodes in successors of this chunk, as if we were coming
1022 // from the original BB before switch expansion. Note that PHI nodes can
1023 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1024 // handle them the right number of times.
1025 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1026 // If new BB's are created during scheduling, the edges may have been
1027 // updated. That is, the edge from ThisBB to BB may have been split and
1028 // BB's predecessor is now another block.
1029 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1030 SDB->EdgeMapping.find(BB);
1031 if (EI != SDB->EdgeMapping.end())
1032 ThisBB = EI->second;
1033 for (MachineBasicBlock::iterator Phi = BB->begin();
1034 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
1035 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
1036 for (unsigned pn = 0; ; ++pn) {
1037 assert(pn != SDB->PHINodesToUpdate.size() &&
1038 "Didn't find PHI entry!");
1039 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1040 Phi->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[pn].
1042 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1048 // Don't process RHS if same block as LHS.
1049 if (BB == SDB->SwitchCases[i].FalseBB)
1050 SDB->SwitchCases[i].FalseBB = 0;
1052 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1053 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1054 SDB->SwitchCases[i].FalseBB = 0;
1056 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1059 SDB->SwitchCases.clear();
1061 SDB->PHINodesToUpdate.clear();
1065 /// Create the scheduler. If a specific scheduler was specified
1066 /// via the SchedulerRegistry, use it, otherwise select the
1067 /// one preferred by the target.
1069 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1070 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1074 RegisterScheduler::setDefault(Ctor);
1077 return Ctor(this, OptLevel);
1080 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1081 return new ScheduleHazardRecognizer();
1084 //===----------------------------------------------------------------------===//
1085 // Helper functions used by the generated instruction selector.
1086 //===----------------------------------------------------------------------===//
1087 // Calls to these methods are generated by tblgen.
1089 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1090 /// the dag combiner simplified the 255, we still want to match. RHS is the
1091 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1092 /// specified in the .td file (e.g. 255).
1093 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1094 int64_t DesiredMaskS) const {
1095 const APInt &ActualMask = RHS->getAPIntValue();
1096 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1098 // If the actual mask exactly matches, success!
1099 if (ActualMask == DesiredMask)
1102 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1103 if (ActualMask.intersects(~DesiredMask))
1106 // Otherwise, the DAG Combiner may have proven that the value coming in is
1107 // either already zero or is not demanded. Check for known zero input bits.
1108 APInt NeededMask = DesiredMask & ~ActualMask;
1109 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1112 // TODO: check to see if missing bits are just not demanded.
1114 // Otherwise, this pattern doesn't match.
1118 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1119 /// the dag combiner simplified the 255, we still want to match. RHS is the
1120 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1121 /// specified in the .td file (e.g. 255).
1122 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1123 int64_t DesiredMaskS) const {
1124 const APInt &ActualMask = RHS->getAPIntValue();
1125 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1127 // If the actual mask exactly matches, success!
1128 if (ActualMask == DesiredMask)
1131 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1132 if (ActualMask.intersects(~DesiredMask))
1135 // Otherwise, the DAG Combiner may have proven that the value coming in is
1136 // either already zero or is not demanded. Check for known zero input bits.
1137 APInt NeededMask = DesiredMask & ~ActualMask;
1139 APInt KnownZero, KnownOne;
1140 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1142 // If all the missing bits in the or are already known to be set, match!
1143 if ((NeededMask & KnownOne) == NeededMask)
1146 // TODO: check to see if missing bits are just not demanded.
1148 // Otherwise, this pattern doesn't match.
1153 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1154 /// by tblgen. Others should not call it.
1155 void SelectionDAGISel::
1156 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1157 std::vector<SDValue> InOps;
1158 std::swap(InOps, Ops);
1160 Ops.push_back(InOps[0]); // input chain.
1161 Ops.push_back(InOps[1]); // input asm string.
1163 unsigned i = 2, e = InOps.size();
1164 if (InOps[e-1].getValueType() == MVT::Flag)
1165 --e; // Don't process a flag operand if it is here.
1168 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1169 if ((Flags & 7) != 4 /*MEM*/) {
1170 // Just skip over this operand, copying the operands verbatim.
1171 Ops.insert(Ops.end(), InOps.begin()+i,
1172 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1173 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1175 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1176 "Memory operand with multiple values?");
1177 // Otherwise, this is a memory operand. Ask the target to select it.
1178 std::vector<SDValue> SelOps;
1179 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
1180 llvm_report_error("Could not match memory address. Inline asm"
1184 // Add this to the output node.
1185 EVT IntPtrTy = TLI.getPointerTy();
1186 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
1188 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1193 // Add the flag input back if present.
1194 if (e != InOps.size())
1195 Ops.push_back(InOps.back());
1198 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1201 static SDNode *findFlagUse(SDNode *N) {
1202 unsigned FlagResNo = N->getNumValues()-1;
1203 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1204 SDUse &Use = I.getUse();
1205 if (Use.getResNo() == FlagResNo)
1206 return Use.getUser();
1211 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1212 /// This function recursively traverses up the operand chain, ignoring
1214 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1216 SmallPtrSet<SDNode*, 16> &Visited) {
1217 if (Use->getNodeId() < Def->getNodeId() ||
1218 !Visited.insert(Use))
1221 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1222 SDNode *N = Use->getOperand(i).getNode();
1224 if (Use == ImmedUse || Use == Root)
1225 continue; // We are not looking for immediate use.
1230 // Traverse up the operand chain.
1231 if (findNonImmUse(N, Def, ImmedUse, Root, Visited))
1237 /// isNonImmUse - Start searching from Root up the DAG to check is Def can
1238 /// be reached. Return true if that's the case. However, ignore direct uses
1239 /// by ImmedUse (which would be U in the example illustrated in
1240 /// IsLegalAndProfitableToFold) and by Root (which can happen in the store
1242 /// FIXME: to be really generic, we should allow direct use by any node
1243 /// that is being folded. But realisticly since we only fold loads which
1244 /// have one non-chain use, we only need to watch out for load/op/store
1245 /// and load/op/cmp case where the root (store / cmp) may reach the load via
1246 /// its chain operand.
1247 static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) {
1248 SmallPtrSet<SDNode*, 16> Visited;
1249 return findNonImmUse(Root, Def, ImmedUse, Root, Visited);
1252 /// IsLegalAndProfitableToFold - Returns true if the specific operand node N of
1253 /// U can be folded during instruction selection that starts at Root and
1254 /// folding N is profitable.
1255 bool SelectionDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
1256 SDNode *Root) const {
1257 if (OptLevel == CodeGenOpt::None) return false;
1259 // If Root use can somehow reach N through a path that that doesn't contain
1260 // U then folding N would create a cycle. e.g. In the following
1261 // diagram, Root can reach N through X. If N is folded into into Root, then
1262 // X is both a predecessor and a successor of U.
1273 // * indicates nodes to be folded together.
1275 // If Root produces a flag, then it gets (even more) interesting. Since it
1276 // will be "glued" together with its flag use in the scheduler, we need to
1277 // check if it might reach N.
1296 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1297 // (call it Fold), then X is a predecessor of FU and a successor of
1298 // Fold. But since Fold and FU are flagged together, this will create
1299 // a cycle in the scheduling graph.
1301 EVT VT = Root->getValueType(Root->getNumValues()-1);
1302 while (VT == MVT::Flag) {
1303 SDNode *FU = findFlagUse(Root);
1307 VT = Root->getValueType(Root->getNumValues()-1);
1310 return !isNonImmUse(Root, N, U);
1313 SDNode *SelectionDAGISel::Select_INLINEASM(SDValue N) {
1314 std::vector<SDValue> Ops(N.getNode()->op_begin(), N.getNode()->op_end());
1315 SelectInlineAsmMemoryOperands(Ops);
1317 std::vector<EVT> VTs;
1318 VTs.push_back(MVT::Other);
1319 VTs.push_back(MVT::Flag);
1320 SDValue New = CurDAG->getNode(ISD::INLINEASM, N.getDebugLoc(),
1321 VTs, &Ops[0], Ops.size());
1322 return New.getNode();
1325 SDNode *SelectionDAGISel::Select_UNDEF(const SDValue &N) {
1326 return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::IMPLICIT_DEF,
1330 SDNode *SelectionDAGISel::Select_EH_LABEL(const SDValue &N) {
1331 SDValue Chain = N.getOperand(0);
1332 unsigned C = cast<LabelSDNode>(N)->getLabelID();
1333 SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);
1334 return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::EH_LABEL,
1335 MVT::Other, Tmp, Chain);
1338 void SelectionDAGISel::CannotYetSelect(SDValue N) {
1340 raw_string_ostream Msg(msg);
1341 Msg << "Cannot yet select: ";
1342 N.getNode()->print(Msg, CurDAG);
1343 llvm_report_error(Msg.str());
1346 void SelectionDAGISel::CannotYetSelectIntrinsic(SDValue N) {
1347 errs() << "Cannot yet select: ";
1349 cast<ConstantSDNode>(N.getOperand(N.getOperand(0).getValueType() == MVT::Other))->getZExtValue();
1350 if (iid < Intrinsic::num_intrinsics)
1351 llvm_report_error("Cannot yet select: intrinsic %" + Intrinsic::getName((Intrinsic::ID)iid));
1352 else if (const TargetIntrinsicInfo *tii = TM.getIntrinsicInfo())
1353 llvm_report_error(Twine("Cannot yet select: target intrinsic %") +
1357 char SelectionDAGISel::ID = 0;