1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
37 #include "llvm/CodeGen/SchedulerRegistry.h"
38 #include "llvm/CodeGen/SelectionDAG.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/Target/TargetIntrinsicInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/Timer.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/ADT/Statistic.h"
54 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
55 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
58 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
59 cl::desc("Enable verbose messages in the \"fast\" "
60 "instruction selector"));
62 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
63 cl::desc("Enable abort calls when \"fast\" instruction fails"));
67 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
68 cl::desc("Pop up a window to show dags before the first "
71 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
72 cl::desc("Pop up a window to show dags before legalize types"));
74 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
75 cl::desc("Pop up a window to show dags before legalize"));
77 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
78 cl::desc("Pop up a window to show dags before the second "
81 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
82 cl::desc("Pop up a window to show dags before the post legalize types"
83 " dag combine pass"));
85 ViewISelDAGs("view-isel-dags", cl::Hidden,
86 cl::desc("Pop up a window to show isel dags as they are selected"));
88 ViewSchedDAGs("view-sched-dags", cl::Hidden,
89 cl::desc("Pop up a window to show sched dags as they are processed"));
91 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
92 cl::desc("Pop up a window to show SUnit dags after they are processed"));
94 static const bool ViewDAGCombine1 = false,
95 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
96 ViewDAGCombine2 = false,
97 ViewDAGCombineLT = false,
98 ViewISelDAGs = false, ViewSchedDAGs = false,
99 ViewSUnitDAGs = false;
102 //===---------------------------------------------------------------------===//
104 /// RegisterScheduler class - Track the registration of instruction schedulers.
106 //===---------------------------------------------------------------------===//
107 MachinePassRegistry RegisterScheduler::Registry;
109 //===---------------------------------------------------------------------===//
111 /// ISHeuristic command line option for instruction schedulers.
113 //===---------------------------------------------------------------------===//
114 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
115 RegisterPassParser<RegisterScheduler> >
116 ISHeuristic("pre-RA-sched",
117 cl::init(&createDefaultScheduler),
118 cl::desc("Instruction schedulers available (before register"
121 static RegisterScheduler
122 defaultListDAGScheduler("default", "Best scheduler for the target",
123 createDefaultScheduler);
126 //===--------------------------------------------------------------------===//
127 /// createDefaultScheduler - This creates an instruction scheduler appropriate
129 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
130 CodeGenOpt::Level OptLevel) {
131 const TargetLowering &TLI = IS->getTargetLowering();
133 if (OptLevel == CodeGenOpt::None)
134 return createFastDAGScheduler(IS, OptLevel);
135 if (TLI.getSchedulingPreference() == Sched::Latency)
136 return createTDListDAGScheduler(IS, OptLevel);
137 assert(TLI.getSchedulingPreference() == Sched::RegPressure &&
138 "Unknown sched type!");
139 return createBURRListDAGScheduler(IS, OptLevel);
143 // EmitInstrWithCustomInserter - This method should be implemented by targets
144 // that mark instructions with the 'usesCustomInserter' flag. These
145 // instructions are special in various ways, which require special support to
146 // insert. The specified MachineInstr is created but not inserted into any
147 // basic blocks, and this method is called to expand it into a sequence of
148 // instructions, potentially also creating new basic blocks and control flow.
149 // When new basic blocks are inserted and the edges from MBB to its successors
150 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
153 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
154 MachineBasicBlock *MBB) const {
156 dbgs() << "If a target marks an instruction with "
157 "'usesCustomInserter', it must implement "
158 "TargetLowering::EmitInstrWithCustomInserter!";
164 //===----------------------------------------------------------------------===//
165 // SelectionDAGISel code
166 //===----------------------------------------------------------------------===//
168 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
169 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
170 FuncInfo(new FunctionLoweringInfo(TLI)),
171 CurDAG(new SelectionDAG(tm, *FuncInfo)),
172 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
178 SelectionDAGISel::~SelectionDAGISel() {
184 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
185 AU.addRequired<AliasAnalysis>();
186 AU.addPreserved<AliasAnalysis>();
187 AU.addRequired<GCModuleInfo>();
188 AU.addPreserved<GCModuleInfo>();
189 MachineFunctionPass::getAnalysisUsage(AU);
192 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
193 // Do some sanity-checking on the command-line options.
194 assert((!EnableFastISelVerbose || EnableFastISel) &&
195 "-fast-isel-verbose requires -fast-isel");
196 assert((!EnableFastISelAbort || EnableFastISel) &&
197 "-fast-isel-abort requires -fast-isel");
199 const Function &Fn = *mf.getFunction();
200 const TargetInstrInfo &TII = *TM.getInstrInfo();
201 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
204 RegInfo = &MF->getRegInfo();
205 AA = &getAnalysis<AliasAnalysis>();
206 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
208 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
211 FuncInfo->set(Fn, *MF, EnableFastISel);
214 SelectAllBasicBlocks(Fn);
216 // If the first basic block in the function has live ins that need to be
217 // copied into vregs, emit the copies into the top of the block before
218 // emitting the code for the block.
219 MachineBasicBlock *EntryMBB = MF->begin();
220 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
222 // Insert DBG_VALUE instructions for function arguments to the entry block.
223 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
224 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
225 unsigned Reg = MI->getOperand(0).getReg();
226 if (TargetRegisterInfo::isPhysicalRegister(Reg))
227 EntryMBB->insert(EntryMBB->begin(), MI);
229 MachineInstr *Def = RegInfo->getVRegDef(Reg);
230 MachineBasicBlock::iterator InsertPos = Def;
231 // FIXME: VR def may not be in entry block.
232 Def->getParent()->insert(llvm::next(InsertPos), MI);
236 // Determine if there are any calls in this machine function.
237 MachineFrameInfo *MFI = MF->getFrameInfo();
238 if (!MFI->hasCalls()) {
239 for (MachineFunction::const_iterator
240 I = MF->begin(), E = MF->end(); I != E; ++I) {
241 const MachineBasicBlock *MBB = I;
242 for (MachineBasicBlock::const_iterator
243 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
244 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
245 if (II->isInlineAsm() || (TID.isCall() && !TID.isReturn())) {
246 MFI->setHasCalls(true);
254 // Release function-specific state. SDB and CurDAG are already cleared
262 SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB,
263 const BasicBlock *LLVMBB,
264 BasicBlock::const_iterator Begin,
265 BasicBlock::const_iterator End,
267 // Lower all of the non-terminator instructions. If a call is emitted
268 // as a tail call, cease emitting nodes for this block. Terminators
269 // are handled below.
270 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
273 // Make sure the root of the DAG is up-to-date.
274 CurDAG->setRoot(SDB->getControlRoot());
275 HadTailCall = SDB->HasTailCall;
278 // Final step, emit the lowered DAG as machine code.
279 return CodeGenAndEmitDAG(BB);
283 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
284 /// nodes from the worklist.
285 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
286 SmallVector<SDNode*, 128> &Worklist;
287 SmallPtrSet<SDNode*, 128> &InWorklist;
289 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
290 SmallPtrSet<SDNode*, 128> &inwl)
291 : Worklist(wl), InWorklist(inwl) {}
293 void RemoveFromWorklist(SDNode *N) {
294 if (!InWorklist.erase(N)) return;
296 SmallVector<SDNode*, 128>::iterator I =
297 std::find(Worklist.begin(), Worklist.end(), N);
298 assert(I != Worklist.end() && "Not in worklist");
300 *I = Worklist.back();
304 virtual void NodeDeleted(SDNode *N, SDNode *E) {
305 RemoveFromWorklist(N);
308 virtual void NodeUpdated(SDNode *N) {
314 /// TrivialTruncElim - Eliminate some trivial nops that can result from
315 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
316 static bool TrivialTruncElim(SDValue Op,
317 TargetLowering::TargetLoweringOpt &TLO) {
318 SDValue N0 = Op.getOperand(0);
319 EVT VT = Op.getValueType();
320 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
321 N0.getOpcode() == ISD::SIGN_EXTEND ||
322 N0.getOpcode() == ISD::ANY_EXTEND) &&
323 N0.getOperand(0).getValueType() == VT) {
324 return TLO.CombineTo(Op, N0.getOperand(0));
329 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
330 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
331 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
332 void SelectionDAGISel::ShrinkDemandedOps() {
333 SmallVector<SDNode*, 128> Worklist;
334 SmallPtrSet<SDNode*, 128> InWorklist;
336 // Add all the dag nodes to the worklist.
337 Worklist.reserve(CurDAG->allnodes_size());
338 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
339 E = CurDAG->allnodes_end(); I != E; ++I) {
340 Worklist.push_back(I);
341 InWorklist.insert(I);
344 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true, true);
345 while (!Worklist.empty()) {
346 SDNode *N = Worklist.pop_back_val();
349 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
350 // Deleting this node may make its operands dead, add them to the worklist
351 // if they aren't already there.
352 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
353 if (InWorklist.insert(N->getOperand(i).getNode()))
354 Worklist.push_back(N->getOperand(i).getNode());
356 CurDAG->DeleteNode(N);
360 // Run ShrinkDemandedOp on scalar binary operations.
361 if (N->getNumValues() != 1 ||
362 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
365 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
366 APInt Demanded = APInt::getAllOnesValue(BitWidth);
367 APInt KnownZero, KnownOne;
368 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
369 KnownZero, KnownOne, TLO) &&
370 (N->getOpcode() != ISD::TRUNCATE ||
371 !TrivialTruncElim(SDValue(N, 0), TLO)))
375 assert(!InWorklist.count(N) && "Already in worklist");
376 Worklist.push_back(N);
377 InWorklist.insert(N);
379 // Replace the old value with the new one.
380 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
381 TLO.Old.getNode()->dump(CurDAG);
382 errs() << "\nWith: ";
383 TLO.New.getNode()->dump(CurDAG);
386 if (InWorklist.insert(TLO.New.getNode()))
387 Worklist.push_back(TLO.New.getNode());
389 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
390 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
392 if (!TLO.Old.getNode()->use_empty()) continue;
394 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
396 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
397 if (OpNode->hasOneUse()) {
398 // Add OpNode to the end of the list to revisit.
399 DeadNodes.RemoveFromWorklist(OpNode);
400 Worklist.push_back(OpNode);
401 InWorklist.insert(OpNode);
405 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
406 CurDAG->DeleteNode(TLO.Old.getNode());
410 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
411 SmallPtrSet<SDNode*, 128> VisitedNodes;
412 SmallVector<SDNode*, 128> Worklist;
414 Worklist.push_back(CurDAG->getRoot().getNode());
421 SDNode *N = Worklist.pop_back_val();
423 // If we've already seen this node, ignore it.
424 if (!VisitedNodes.insert(N))
427 // Otherwise, add all chain operands to the worklist.
428 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
429 if (N->getOperand(i).getValueType() == MVT::Other)
430 Worklist.push_back(N->getOperand(i).getNode());
432 // If this is a CopyToReg with a vreg dest, process it.
433 if (N->getOpcode() != ISD::CopyToReg)
436 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
437 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
440 // Ignore non-scalar or non-integer values.
441 SDValue Src = N->getOperand(2);
442 EVT SrcVT = Src.getValueType();
443 if (!SrcVT.isInteger() || SrcVT.isVector())
446 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
447 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
448 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
450 // Only install this information if it tells us something.
451 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
452 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
453 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
454 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
455 FunctionLoweringInfo::LiveOutInfo &LOI =
456 FuncInfo->LiveOutRegInfo[DestReg];
457 LOI.NumSignBits = NumSignBits;
458 LOI.KnownOne = KnownOne;
459 LOI.KnownZero = KnownZero;
461 } while (!Worklist.empty());
464 MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) {
465 std::string GroupName;
466 if (TimePassesIsEnabled)
467 GroupName = "Instruction Selection and Scheduling";
468 std::string BlockName;
469 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
470 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
472 BlockName = MF->getFunction()->getNameStr() + ":" +
473 BB->getBasicBlock()->getNameStr();
475 DEBUG(dbgs() << "Initial selection DAG:\n");
476 DEBUG(CurDAG->dump());
478 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
480 // Run the DAG combiner in pre-legalize mode.
481 if (TimePassesIsEnabled) {
482 NamedRegionTimer T("DAG Combining 1", GroupName);
483 CurDAG->Combine(Unrestricted, *AA, OptLevel);
485 CurDAG->Combine(Unrestricted, *AA, OptLevel);
488 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
489 DEBUG(CurDAG->dump());
491 // Second step, hack on the DAG until it only uses operations and types that
492 // the target supports.
493 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
497 if (TimePassesIsEnabled) {
498 NamedRegionTimer T("Type Legalization", GroupName);
499 Changed = CurDAG->LegalizeTypes();
501 Changed = CurDAG->LegalizeTypes();
504 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
505 DEBUG(CurDAG->dump());
508 if (ViewDAGCombineLT)
509 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
511 // Run the DAG combiner in post-type-legalize mode.
512 if (TimePassesIsEnabled) {
513 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
514 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
516 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
519 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
520 DEBUG(CurDAG->dump());
523 if (TimePassesIsEnabled) {
524 NamedRegionTimer T("Vector Legalization", GroupName);
525 Changed = CurDAG->LegalizeVectors();
527 Changed = CurDAG->LegalizeVectors();
531 if (TimePassesIsEnabled) {
532 NamedRegionTimer T("Type Legalization 2", GroupName);
533 CurDAG->LegalizeTypes();
535 CurDAG->LegalizeTypes();
538 if (ViewDAGCombineLT)
539 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
541 // Run the DAG combiner in post-type-legalize mode.
542 if (TimePassesIsEnabled) {
543 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
544 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
546 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
549 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
550 DEBUG(CurDAG->dump());
553 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
555 if (TimePassesIsEnabled) {
556 NamedRegionTimer T("DAG Legalization", GroupName);
557 CurDAG->Legalize(OptLevel);
559 CurDAG->Legalize(OptLevel);
562 DEBUG(dbgs() << "Legalized selection DAG:\n");
563 DEBUG(CurDAG->dump());
565 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
567 // Run the DAG combiner in post-legalize mode.
568 if (TimePassesIsEnabled) {
569 NamedRegionTimer T("DAG Combining 2", GroupName);
570 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
572 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
575 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
576 DEBUG(CurDAG->dump());
578 if (OptLevel != CodeGenOpt::None) {
580 ComputeLiveOutVRegInfo();
583 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
585 // Third, instruction select all of the operations to machine code, adding the
586 // code to the MachineBasicBlock.
587 if (TimePassesIsEnabled) {
588 NamedRegionTimer T("Instruction Selection", GroupName);
589 DoInstructionSelection();
591 DoInstructionSelection();
594 DEBUG(dbgs() << "Selected selection DAG:\n");
595 DEBUG(CurDAG->dump());
597 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
599 // Schedule machine code.
600 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
601 if (TimePassesIsEnabled) {
602 NamedRegionTimer T("Instruction Scheduling", GroupName);
603 Scheduler->Run(CurDAG, BB, BB->end());
605 Scheduler->Run(CurDAG, BB, BB->end());
608 if (ViewSUnitDAGs) Scheduler->viewGraph();
610 // Emit machine code to BB. This can change 'BB' to the last block being
612 if (TimePassesIsEnabled) {
613 NamedRegionTimer T("Instruction Creation", GroupName);
614 BB = Scheduler->EmitSchedule();
616 BB = Scheduler->EmitSchedule();
619 // Free the scheduler state.
620 if (TimePassesIsEnabled) {
621 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
627 // Free the SelectionDAG state, now that we're finished with it.
633 void SelectionDAGISel::DoInstructionSelection() {
634 DEBUG(errs() << "===== Instruction selection begins:\n");
638 // Select target instructions for the DAG.
640 // Number all nodes with a topological order and set DAGSize.
641 DAGSize = CurDAG->AssignTopologicalOrder();
643 // Create a dummy node (which is not added to allnodes), that adds
644 // a reference to the root node, preventing it from being deleted,
645 // and tracking any changes of the root.
646 HandleSDNode Dummy(CurDAG->getRoot());
647 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
650 // The AllNodes list is now topological-sorted. Visit the
651 // nodes by starting at the end of the list (the root of the
652 // graph) and preceding back toward the beginning (the entry
654 while (ISelPosition != CurDAG->allnodes_begin()) {
655 SDNode *Node = --ISelPosition;
656 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
657 // but there are currently some corner cases that it misses. Also, this
658 // makes it theoretically possible to disable the DAGCombiner.
659 if (Node->use_empty())
662 SDNode *ResNode = Select(Node);
664 // FIXME: This is pretty gross. 'Select' should be changed to not return
665 // anything at all and this code should be nuked with a tactical strike.
667 // If node should not be replaced, continue with the next one.
668 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
672 ReplaceUses(Node, ResNode);
674 // If after the replacement this node is not used any more,
675 // remove this dead node.
676 if (Node->use_empty()) { // Don't delete EntryToken, etc.
677 ISelUpdater ISU(ISelPosition);
678 CurDAG->RemoveDeadNode(Node, &ISU);
682 CurDAG->setRoot(Dummy.getValue());
685 DEBUG(errs() << "===== Instruction selection ends:\n");
687 PostprocessISelDAG();
690 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
691 /// do other setup for EH landing-pad blocks.
692 void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) {
693 // Add a label to mark the beginning of the landing pad. Deletion of the
694 // landing pad can thus be detected via the MachineModuleInfo.
695 MCSymbol *Label = MF->getMMI().addLandingPad(BB);
697 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
698 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
700 // Mark exception register as live in.
701 unsigned Reg = TLI.getExceptionAddressRegister();
702 if (Reg) BB->addLiveIn(Reg);
704 // Mark exception selector register as live in.
705 Reg = TLI.getExceptionSelectorRegister();
706 if (Reg) BB->addLiveIn(Reg);
708 // FIXME: Hack around an exception handling flaw (PR1508): the personality
709 // function and list of typeids logically belong to the invoke (or, if you
710 // like, the basic block containing the invoke), and need to be associated
711 // with it in the dwarf exception handling tables. Currently however the
712 // information is provided by an intrinsic (eh.selector) that can be moved
713 // to unexpected places by the optimizers: if the unwind edge is critical,
714 // then breaking it can result in the intrinsics being in the successor of
715 // the landing pad, not the landing pad itself. This results
716 // in exceptions not being caught because no typeids are associated with
717 // the invoke. This may not be the only way things can go wrong, but it
718 // is the only way we try to work around for the moment.
719 const BasicBlock *LLVMBB = BB->getBasicBlock();
720 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
722 if (Br && Br->isUnconditional()) { // Critical edge?
723 BasicBlock::const_iterator I, E;
724 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
725 if (isa<EHSelectorInst>(I))
729 // No catch info found - try to extract some from the successor.
730 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
734 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
735 // Initialize the Fast-ISel state, if needed.
736 FastISel *FastIS = 0;
738 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
739 FuncInfo->StaticAllocaMap,
740 FuncInfo->PHINodesToUpdate
742 , FuncInfo->CatchInfoLost
746 // Iterate over all basic blocks in the function.
747 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
748 const BasicBlock *LLVMBB = &*I;
749 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB];
751 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
752 BasicBlock::const_iterator const End = LLVMBB->end();
753 BasicBlock::const_iterator BI = Begin;
755 // Lower any arguments needed in this block if this is the entry block.
756 if (LLVMBB == &Fn.getEntryBlock())
757 LowerArguments(LLVMBB);
759 // Setup an EH landing-pad block.
760 if (BB->isLandingPad())
761 PrepareEHLandingPad(BB);
763 // Before doing SelectionDAG ISel, see if FastISel has been requested.
765 // Emit code for any incoming arguments. This must happen before
766 // beginning FastISel on the entry block.
767 if (LLVMBB == &Fn.getEntryBlock()) {
768 CurDAG->setRoot(SDB->getControlRoot());
770 BB = CodeGenAndEmitDAG(BB);
772 FastIS->startNewBlock(BB);
773 // Do FastISel on as many instructions as possible.
774 for (; BI != End; ++BI) {
775 // Try to select the instruction with FastISel.
776 if (FastIS->SelectInstruction(BI))
779 // Then handle certain instructions as single-LLVM-Instruction blocks.
780 if (isa<CallInst>(BI)) {
781 ++NumFastIselFailures;
782 if (EnableFastISelVerbose || EnableFastISelAbort) {
783 dbgs() << "FastISel missed call: ";
787 if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
788 unsigned &R = FuncInfo->ValueMap[BI];
790 R = FuncInfo->CreateRegForValue(BI);
793 bool HadTailCall = false;
794 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall);
796 // If the call was emitted as a tail call, we're done with the block.
802 // If the instruction was codegen'd with multiple blocks,
803 // inform the FastISel object where to resume inserting.
804 FastIS->setCurrentBlock(BB);
808 // Otherwise, give up on FastISel for the rest of the block.
809 // For now, be a little lenient about non-branch terminators.
810 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
811 ++NumFastIselFailures;
812 if (EnableFastISelVerbose || EnableFastISelAbort) {
813 dbgs() << "FastISel miss: ";
816 if (EnableFastISelAbort)
817 // The "fast" selector couldn't handle something and bailed.
818 // For the purpose of debugging, just abort.
819 llvm_unreachable("FastISel didn't select the entire block");
825 // Run SelectionDAG instruction selection on the remainder of the block
826 // not handled by FastISel. If FastISel is not run, this is the entire
830 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall);
833 FinishBasicBlock(BB);
834 FuncInfo->PHINodesToUpdate.clear();
841 SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) {
843 DEBUG(dbgs() << "Total amount of phi nodes to update: "
844 << FuncInfo->PHINodesToUpdate.size() << "\n");
845 DEBUG(for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
846 dbgs() << "Node " << i << " : ("
847 << FuncInfo->PHINodesToUpdate[i].first
848 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
850 // Next, now that we know what the last MBB the LLVM BB expanded is, update
851 // PHI nodes in successors.
852 if (SDB->SwitchCases.empty() &&
853 SDB->JTCases.empty() &&
854 SDB->BitTestCases.empty()) {
855 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
856 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
857 assert(PHI->isPHI() &&
858 "This is not a machine PHI node that we are updating!");
859 if (!BB->isSuccessor(PHI->getParent()))
862 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
863 PHI->addOperand(MachineOperand::CreateMBB(BB));
868 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
869 // Lower header first, if it wasn't already lowered
870 if (!SDB->BitTestCases[i].Emitted) {
871 // Set the current basic block to the mbb we wish to insert the code into
872 BB = SDB->BitTestCases[i].Parent;
874 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB);
875 CurDAG->setRoot(SDB->getRoot());
877 BB = CodeGenAndEmitDAG(BB);
880 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
881 // Set the current basic block to the mbb we wish to insert the code into
882 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
885 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
886 SDB->BitTestCases[i].Reg,
887 SDB->BitTestCases[i].Cases[j],
890 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
891 SDB->BitTestCases[i].Reg,
892 SDB->BitTestCases[i].Cases[j],
896 CurDAG->setRoot(SDB->getRoot());
898 BB = CodeGenAndEmitDAG(BB);
902 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
904 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
905 MachineBasicBlock *PHIBB = PHI->getParent();
906 assert(PHI->isPHI() &&
907 "This is not a machine PHI node that we are updating!");
908 // This is "default" BB. We have two jumps to it. From "header" BB and
909 // from last "case" BB.
910 if (PHIBB == SDB->BitTestCases[i].Default) {
911 PHI->addOperand(MachineOperand::
912 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
914 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
915 PHI->addOperand(MachineOperand::
916 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
918 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
921 // One of "cases" BB.
922 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
924 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
925 if (cBB->isSuccessor(PHIBB)) {
926 PHI->addOperand(MachineOperand::
927 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
929 PHI->addOperand(MachineOperand::CreateMBB(cBB));
934 SDB->BitTestCases.clear();
936 // If the JumpTable record is filled in, then we need to emit a jump table.
937 // Updating the PHI nodes is tricky in this case, since we need to determine
938 // whether the PHI is a successor of the range check MBB or the jump table MBB
939 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
940 // Lower header first, if it wasn't already lowered
941 if (!SDB->JTCases[i].first.Emitted) {
942 // Set the current basic block to the mbb we wish to insert the code into
943 BB = SDB->JTCases[i].first.HeaderBB;
945 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
947 CurDAG->setRoot(SDB->getRoot());
949 BB = CodeGenAndEmitDAG(BB);
952 // Set the current basic block to the mbb we wish to insert the code into
953 BB = SDB->JTCases[i].second.MBB;
955 SDB->visitJumpTable(SDB->JTCases[i].second);
956 CurDAG->setRoot(SDB->getRoot());
958 BB = CodeGenAndEmitDAG(BB);
961 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
963 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
964 MachineBasicBlock *PHIBB = PHI->getParent();
965 assert(PHI->isPHI() &&
966 "This is not a machine PHI node that we are updating!");
967 // "default" BB. We can go there only from header BB.
968 if (PHIBB == SDB->JTCases[i].second.Default) {
970 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
973 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
975 // JT BB. Just iterate over successors here
976 if (BB->isSuccessor(PHIBB)) {
978 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
980 PHI->addOperand(MachineOperand::CreateMBB(BB));
984 SDB->JTCases.clear();
986 // If the switch block involved a branch to one of the actual successors, we
987 // need to update PHI nodes in that block.
988 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
989 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
990 assert(PHI->isPHI() &&
991 "This is not a machine PHI node that we are updating!");
992 if (BB->isSuccessor(PHI->getParent())) {
994 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
995 PHI->addOperand(MachineOperand::CreateMBB(BB));
999 // If we generated any switch lowering information, build and codegen any
1000 // additional DAGs necessary.
1001 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1002 // Set the current basic block to the mbb we wish to insert the code into
1003 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1005 // Determine the unique successors.
1006 SmallVector<MachineBasicBlock *, 2> Succs;
1007 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1008 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1009 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1011 // Emit the code. Note that this could result in ThisBB being split, so
1012 // we need to check for updates.
1013 SDB->visitSwitchCase(SDB->SwitchCases[i], BB);
1014 CurDAG->setRoot(SDB->getRoot());
1016 ThisBB = CodeGenAndEmitDAG(BB);
1018 // Handle any PHI nodes in successors of this chunk, as if we were coming
1019 // from the original BB before switch expansion. Note that PHI nodes can
1020 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1021 // handle them the right number of times.
1022 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1024 // BB may have been removed from the CFG if a branch was constant folded.
1025 if (ThisBB->isSuccessor(BB)) {
1026 for (MachineBasicBlock::iterator Phi = BB->begin();
1027 Phi != BB->end() && Phi->isPHI();
1029 // This value for this PHI node is recorded in PHINodesToUpdate.
1030 for (unsigned pn = 0; ; ++pn) {
1031 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1032 "Didn't find PHI entry!");
1033 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1034 Phi->addOperand(MachineOperand::
1035 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1037 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1045 SDB->SwitchCases.clear();
1049 /// Create the scheduler. If a specific scheduler was specified
1050 /// via the SchedulerRegistry, use it, otherwise select the
1051 /// one preferred by the target.
1053 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1054 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1058 RegisterScheduler::setDefault(Ctor);
1061 return Ctor(this, OptLevel);
1064 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1065 return new ScheduleHazardRecognizer();
1068 //===----------------------------------------------------------------------===//
1069 // Helper functions used by the generated instruction selector.
1070 //===----------------------------------------------------------------------===//
1071 // Calls to these methods are generated by tblgen.
1073 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1074 /// the dag combiner simplified the 255, we still want to match. RHS is the
1075 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1076 /// specified in the .td file (e.g. 255).
1077 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1078 int64_t DesiredMaskS) const {
1079 const APInt &ActualMask = RHS->getAPIntValue();
1080 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1082 // If the actual mask exactly matches, success!
1083 if (ActualMask == DesiredMask)
1086 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1087 if (ActualMask.intersects(~DesiredMask))
1090 // Otherwise, the DAG Combiner may have proven that the value coming in is
1091 // either already zero or is not demanded. Check for known zero input bits.
1092 APInt NeededMask = DesiredMask & ~ActualMask;
1093 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1096 // TODO: check to see if missing bits are just not demanded.
1098 // Otherwise, this pattern doesn't match.
1102 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1103 /// the dag combiner simplified the 255, we still want to match. RHS is the
1104 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1105 /// specified in the .td file (e.g. 255).
1106 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1107 int64_t DesiredMaskS) const {
1108 const APInt &ActualMask = RHS->getAPIntValue();
1109 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1111 // If the actual mask exactly matches, success!
1112 if (ActualMask == DesiredMask)
1115 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1116 if (ActualMask.intersects(~DesiredMask))
1119 // Otherwise, the DAG Combiner may have proven that the value coming in is
1120 // either already zero or is not demanded. Check for known zero input bits.
1121 APInt NeededMask = DesiredMask & ~ActualMask;
1123 APInt KnownZero, KnownOne;
1124 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1126 // If all the missing bits in the or are already known to be set, match!
1127 if ((NeededMask & KnownOne) == NeededMask)
1130 // TODO: check to see if missing bits are just not demanded.
1132 // Otherwise, this pattern doesn't match.
1137 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1138 /// by tblgen. Others should not call it.
1139 void SelectionDAGISel::
1140 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1141 std::vector<SDValue> InOps;
1142 std::swap(InOps, Ops);
1144 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1145 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1146 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1148 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1149 if (InOps[e-1].getValueType() == MVT::Flag)
1150 --e; // Don't process a flag operand if it is here.
1153 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1154 if (!InlineAsm::isMemKind(Flags)) {
1155 // Just skip over this operand, copying the operands verbatim.
1156 Ops.insert(Ops.end(), InOps.begin()+i,
1157 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1158 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1160 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1161 "Memory operand with multiple values?");
1162 // Otherwise, this is a memory operand. Ask the target to select it.
1163 std::vector<SDValue> SelOps;
1164 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1165 report_fatal_error("Could not match memory address. Inline asm"
1168 // Add this to the output node.
1170 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1171 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1172 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1177 // Add the flag input back if present.
1178 if (e != InOps.size())
1179 Ops.push_back(InOps.back());
1182 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1185 static SDNode *findFlagUse(SDNode *N) {
1186 unsigned FlagResNo = N->getNumValues()-1;
1187 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1188 SDUse &Use = I.getUse();
1189 if (Use.getResNo() == FlagResNo)
1190 return Use.getUser();
1195 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1196 /// This function recursively traverses up the operand chain, ignoring
1198 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1199 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1200 bool IgnoreChains) {
1201 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1202 // greater than all of its (recursive) operands. If we scan to a point where
1203 // 'use' is smaller than the node we're scanning for, then we know we will
1206 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1207 // happen because we scan down to newly selected nodes in the case of flag
1209 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1212 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1213 // won't fail if we scan it again.
1214 if (!Visited.insert(Use))
1217 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1218 // Ignore chain uses, they are validated by HandleMergeInputChains.
1219 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1222 SDNode *N = Use->getOperand(i).getNode();
1224 if (Use == ImmedUse || Use == Root)
1225 continue; // We are not looking for immediate use.
1230 // Traverse up the operand chain.
1231 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1237 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1238 /// operand node N of U during instruction selection that starts at Root.
1239 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1240 SDNode *Root) const {
1241 if (OptLevel == CodeGenOpt::None) return false;
1242 return N.hasOneUse();
1245 /// IsLegalToFold - Returns true if the specific operand node N of
1246 /// U can be folded during instruction selection that starts at Root.
1247 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1248 CodeGenOpt::Level OptLevel,
1249 bool IgnoreChains) {
1250 if (OptLevel == CodeGenOpt::None) return false;
1252 // If Root use can somehow reach N through a path that that doesn't contain
1253 // U then folding N would create a cycle. e.g. In the following
1254 // diagram, Root can reach N through X. If N is folded into into Root, then
1255 // X is both a predecessor and a successor of U.
1266 // * indicates nodes to be folded together.
1268 // If Root produces a flag, then it gets (even more) interesting. Since it
1269 // will be "glued" together with its flag use in the scheduler, we need to
1270 // check if it might reach N.
1289 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1290 // (call it Fold), then X is a predecessor of FU and a successor of
1291 // Fold. But since Fold and FU are flagged together, this will create
1292 // a cycle in the scheduling graph.
1294 // If the node has flags, walk down the graph to the "lowest" node in the
1296 EVT VT = Root->getValueType(Root->getNumValues()-1);
1297 while (VT == MVT::Flag) {
1298 SDNode *FU = findFlagUse(Root);
1302 VT = Root->getValueType(Root->getNumValues()-1);
1304 // If our query node has a flag result with a use, we've walked up it. If
1305 // the user (which has already been selected) has a chain or indirectly uses
1306 // the chain, our WalkChainUsers predicate will not consider it. Because of
1307 // this, we cannot ignore chains in this predicate.
1308 IgnoreChains = false;
1312 SmallPtrSet<SDNode*, 16> Visited;
1313 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1316 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1317 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1318 SelectInlineAsmMemoryOperands(Ops);
1320 std::vector<EVT> VTs;
1321 VTs.push_back(MVT::Other);
1322 VTs.push_back(MVT::Flag);
1323 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1324 VTs, &Ops[0], Ops.size());
1326 return New.getNode();
1329 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1330 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1333 /// GetVBR - decode a vbr encoding whose top bit is set.
1334 ALWAYS_INLINE static uint64_t
1335 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1336 assert(Val >= 128 && "Not a VBR");
1337 Val &= 127; // Remove first vbr bit.
1342 NextBits = MatcherTable[Idx++];
1343 Val |= (NextBits&127) << Shift;
1345 } while (NextBits & 128);
1351 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1352 /// interior flag and chain results to use the new flag and chain results.
1353 void SelectionDAGISel::
1354 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1355 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1357 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1358 bool isMorphNodeTo) {
1359 SmallVector<SDNode*, 4> NowDeadNodes;
1361 ISelUpdater ISU(ISelPosition);
1363 // Now that all the normal results are replaced, we replace the chain and
1364 // flag results if present.
1365 if (!ChainNodesMatched.empty()) {
1366 assert(InputChain.getNode() != 0 &&
1367 "Matched input chains but didn't produce a chain");
1368 // Loop over all of the nodes we matched that produced a chain result.
1369 // Replace all the chain results with the final chain we ended up with.
1370 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1371 SDNode *ChainNode = ChainNodesMatched[i];
1373 // If this node was already deleted, don't look at it.
1374 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1377 // Don't replace the results of the root node if we're doing a
1379 if (ChainNode == NodeToMatch && isMorphNodeTo)
1382 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1383 if (ChainVal.getValueType() == MVT::Flag)
1384 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1385 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1386 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1388 // If the node became dead and we haven't already seen it, delete it.
1389 if (ChainNode->use_empty() &&
1390 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1391 NowDeadNodes.push_back(ChainNode);
1395 // If the result produces a flag, update any flag results in the matched
1396 // pattern with the flag result.
1397 if (InputFlag.getNode() != 0) {
1398 // Handle any interior nodes explicitly marked.
1399 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1400 SDNode *FRN = FlagResultNodesMatched[i];
1402 // If this node was already deleted, don't look at it.
1403 if (FRN->getOpcode() == ISD::DELETED_NODE)
1406 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1407 "Doesn't have a flag result");
1408 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1411 // If the node became dead and we haven't already seen it, delete it.
1412 if (FRN->use_empty() &&
1413 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1414 NowDeadNodes.push_back(FRN);
1418 if (!NowDeadNodes.empty())
1419 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1421 DEBUG(errs() << "ISEL: Match complete!\n");
1427 CR_LeadsToInteriorNode
1430 /// WalkChainUsers - Walk down the users of the specified chained node that is
1431 /// part of the pattern we're matching, looking at all of the users we find.
1432 /// This determines whether something is an interior node, whether we have a
1433 /// non-pattern node in between two pattern nodes (which prevent folding because
1434 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1435 /// between pattern nodes (in which case the TF becomes part of the pattern).
1437 /// The walk we do here is guaranteed to be small because we quickly get down to
1438 /// already selected nodes "below" us.
1440 WalkChainUsers(SDNode *ChainedNode,
1441 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1442 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1443 ChainResult Result = CR_Simple;
1445 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1446 E = ChainedNode->use_end(); UI != E; ++UI) {
1447 // Make sure the use is of the chain, not some other value we produce.
1448 if (UI.getUse().getValueType() != MVT::Other) continue;
1452 // If we see an already-selected machine node, then we've gone beyond the
1453 // pattern that we're selecting down into the already selected chunk of the
1455 if (User->isMachineOpcode() ||
1456 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1459 if (User->getOpcode() == ISD::CopyToReg ||
1460 User->getOpcode() == ISD::CopyFromReg ||
1461 User->getOpcode() == ISD::INLINEASM ||
1462 User->getOpcode() == ISD::EH_LABEL) {
1463 // If their node ID got reset to -1 then they've already been selected.
1464 // Treat them like a MachineOpcode.
1465 if (User->getNodeId() == -1)
1469 // If we have a TokenFactor, we handle it specially.
1470 if (User->getOpcode() != ISD::TokenFactor) {
1471 // If the node isn't a token factor and isn't part of our pattern, then it
1472 // must be a random chained node in between two nodes we're selecting.
1473 // This happens when we have something like:
1478 // Because we structurally match the load/store as a read/modify/write,
1479 // but the call is chained between them. We cannot fold in this case
1480 // because it would induce a cycle in the graph.
1481 if (!std::count(ChainedNodesInPattern.begin(),
1482 ChainedNodesInPattern.end(), User))
1483 return CR_InducesCycle;
1485 // Otherwise we found a node that is part of our pattern. For example in:
1489 // This would happen when we're scanning down from the load and see the
1490 // store as a user. Record that there is a use of ChainedNode that is
1491 // part of the pattern and keep scanning uses.
1492 Result = CR_LeadsToInteriorNode;
1493 InteriorChainedNodes.push_back(User);
1497 // If we found a TokenFactor, there are two cases to consider: first if the
1498 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1499 // uses of the TF are in our pattern) we just want to ignore it. Second,
1500 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1506 // | \ DAG's like cheese
1509 // [TokenFactor] [Op]
1516 // In this case, the TokenFactor becomes part of our match and we rewrite it
1517 // as a new TokenFactor.
1519 // To distinguish these two cases, do a recursive walk down the uses.
1520 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1522 // If the uses of the TokenFactor are just already-selected nodes, ignore
1523 // it, it is "below" our pattern.
1525 case CR_InducesCycle:
1526 // If the uses of the TokenFactor lead to nodes that are not part of our
1527 // pattern that are not selected, folding would turn this into a cycle,
1529 return CR_InducesCycle;
1530 case CR_LeadsToInteriorNode:
1531 break; // Otherwise, keep processing.
1534 // Okay, we know we're in the interesting interior case. The TokenFactor
1535 // is now going to be considered part of the pattern so that we rewrite its
1536 // uses (it may have uses that are not part of the pattern) with the
1537 // ultimate chain result of the generated code. We will also add its chain
1538 // inputs as inputs to the ultimate TokenFactor we create.
1539 Result = CR_LeadsToInteriorNode;
1540 ChainedNodesInPattern.push_back(User);
1541 InteriorChainedNodes.push_back(User);
1548 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1549 /// operation for when the pattern matched at least one node with a chains. The
1550 /// input vector contains a list of all of the chained nodes that we match. We
1551 /// must determine if this is a valid thing to cover (i.e. matching it won't
1552 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1553 /// be used as the input node chain for the generated nodes.
1555 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1556 SelectionDAG *CurDAG) {
1557 // Walk all of the chained nodes we've matched, recursively scanning down the
1558 // users of the chain result. This adds any TokenFactor nodes that are caught
1559 // in between chained nodes to the chained and interior nodes list.
1560 SmallVector<SDNode*, 3> InteriorChainedNodes;
1561 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1562 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1563 InteriorChainedNodes) == CR_InducesCycle)
1564 return SDValue(); // Would induce a cycle.
1567 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1568 // that we are interested in. Form our input TokenFactor node.
1569 SmallVector<SDValue, 3> InputChains;
1570 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1571 // Add the input chain of this node to the InputChains list (which will be
1572 // the operands of the generated TokenFactor) if it's not an interior node.
1573 SDNode *N = ChainNodesMatched[i];
1574 if (N->getOpcode() != ISD::TokenFactor) {
1575 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1578 // Otherwise, add the input chain.
1579 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1580 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1581 InputChains.push_back(InChain);
1585 // If we have a token factor, we want to add all inputs of the token factor
1586 // that are not part of the pattern we're matching.
1587 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1588 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1589 N->getOperand(op).getNode()))
1590 InputChains.push_back(N->getOperand(op));
1595 if (InputChains.size() == 1)
1596 return InputChains[0];
1597 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1598 MVT::Other, &InputChains[0], InputChains.size());
1601 /// MorphNode - Handle morphing a node in place for the selector.
1602 SDNode *SelectionDAGISel::
1603 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1604 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1605 // It is possible we're using MorphNodeTo to replace a node with no
1606 // normal results with one that has a normal result (or we could be
1607 // adding a chain) and the input could have flags and chains as well.
1608 // In this case we need to shift the operands down.
1609 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1610 // than the old isel though.
1611 int OldFlagResultNo = -1, OldChainResultNo = -1;
1613 unsigned NTMNumResults = Node->getNumValues();
1614 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1615 OldFlagResultNo = NTMNumResults-1;
1616 if (NTMNumResults != 1 &&
1617 Node->getValueType(NTMNumResults-2) == MVT::Other)
1618 OldChainResultNo = NTMNumResults-2;
1619 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1620 OldChainResultNo = NTMNumResults-1;
1622 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1623 // that this deletes operands of the old node that become dead.
1624 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1626 // MorphNodeTo can operate in two ways: if an existing node with the
1627 // specified operands exists, it can just return it. Otherwise, it
1628 // updates the node in place to have the requested operands.
1630 // If we updated the node in place, reset the node ID. To the isel,
1631 // this should be just like a newly allocated machine node.
1635 unsigned ResNumResults = Res->getNumValues();
1636 // Move the flag if needed.
1637 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1638 (unsigned)OldFlagResultNo != ResNumResults-1)
1639 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1640 SDValue(Res, ResNumResults-1));
1642 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1645 // Move the chain reference if needed.
1646 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1647 (unsigned)OldChainResultNo != ResNumResults-1)
1648 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1649 SDValue(Res, ResNumResults-1));
1651 // Otherwise, no replacement happened because the node already exists. Replace
1652 // Uses of the old node with the new one.
1654 CurDAG->ReplaceAllUsesWith(Node, Res);
1659 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1660 ALWAYS_INLINE static bool
1661 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1662 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1663 // Accept if it is exactly the same as a previously recorded node.
1664 unsigned RecNo = MatcherTable[MatcherIndex++];
1665 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1666 return N == RecordedNodes[RecNo];
1669 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1670 ALWAYS_INLINE static bool
1671 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1672 SelectionDAGISel &SDISel) {
1673 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1676 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1677 ALWAYS_INLINE static bool
1678 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1679 SelectionDAGISel &SDISel, SDNode *N) {
1680 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1683 ALWAYS_INLINE static bool
1684 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1686 uint16_t Opc = MatcherTable[MatcherIndex++];
1687 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1688 return N->getOpcode() == Opc;
1691 ALWAYS_INLINE static bool
1692 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1693 SDValue N, const TargetLowering &TLI) {
1694 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1695 if (N.getValueType() == VT) return true;
1697 // Handle the case when VT is iPTR.
1698 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1701 ALWAYS_INLINE static bool
1702 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1703 SDValue N, const TargetLowering &TLI,
1705 if (ChildNo >= N.getNumOperands())
1706 return false; // Match fails if out of range child #.
1707 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1711 ALWAYS_INLINE static bool
1712 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1714 return cast<CondCodeSDNode>(N)->get() ==
1715 (ISD::CondCode)MatcherTable[MatcherIndex++];
1718 ALWAYS_INLINE static bool
1719 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1720 SDValue N, const TargetLowering &TLI) {
1721 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1722 if (cast<VTSDNode>(N)->getVT() == VT)
1725 // Handle the case when VT is iPTR.
1726 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1729 ALWAYS_INLINE static bool
1730 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1732 int64_t Val = MatcherTable[MatcherIndex++];
1734 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1736 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1737 return C != 0 && C->getSExtValue() == Val;
1740 ALWAYS_INLINE static bool
1741 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1742 SDValue N, SelectionDAGISel &SDISel) {
1743 int64_t Val = MatcherTable[MatcherIndex++];
1745 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1747 if (N->getOpcode() != ISD::AND) return false;
1749 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1750 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1753 ALWAYS_INLINE static bool
1754 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1755 SDValue N, SelectionDAGISel &SDISel) {
1756 int64_t Val = MatcherTable[MatcherIndex++];
1758 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1760 if (N->getOpcode() != ISD::OR) return false;
1762 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1763 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1766 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1767 /// scope, evaluate the current node. If the current predicate is known to
1768 /// fail, set Result=true and return anything. If the current predicate is
1769 /// known to pass, set Result=false and return the MatcherIndex to continue
1770 /// with. If the current predicate is unknown, set Result=false and return the
1771 /// MatcherIndex to continue with.
1772 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1773 unsigned Index, SDValue N,
1774 bool &Result, SelectionDAGISel &SDISel,
1775 SmallVectorImpl<SDValue> &RecordedNodes){
1776 switch (Table[Index++]) {
1779 return Index-1; // Could not evaluate this predicate.
1780 case SelectionDAGISel::OPC_CheckSame:
1781 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1783 case SelectionDAGISel::OPC_CheckPatternPredicate:
1784 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1786 case SelectionDAGISel::OPC_CheckPredicate:
1787 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1789 case SelectionDAGISel::OPC_CheckOpcode:
1790 Result = !::CheckOpcode(Table, Index, N.getNode());
1792 case SelectionDAGISel::OPC_CheckType:
1793 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1795 case SelectionDAGISel::OPC_CheckChild0Type:
1796 case SelectionDAGISel::OPC_CheckChild1Type:
1797 case SelectionDAGISel::OPC_CheckChild2Type:
1798 case SelectionDAGISel::OPC_CheckChild3Type:
1799 case SelectionDAGISel::OPC_CheckChild4Type:
1800 case SelectionDAGISel::OPC_CheckChild5Type:
1801 case SelectionDAGISel::OPC_CheckChild6Type:
1802 case SelectionDAGISel::OPC_CheckChild7Type:
1803 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1804 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1806 case SelectionDAGISel::OPC_CheckCondCode:
1807 Result = !::CheckCondCode(Table, Index, N);
1809 case SelectionDAGISel::OPC_CheckValueType:
1810 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1812 case SelectionDAGISel::OPC_CheckInteger:
1813 Result = !::CheckInteger(Table, Index, N);
1815 case SelectionDAGISel::OPC_CheckAndImm:
1816 Result = !::CheckAndImm(Table, Index, N, SDISel);
1818 case SelectionDAGISel::OPC_CheckOrImm:
1819 Result = !::CheckOrImm(Table, Index, N, SDISel);
1827 /// FailIndex - If this match fails, this is the index to continue with.
1830 /// NodeStack - The node stack when the scope was formed.
1831 SmallVector<SDValue, 4> NodeStack;
1833 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1834 unsigned NumRecordedNodes;
1836 /// NumMatchedMemRefs - The number of matched memref entries.
1837 unsigned NumMatchedMemRefs;
1839 /// InputChain/InputFlag - The current chain/flag
1840 SDValue InputChain, InputFlag;
1842 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1843 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1848 SDNode *SelectionDAGISel::
1849 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1850 unsigned TableSize) {
1851 // FIXME: Should these even be selected? Handle these cases in the caller?
1852 switch (NodeToMatch->getOpcode()) {
1855 case ISD::EntryToken: // These nodes remain the same.
1856 case ISD::BasicBlock:
1858 //case ISD::VALUETYPE:
1859 //case ISD::CONDCODE:
1860 case ISD::HANDLENODE:
1861 case ISD::MDNODE_SDNODE:
1862 case ISD::TargetConstant:
1863 case ISD::TargetConstantFP:
1864 case ISD::TargetConstantPool:
1865 case ISD::TargetFrameIndex:
1866 case ISD::TargetExternalSymbol:
1867 case ISD::TargetBlockAddress:
1868 case ISD::TargetJumpTable:
1869 case ISD::TargetGlobalTLSAddress:
1870 case ISD::TargetGlobalAddress:
1871 case ISD::TokenFactor:
1872 case ISD::CopyFromReg:
1873 case ISD::CopyToReg:
1875 NodeToMatch->setNodeId(-1); // Mark selected.
1877 case ISD::AssertSext:
1878 case ISD::AssertZext:
1879 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1880 NodeToMatch->getOperand(0));
1882 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1883 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1886 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1888 // Set up the node stack with NodeToMatch as the only node on the stack.
1889 SmallVector<SDValue, 8> NodeStack;
1890 SDValue N = SDValue(NodeToMatch, 0);
1891 NodeStack.push_back(N);
1893 // MatchScopes - Scopes used when matching, if a match failure happens, this
1894 // indicates where to continue checking.
1895 SmallVector<MatchScope, 8> MatchScopes;
1897 // RecordedNodes - This is the set of nodes that have been recorded by the
1899 SmallVector<SDValue, 8> RecordedNodes;
1901 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1903 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1905 // These are the current input chain and flag for use when generating nodes.
1906 // Various Emit operations change these. For example, emitting a copytoreg
1907 // uses and updates these.
1908 SDValue InputChain, InputFlag;
1910 // ChainNodesMatched - If a pattern matches nodes that have input/output
1911 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1912 // which ones they are. The result is captured into this list so that we can
1913 // update the chain results when the pattern is complete.
1914 SmallVector<SDNode*, 3> ChainNodesMatched;
1915 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1917 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1918 NodeToMatch->dump(CurDAG);
1921 // Determine where to start the interpreter. Normally we start at opcode #0,
1922 // but if the state machine starts with an OPC_SwitchOpcode, then we
1923 // accelerate the first lookup (which is guaranteed to be hot) with the
1924 // OpcodeOffset table.
1925 unsigned MatcherIndex = 0;
1927 if (!OpcodeOffset.empty()) {
1928 // Already computed the OpcodeOffset table, just index into it.
1929 if (N.getOpcode() < OpcodeOffset.size())
1930 MatcherIndex = OpcodeOffset[N.getOpcode()];
1931 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1933 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1934 // Otherwise, the table isn't computed, but the state machine does start
1935 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1936 // is the first time we're selecting an instruction.
1939 // Get the size of this case.
1940 unsigned CaseSize = MatcherTable[Idx++];
1942 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1943 if (CaseSize == 0) break;
1945 // Get the opcode, add the index to the table.
1946 uint16_t Opc = MatcherTable[Idx++];
1947 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
1948 if (Opc >= OpcodeOffset.size())
1949 OpcodeOffset.resize((Opc+1)*2);
1950 OpcodeOffset[Opc] = Idx;
1954 // Okay, do the lookup for the first opcode.
1955 if (N.getOpcode() < OpcodeOffset.size())
1956 MatcherIndex = OpcodeOffset[N.getOpcode()];
1960 assert(MatcherIndex < TableSize && "Invalid index");
1962 unsigned CurrentOpcodeIndex = MatcherIndex;
1964 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
1967 // Okay, the semantics of this operation are that we should push a scope
1968 // then evaluate the first child. However, pushing a scope only to have
1969 // the first check fail (which then pops it) is inefficient. If we can
1970 // determine immediately that the first check (or first several) will
1971 // immediately fail, don't even bother pushing a scope for them.
1975 unsigned NumToSkip = MatcherTable[MatcherIndex++];
1976 if (NumToSkip & 128)
1977 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
1978 // Found the end of the scope with no match.
1979 if (NumToSkip == 0) {
1984 FailIndex = MatcherIndex+NumToSkip;
1986 unsigned MatcherIndexOfPredicate = MatcherIndex;
1987 (void)MatcherIndexOfPredicate; // silence warning.
1989 // If we can't evaluate this predicate without pushing a scope (e.g. if
1990 // it is a 'MoveParent') or if the predicate succeeds on this node, we
1991 // push the scope and evaluate the full predicate chain.
1993 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
1994 Result, *this, RecordedNodes);
1998 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
1999 << "index " << MatcherIndexOfPredicate
2000 << ", continuing at " << FailIndex << "\n");
2001 ++NumDAGIselRetries;
2003 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2004 // move to the next case.
2005 MatcherIndex = FailIndex;
2008 // If the whole scope failed to match, bail.
2009 if (FailIndex == 0) break;
2011 // Push a MatchScope which indicates where to go if the first child fails
2013 MatchScope NewEntry;
2014 NewEntry.FailIndex = FailIndex;
2015 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2016 NewEntry.NumRecordedNodes = RecordedNodes.size();
2017 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2018 NewEntry.InputChain = InputChain;
2019 NewEntry.InputFlag = InputFlag;
2020 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2021 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2022 MatchScopes.push_back(NewEntry);
2025 case OPC_RecordNode:
2026 // Remember this node, it may end up being an operand in the pattern.
2027 RecordedNodes.push_back(N);
2030 case OPC_RecordChild0: case OPC_RecordChild1:
2031 case OPC_RecordChild2: case OPC_RecordChild3:
2032 case OPC_RecordChild4: case OPC_RecordChild5:
2033 case OPC_RecordChild6: case OPC_RecordChild7: {
2034 unsigned ChildNo = Opcode-OPC_RecordChild0;
2035 if (ChildNo >= N.getNumOperands())
2036 break; // Match fails if out of range child #.
2038 RecordedNodes.push_back(N->getOperand(ChildNo));
2041 case OPC_RecordMemRef:
2042 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2045 case OPC_CaptureFlagInput:
2046 // If the current node has an input flag, capture it in InputFlag.
2047 if (N->getNumOperands() != 0 &&
2048 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2049 InputFlag = N->getOperand(N->getNumOperands()-1);
2052 case OPC_MoveChild: {
2053 unsigned ChildNo = MatcherTable[MatcherIndex++];
2054 if (ChildNo >= N.getNumOperands())
2055 break; // Match fails if out of range child #.
2056 N = N.getOperand(ChildNo);
2057 NodeStack.push_back(N);
2061 case OPC_MoveParent:
2062 // Pop the current node off the NodeStack.
2063 NodeStack.pop_back();
2064 assert(!NodeStack.empty() && "Node stack imbalance!");
2065 N = NodeStack.back();
2069 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2071 case OPC_CheckPatternPredicate:
2072 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2074 case OPC_CheckPredicate:
2075 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2079 case OPC_CheckComplexPat: {
2080 unsigned CPNum = MatcherTable[MatcherIndex++];
2081 unsigned RecNo = MatcherTable[MatcherIndex++];
2082 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2083 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2088 case OPC_CheckOpcode:
2089 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2093 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2096 case OPC_SwitchOpcode: {
2097 unsigned CurNodeOpcode = N.getOpcode();
2098 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2101 // Get the size of this case.
2102 CaseSize = MatcherTable[MatcherIndex++];
2104 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2105 if (CaseSize == 0) break;
2107 uint16_t Opc = MatcherTable[MatcherIndex++];
2108 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2110 // If the opcode matches, then we will execute this case.
2111 if (CurNodeOpcode == Opc)
2114 // Otherwise, skip over this case.
2115 MatcherIndex += CaseSize;
2118 // If no cases matched, bail out.
2119 if (CaseSize == 0) break;
2121 // Otherwise, execute the case we found.
2122 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2123 << " to " << MatcherIndex << "\n");
2127 case OPC_SwitchType: {
2128 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2129 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2132 // Get the size of this case.
2133 CaseSize = MatcherTable[MatcherIndex++];
2135 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2136 if (CaseSize == 0) break;
2138 MVT::SimpleValueType CaseVT =
2139 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2140 if (CaseVT == MVT::iPTR)
2141 CaseVT = TLI.getPointerTy().SimpleTy;
2143 // If the VT matches, then we will execute this case.
2144 if (CurNodeVT == CaseVT)
2147 // Otherwise, skip over this case.
2148 MatcherIndex += CaseSize;
2151 // If no cases matched, bail out.
2152 if (CaseSize == 0) break;
2154 // Otherwise, execute the case we found.
2155 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2156 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2159 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2160 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2161 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2162 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2163 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2164 Opcode-OPC_CheckChild0Type))
2167 case OPC_CheckCondCode:
2168 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2170 case OPC_CheckValueType:
2171 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2173 case OPC_CheckInteger:
2174 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2176 case OPC_CheckAndImm:
2177 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2179 case OPC_CheckOrImm:
2180 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2183 case OPC_CheckFoldableChainNode: {
2184 assert(NodeStack.size() != 1 && "No parent node");
2185 // Verify that all intermediate nodes between the root and this one have
2187 bool HasMultipleUses = false;
2188 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2189 if (!NodeStack[i].hasOneUse()) {
2190 HasMultipleUses = true;
2193 if (HasMultipleUses) break;
2195 // Check to see that the target thinks this is profitable to fold and that
2196 // we can fold it without inducing cycles in the graph.
2197 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2199 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2200 NodeToMatch, OptLevel,
2201 true/*We validate our own chains*/))
2206 case OPC_EmitInteger: {
2207 MVT::SimpleValueType VT =
2208 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2209 int64_t Val = MatcherTable[MatcherIndex++];
2211 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2212 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2215 case OPC_EmitRegister: {
2216 MVT::SimpleValueType VT =
2217 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2218 unsigned RegNo = MatcherTable[MatcherIndex++];
2219 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2223 case OPC_EmitConvertToTarget: {
2224 // Convert from IMM/FPIMM to target version.
2225 unsigned RecNo = MatcherTable[MatcherIndex++];
2226 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2227 SDValue Imm = RecordedNodes[RecNo];
2229 if (Imm->getOpcode() == ISD::Constant) {
2230 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2231 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2232 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2233 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2234 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2237 RecordedNodes.push_back(Imm);
2241 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2242 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2243 // These are space-optimized forms of OPC_EmitMergeInputChains.
2244 assert(InputChain.getNode() == 0 &&
2245 "EmitMergeInputChains should be the first chain producing node");
2246 assert(ChainNodesMatched.empty() &&
2247 "Should only have one EmitMergeInputChains per match");
2249 // Read all of the chained nodes.
2250 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2251 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2252 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2254 // FIXME: What if other value results of the node have uses not matched
2256 if (ChainNodesMatched.back() != NodeToMatch &&
2257 !RecordedNodes[RecNo].hasOneUse()) {
2258 ChainNodesMatched.clear();
2262 // Merge the input chains if they are not intra-pattern references.
2263 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2265 if (InputChain.getNode() == 0)
2266 break; // Failed to merge.
2270 case OPC_EmitMergeInputChains: {
2271 assert(InputChain.getNode() == 0 &&
2272 "EmitMergeInputChains should be the first chain producing node");
2273 // This node gets a list of nodes we matched in the input that have
2274 // chains. We want to token factor all of the input chains to these nodes
2275 // together. However, if any of the input chains is actually one of the
2276 // nodes matched in this pattern, then we have an intra-match reference.
2277 // Ignore these because the newly token factored chain should not refer to
2279 unsigned NumChains = MatcherTable[MatcherIndex++];
2280 assert(NumChains != 0 && "Can't TF zero chains");
2282 assert(ChainNodesMatched.empty() &&
2283 "Should only have one EmitMergeInputChains per match");
2285 // Read all of the chained nodes.
2286 for (unsigned i = 0; i != NumChains; ++i) {
2287 unsigned RecNo = MatcherTable[MatcherIndex++];
2288 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2289 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2291 // FIXME: What if other value results of the node have uses not matched
2293 if (ChainNodesMatched.back() != NodeToMatch &&
2294 !RecordedNodes[RecNo].hasOneUse()) {
2295 ChainNodesMatched.clear();
2300 // If the inner loop broke out, the match fails.
2301 if (ChainNodesMatched.empty())
2304 // Merge the input chains if they are not intra-pattern references.
2305 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2307 if (InputChain.getNode() == 0)
2308 break; // Failed to merge.
2313 case OPC_EmitCopyToReg: {
2314 unsigned RecNo = MatcherTable[MatcherIndex++];
2315 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2316 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2318 if (InputChain.getNode() == 0)
2319 InputChain = CurDAG->getEntryNode();
2321 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2322 DestPhysReg, RecordedNodes[RecNo],
2325 InputFlag = InputChain.getValue(1);
2329 case OPC_EmitNodeXForm: {
2330 unsigned XFormNo = MatcherTable[MatcherIndex++];
2331 unsigned RecNo = MatcherTable[MatcherIndex++];
2332 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2333 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2338 case OPC_MorphNodeTo: {
2339 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2340 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2341 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2342 // Get the result VT list.
2343 unsigned NumVTs = MatcherTable[MatcherIndex++];
2344 SmallVector<EVT, 4> VTs;
2345 for (unsigned i = 0; i != NumVTs; ++i) {
2346 MVT::SimpleValueType VT =
2347 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2348 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2352 if (EmitNodeInfo & OPFL_Chain)
2353 VTs.push_back(MVT::Other);
2354 if (EmitNodeInfo & OPFL_FlagOutput)
2355 VTs.push_back(MVT::Flag);
2357 // This is hot code, so optimize the two most common cases of 1 and 2
2360 if (VTs.size() == 1)
2361 VTList = CurDAG->getVTList(VTs[0]);
2362 else if (VTs.size() == 2)
2363 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2365 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2367 // Get the operand list.
2368 unsigned NumOps = MatcherTable[MatcherIndex++];
2369 SmallVector<SDValue, 8> Ops;
2370 for (unsigned i = 0; i != NumOps; ++i) {
2371 unsigned RecNo = MatcherTable[MatcherIndex++];
2373 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2375 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2376 Ops.push_back(RecordedNodes[RecNo]);
2379 // If there are variadic operands to add, handle them now.
2380 if (EmitNodeInfo & OPFL_VariadicInfo) {
2381 // Determine the start index to copy from.
2382 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2383 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2384 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2385 "Invalid variadic node");
2386 // Copy all of the variadic operands, not including a potential flag
2388 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2390 SDValue V = NodeToMatch->getOperand(i);
2391 if (V.getValueType() == MVT::Flag) break;
2396 // If this has chain/flag inputs, add them.
2397 if (EmitNodeInfo & OPFL_Chain)
2398 Ops.push_back(InputChain);
2399 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2400 Ops.push_back(InputFlag);
2404 if (Opcode != OPC_MorphNodeTo) {
2405 // If this is a normal EmitNode command, just create the new node and
2406 // add the results to the RecordedNodes list.
2407 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2408 VTList, Ops.data(), Ops.size());
2410 // Add all the non-flag/non-chain results to the RecordedNodes list.
2411 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2412 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2413 RecordedNodes.push_back(SDValue(Res, i));
2417 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2421 // If the node had chain/flag results, update our notion of the current
2423 if (EmitNodeInfo & OPFL_FlagOutput) {
2424 InputFlag = SDValue(Res, VTs.size()-1);
2425 if (EmitNodeInfo & OPFL_Chain)
2426 InputChain = SDValue(Res, VTs.size()-2);
2427 } else if (EmitNodeInfo & OPFL_Chain)
2428 InputChain = SDValue(Res, VTs.size()-1);
2430 // If the OPFL_MemRefs flag is set on this node, slap all of the
2431 // accumulated memrefs onto it.
2433 // FIXME: This is vastly incorrect for patterns with multiple outputs
2434 // instructions that access memory and for ComplexPatterns that match
2436 if (EmitNodeInfo & OPFL_MemRefs) {
2437 MachineSDNode::mmo_iterator MemRefs =
2438 MF->allocateMemRefsArray(MatchedMemRefs.size());
2439 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2440 cast<MachineSDNode>(Res)
2441 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2445 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2446 << " node: "; Res->dump(CurDAG); errs() << "\n");
2448 // If this was a MorphNodeTo then we're completely done!
2449 if (Opcode == OPC_MorphNodeTo) {
2450 // Update chain and flag uses.
2451 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2452 InputFlag, FlagResultNodesMatched, true);
2459 case OPC_MarkFlagResults: {
2460 unsigned NumNodes = MatcherTable[MatcherIndex++];
2462 // Read and remember all the flag-result nodes.
2463 for (unsigned i = 0; i != NumNodes; ++i) {
2464 unsigned RecNo = MatcherTable[MatcherIndex++];
2466 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2468 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2469 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2474 case OPC_CompleteMatch: {
2475 // The match has been completed, and any new nodes (if any) have been
2476 // created. Patch up references to the matched dag to use the newly
2478 unsigned NumResults = MatcherTable[MatcherIndex++];
2480 for (unsigned i = 0; i != NumResults; ++i) {
2481 unsigned ResSlot = MatcherTable[MatcherIndex++];
2483 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2485 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2486 SDValue Res = RecordedNodes[ResSlot];
2488 assert(i < NodeToMatch->getNumValues() &&
2489 NodeToMatch->getValueType(i) != MVT::Other &&
2490 NodeToMatch->getValueType(i) != MVT::Flag &&
2491 "Invalid number of results to complete!");
2492 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2493 NodeToMatch->getValueType(i) == MVT::iPTR ||
2494 Res.getValueType() == MVT::iPTR ||
2495 NodeToMatch->getValueType(i).getSizeInBits() ==
2496 Res.getValueType().getSizeInBits()) &&
2497 "invalid replacement");
2498 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2501 // If the root node defines a flag, add it to the flag nodes to update
2503 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2504 FlagResultNodesMatched.push_back(NodeToMatch);
2506 // Update chain and flag uses.
2507 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2508 InputFlag, FlagResultNodesMatched, false);
2510 assert(NodeToMatch->use_empty() &&
2511 "Didn't replace all uses of the node?");
2513 // FIXME: We just return here, which interacts correctly with SelectRoot
2514 // above. We should fix this to not return an SDNode* anymore.
2519 // If the code reached this point, then the match failed. See if there is
2520 // another child to try in the current 'Scope', otherwise pop it until we
2521 // find a case to check.
2522 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2523 ++NumDAGIselRetries;
2525 if (MatchScopes.empty()) {
2526 CannotYetSelect(NodeToMatch);
2530 // Restore the interpreter state back to the point where the scope was
2532 MatchScope &LastScope = MatchScopes.back();
2533 RecordedNodes.resize(LastScope.NumRecordedNodes);
2535 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2536 N = NodeStack.back();
2538 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2539 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2540 MatcherIndex = LastScope.FailIndex;
2542 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2544 InputChain = LastScope.InputChain;
2545 InputFlag = LastScope.InputFlag;
2546 if (!LastScope.HasChainNodesMatched)
2547 ChainNodesMatched.clear();
2548 if (!LastScope.HasFlagResultNodesMatched)
2549 FlagResultNodesMatched.clear();
2551 // Check to see what the offset is at the new MatcherIndex. If it is zero
2552 // we have reached the end of this scope, otherwise we have another child
2553 // in the current scope to try.
2554 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2555 if (NumToSkip & 128)
2556 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2558 // If we have another child in this scope to match, update FailIndex and
2560 if (NumToSkip != 0) {
2561 LastScope.FailIndex = MatcherIndex+NumToSkip;
2565 // End of this scope, pop it and try the next child in the containing
2567 MatchScopes.pop_back();
2574 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2576 raw_string_ostream Msg(msg);
2577 Msg << "Cannot yet select: ";
2579 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2580 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2581 N->getOpcode() != ISD::INTRINSIC_VOID) {
2582 N->printrFull(Msg, CurDAG);
2584 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2586 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2587 if (iid < Intrinsic::num_intrinsics)
2588 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2589 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2590 Msg << "target intrinsic %" << TII->getName(iid);
2592 Msg << "unknown intrinsic #" << iid;
2594 report_fatal_error(Msg.str());
2597 char SelectionDAGISel::ID = 0;