1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/MRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/Compiler.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
60 cl::desc("Pop up a window to show SUnit dags after they are processed"));
62 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
65 //===---------------------------------------------------------------------===//
67 /// RegisterScheduler class - Track the registration of instruction schedulers.
69 //===---------------------------------------------------------------------===//
70 MachinePassRegistry RegisterScheduler::Registry;
72 //===---------------------------------------------------------------------===//
74 /// ISHeuristic command line option for instruction schedulers.
76 //===---------------------------------------------------------------------===//
78 cl::opt<RegisterScheduler::FunctionPassCtor, false,
79 RegisterPassParser<RegisterScheduler> >
80 ISHeuristic("pre-RA-sched",
81 cl::init(&createDefaultScheduler),
82 cl::desc("Instruction schedulers available (before register allocation):"));
84 static RegisterScheduler
85 defaultListDAGScheduler("default", " Best scheduler for the target",
86 createDefaultScheduler);
89 namespace { struct AsmOperandInfo; }
92 /// RegsForValue - This struct represents the physical registers that a
93 /// particular value is assigned and the type information about the value.
94 /// This is needed because values can be promoted into larger registers and
95 /// expanded into multiple smaller registers than the value.
96 struct VISIBILITY_HIDDEN RegsForValue {
97 /// Regs - This list holds the register (for legal and promoted values)
98 /// or register set (for expanded values) that the value should be assigned
100 std::vector<unsigned> Regs;
102 /// RegVT - The value type of each register.
104 MVT::ValueType RegVT;
106 /// ValueVT - The value type of the LLVM value, which may be promoted from
107 /// RegVT or made from merging the two expanded parts.
108 MVT::ValueType ValueVT;
110 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
112 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
113 : RegVT(regvt), ValueVT(valuevt) {
116 RegsForValue(const std::vector<unsigned> ®s,
117 MVT::ValueType regvt, MVT::ValueType valuevt)
118 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
121 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
122 /// this value and returns the result as a ValueVT value. This uses
123 /// Chain/Flag as the input and updates them for the output Chain/Flag.
124 /// If the Flag pointer is NULL, no flag is used.
125 SDOperand getCopyFromRegs(SelectionDAG &DAG,
126 SDOperand &Chain, SDOperand *Flag) const;
128 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
129 /// specified value into the registers specified by this object. This uses
130 /// Chain/Flag as the input and updates them for the output Chain/Flag.
131 /// If the Flag pointer is NULL, no flag is used.
132 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
133 SDOperand &Chain, SDOperand *Flag) const;
135 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
136 /// operand list. This adds the code marker and includes the number of
137 /// values added into it.
138 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
139 std::vector<SDOperand> &Ops) const;
144 //===--------------------------------------------------------------------===//
145 /// createDefaultScheduler - This creates an instruction scheduler appropriate
147 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
149 MachineBasicBlock *BB) {
150 TargetLowering &TLI = IS->getTargetLowering();
152 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
153 return createTDListDAGScheduler(IS, DAG, BB);
155 assert(TLI.getSchedulingPreference() ==
156 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
157 return createBURRListDAGScheduler(IS, DAG, BB);
162 //===--------------------------------------------------------------------===//
163 /// FunctionLoweringInfo - This contains information that is global to a
164 /// function that is used when lowering a region of the function.
165 class FunctionLoweringInfo {
170 MachineRegisterInfo &RegInfo;
172 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
174 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
175 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
177 /// ValueMap - Since we emit code for the function a basic block at a time,
178 /// we must remember which virtual registers hold the values for
179 /// cross-basic-block values.
180 DenseMap<const Value*, unsigned> ValueMap;
182 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
183 /// the entry block. This allows the allocas to be efficiently referenced
184 /// anywhere in the function.
185 std::map<const AllocaInst*, int> StaticAllocaMap;
188 SmallSet<Instruction*, 8> CatchInfoLost;
189 SmallSet<Instruction*, 8> CatchInfoFound;
192 unsigned MakeReg(MVT::ValueType VT) {
193 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
196 /// isExportedInst - Return true if the specified value is an instruction
197 /// exported from its block.
198 bool isExportedInst(const Value *V) {
199 return ValueMap.count(V);
202 unsigned CreateRegForValue(const Value *V);
204 unsigned InitializeRegForValue(const Value *V) {
205 unsigned &R = ValueMap[V];
206 assert(R == 0 && "Already initialized this value register!");
207 return R = CreateRegForValue(V);
212 /// isSelector - Return true if this instruction is a call to the
213 /// eh.selector intrinsic.
214 static bool isSelector(Instruction *I) {
215 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
216 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
217 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
221 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
222 /// PHI nodes or outside of the basic block that defines it, or used by a
223 /// switch instruction, which may expand to multiple basic blocks.
224 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
225 if (isa<PHINode>(I)) return true;
226 BasicBlock *BB = I->getParent();
227 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
228 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
229 // FIXME: Remove switchinst special case.
230 isa<SwitchInst>(*UI))
235 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
236 /// entry block, return true. This includes arguments used by switches, since
237 /// the switch may expand into multiple basic blocks.
238 static bool isOnlyUsedInEntryBlock(Argument *A) {
239 BasicBlock *Entry = A->getParent()->begin();
240 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
241 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
242 return false; // Use not in entry block.
246 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
247 Function &fn, MachineFunction &mf)
248 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
250 // Create a vreg for each argument register that is not dead and is used
251 // outside of the entry block for the function.
252 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
254 if (!isOnlyUsedInEntryBlock(AI))
255 InitializeRegForValue(AI);
257 // Initialize the mapping of values to registers. This is only set up for
258 // instruction values that are used outside of the block that defines
260 Function::iterator BB = Fn.begin(), EB = Fn.end();
261 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
262 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
263 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
264 const Type *Ty = AI->getAllocatedType();
265 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
267 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
270 TySize *= CUI->getZExtValue(); // Get total allocated size.
271 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
272 StaticAllocaMap[AI] =
273 MF.getFrameInfo()->CreateStackObject(TySize, Align);
276 for (; BB != EB; ++BB)
277 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
278 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
279 if (!isa<AllocaInst>(I) ||
280 !StaticAllocaMap.count(cast<AllocaInst>(I)))
281 InitializeRegForValue(I);
283 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
284 // also creates the initial PHI MachineInstrs, though none of the input
285 // operands are populated.
286 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
287 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
289 MF.getBasicBlockList().push_back(MBB);
291 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
294 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
295 if (PN->use_empty()) continue;
297 MVT::ValueType VT = TLI.getValueType(PN->getType());
298 unsigned NumRegisters = TLI.getNumRegisters(VT);
299 unsigned PHIReg = ValueMap[PN];
300 assert(PHIReg && "PHI node does not have an assigned virtual register!");
301 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
302 for (unsigned i = 0; i != NumRegisters; ++i)
303 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
308 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
309 /// the correctly promoted or expanded types. Assign these registers
310 /// consecutive vreg numbers and return the first assigned number.
311 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
312 MVT::ValueType VT = TLI.getValueType(V->getType());
314 unsigned NumRegisters = TLI.getNumRegisters(VT);
315 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
317 unsigned R = MakeReg(RegisterVT);
318 for (unsigned i = 1; i != NumRegisters; ++i)
324 //===----------------------------------------------------------------------===//
325 /// SelectionDAGLowering - This is the common target-independent lowering
326 /// implementation that is parameterized by a TargetLowering object.
327 /// Also, targets can overload any lowering method.
330 class SelectionDAGLowering {
331 MachineBasicBlock *CurMBB;
333 DenseMap<const Value*, SDOperand> NodeMap;
335 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
336 /// them up and then emit token factor nodes when possible. This allows us to
337 /// get simple disambiguation between loads without worrying about alias
339 std::vector<SDOperand> PendingLoads;
341 /// Case - A struct to record the Value for a switch case, and the
342 /// case's target basic block.
346 MachineBasicBlock* BB;
348 Case() : Low(0), High(0), BB(0) { }
349 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
350 Low(low), High(high), BB(bb) { }
351 uint64_t size() const {
352 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
353 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
354 return (rHigh - rLow + 1ULL);
360 MachineBasicBlock* BB;
363 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
364 Mask(mask), BB(bb), Bits(bits) { }
367 typedef std::vector<Case> CaseVector;
368 typedef std::vector<CaseBits> CaseBitsVector;
369 typedef CaseVector::iterator CaseItr;
370 typedef std::pair<CaseItr, CaseItr> CaseRange;
372 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
373 /// of conditional branches.
375 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
376 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
378 /// CaseBB - The MBB in which to emit the compare and branch
379 MachineBasicBlock *CaseBB;
380 /// LT, GE - If nonzero, we know the current case value must be less-than or
381 /// greater-than-or-equal-to these Constants.
384 /// Range - A pair of iterators representing the range of case values to be
385 /// processed at this point in the binary search tree.
389 typedef std::vector<CaseRec> CaseRecVector;
391 /// The comparison function for sorting the switch case values in the vector.
392 /// WARNING: Case ranges should be disjoint!
394 bool operator () (const Case& C1, const Case& C2) {
395 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
396 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
397 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
398 return CI1->getValue().slt(CI2->getValue());
403 bool operator () (const CaseBits& C1, const CaseBits& C2) {
404 return C1.Bits > C2.Bits;
408 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
411 // TLI - This is information that describes the available target features we
412 // need for lowering. This indicates when operations are unavailable,
413 // implemented with a libcall, etc.
416 const TargetData *TD;
419 /// SwitchCases - Vector of CaseBlock structures used to communicate
420 /// SwitchInst code generation information.
421 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
422 /// JTCases - Vector of JumpTable structures used to communicate
423 /// SwitchInst code generation information.
424 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
425 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
427 /// FuncInfo - Information about the function as a whole.
429 FunctionLoweringInfo &FuncInfo;
431 /// GCI - Garbage collection metadata for the function.
432 CollectorMetadata *GCI;
434 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
436 FunctionLoweringInfo &funcinfo,
437 CollectorMetadata *gci)
438 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
439 FuncInfo(funcinfo), GCI(gci) {
442 /// getRoot - Return the current virtual root of the Selection DAG.
444 SDOperand getRoot() {
445 if (PendingLoads.empty())
446 return DAG.getRoot();
448 if (PendingLoads.size() == 1) {
449 SDOperand Root = PendingLoads[0];
451 PendingLoads.clear();
455 // Otherwise, we have to make a token factor node.
456 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
457 &PendingLoads[0], PendingLoads.size());
458 PendingLoads.clear();
463 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
465 void visit(Instruction &I) { visit(I.getOpcode(), I); }
467 void visit(unsigned Opcode, User &I) {
468 // Note: this doesn't use InstVisitor, because it has to work with
469 // ConstantExpr's in addition to instructions.
471 default: assert(0 && "Unknown instruction type encountered!");
473 // Build the switch statement using the Instruction.def file.
474 #define HANDLE_INST(NUM, OPCODE, CLASS) \
475 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
476 #include "llvm/Instruction.def"
480 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
482 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
483 const Value *SV, SDOperand Root,
484 bool isVolatile, unsigned Alignment);
486 SDOperand getIntPtrConstant(uint64_t Val) {
487 return DAG.getConstant(Val, TLI.getPointerTy());
490 SDOperand getValue(const Value *V);
492 void setValue(const Value *V, SDOperand NewN) {
493 SDOperand &N = NodeMap[V];
494 assert(N.Val == 0 && "Already set a value for this node!");
498 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
499 std::set<unsigned> &OutputRegs,
500 std::set<unsigned> &InputRegs);
502 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
503 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
505 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
506 void ExportFromCurrentBlock(Value *V);
507 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
508 MachineBasicBlock *LandingPad = NULL);
510 // Terminator instructions.
511 void visitRet(ReturnInst &I);
512 void visitBr(BranchInst &I);
513 void visitSwitch(SwitchInst &I);
514 void visitUnreachable(UnreachableInst &I) { /* noop */ }
516 // Helpers for visitSwitch
517 bool handleSmallSwitchRange(CaseRec& CR,
518 CaseRecVector& WorkList,
520 MachineBasicBlock* Default);
521 bool handleJTSwitchCase(CaseRec& CR,
522 CaseRecVector& WorkList,
524 MachineBasicBlock* Default);
525 bool handleBTSplitSwitchCase(CaseRec& CR,
526 CaseRecVector& WorkList,
528 MachineBasicBlock* Default);
529 bool handleBitTestsSwitchCase(CaseRec& CR,
530 CaseRecVector& WorkList,
532 MachineBasicBlock* Default);
533 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
534 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
535 void visitBitTestCase(MachineBasicBlock* NextMBB,
537 SelectionDAGISel::BitTestCase &B);
538 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
539 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
540 SelectionDAGISel::JumpTableHeader &JTH);
542 // These all get lowered before this pass.
543 void visitInvoke(InvokeInst &I);
544 void visitUnwind(UnwindInst &I);
546 void visitBinary(User &I, unsigned OpCode);
547 void visitShift(User &I, unsigned Opcode);
548 void visitAdd(User &I) {
549 if (I.getType()->isFPOrFPVector())
550 visitBinary(I, ISD::FADD);
552 visitBinary(I, ISD::ADD);
554 void visitSub(User &I);
555 void visitMul(User &I) {
556 if (I.getType()->isFPOrFPVector())
557 visitBinary(I, ISD::FMUL);
559 visitBinary(I, ISD::MUL);
561 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
562 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
563 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
564 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
565 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
566 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
567 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
568 void visitOr (User &I) { visitBinary(I, ISD::OR); }
569 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
570 void visitShl (User &I) { visitShift(I, ISD::SHL); }
571 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
572 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
573 void visitICmp(User &I);
574 void visitFCmp(User &I);
575 // Visit the conversion instructions
576 void visitTrunc(User &I);
577 void visitZExt(User &I);
578 void visitSExt(User &I);
579 void visitFPTrunc(User &I);
580 void visitFPExt(User &I);
581 void visitFPToUI(User &I);
582 void visitFPToSI(User &I);
583 void visitUIToFP(User &I);
584 void visitSIToFP(User &I);
585 void visitPtrToInt(User &I);
586 void visitIntToPtr(User &I);
587 void visitBitCast(User &I);
589 void visitExtractElement(User &I);
590 void visitInsertElement(User &I);
591 void visitShuffleVector(User &I);
593 void visitGetElementPtr(User &I);
594 void visitSelect(User &I);
596 void visitMalloc(MallocInst &I);
597 void visitFree(FreeInst &I);
598 void visitAlloca(AllocaInst &I);
599 void visitLoad(LoadInst &I);
600 void visitStore(StoreInst &I);
601 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
602 void visitCall(CallInst &I);
603 void visitInlineAsm(CallSite CS);
604 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
605 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
607 void visitVAStart(CallInst &I);
608 void visitVAArg(VAArgInst &I);
609 void visitVAEnd(CallInst &I);
610 void visitVACopy(CallInst &I);
612 void visitMemIntrinsic(CallInst &I, unsigned Op);
614 void visitUserOp1(Instruction &I) {
615 assert(0 && "UserOp1 should not exist at instruction selection time!");
618 void visitUserOp2(Instruction &I) {
619 assert(0 && "UserOp2 should not exist at instruction selection time!");
623 } // end namespace llvm
626 /// getCopyFromParts - Create a value that contains the
627 /// specified legal parts combined into the value they represent.
628 static SDOperand getCopyFromParts(SelectionDAG &DAG,
629 const SDOperand *Parts,
631 MVT::ValueType PartVT,
632 MVT::ValueType ValueVT,
633 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
634 if (!MVT::isVector(ValueVT) || NumParts == 1) {
635 SDOperand Val = Parts[0];
637 // If the value was expanded, copy from the top part.
639 assert(NumParts == 2 &&
640 "Cannot expand to more than 2 elts yet!");
641 SDOperand Hi = Parts[1];
642 if (!DAG.getTargetLoweringInfo().isLittleEndian())
644 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
647 // Otherwise, if the value was promoted or extended, truncate it to the
649 if (PartVT == ValueVT)
652 if (MVT::isVector(PartVT)) {
653 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
654 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
657 if (MVT::isVector(ValueVT)) {
658 assert(NumParts == 1 &&
659 MVT::getVectorElementType(ValueVT) == PartVT &&
660 MVT::getVectorNumElements(ValueVT) == 1 &&
661 "Only trivial scalar-to-vector conversions should get here!");
662 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
665 if (MVT::isInteger(PartVT) &&
666 MVT::isInteger(ValueVT)) {
667 if (ValueVT < PartVT) {
668 // For a truncate, see if we have any information to
669 // indicate whether the truncated bits will always be
670 // zero or sign-extension.
671 if (AssertOp != ISD::DELETED_NODE)
672 Val = DAG.getNode(AssertOp, PartVT, Val,
673 DAG.getValueType(ValueVT));
674 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
676 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
680 if (MVT::isFloatingPoint(PartVT) &&
681 MVT::isFloatingPoint(ValueVT))
682 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
684 if (MVT::getSizeInBits(PartVT) ==
685 MVT::getSizeInBits(ValueVT))
686 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
688 assert(0 && "Unknown mismatch!");
691 // Handle a multi-element vector.
692 MVT::ValueType IntermediateVT, RegisterVT;
693 unsigned NumIntermediates;
695 DAG.getTargetLoweringInfo()
696 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
699 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
700 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
701 assert(RegisterVT == Parts[0].getValueType() &&
702 "Part type doesn't match part!");
704 // Assemble the parts into intermediate operands.
705 SmallVector<SDOperand, 8> Ops(NumIntermediates);
706 if (NumIntermediates == NumParts) {
707 // If the register was not expanded, truncate or copy the value,
709 for (unsigned i = 0; i != NumParts; ++i)
710 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
711 PartVT, IntermediateVT);
712 } else if (NumParts > 0) {
713 // If the intermediate type was expanded, build the intermediate operands
715 assert(NumParts % NumIntermediates == 0 &&
716 "Must expand into a divisible number of parts!");
717 unsigned Factor = NumParts / NumIntermediates;
718 for (unsigned i = 0; i != NumIntermediates; ++i)
719 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
720 PartVT, IntermediateVT);
723 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
725 return DAG.getNode(MVT::isVector(IntermediateVT) ?
726 ISD::CONCAT_VECTORS :
728 ValueVT, &Ops[0], NumIntermediates);
731 /// getCopyToParts - Create a series of nodes that contain the
732 /// specified value split into legal parts.
733 static void getCopyToParts(SelectionDAG &DAG,
737 MVT::ValueType PartVT) {
738 TargetLowering &TLI = DAG.getTargetLoweringInfo();
739 MVT::ValueType PtrVT = TLI.getPointerTy();
740 MVT::ValueType ValueVT = Val.getValueType();
742 if (!MVT::isVector(ValueVT) || NumParts == 1) {
743 // If the value was expanded, copy from the parts.
745 for (unsigned i = 0; i != NumParts; ++i)
746 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val,
747 DAG.getConstant(i, PtrVT));
748 if (!DAG.getTargetLoweringInfo().isLittleEndian())
749 std::reverse(Parts, Parts + NumParts);
753 // If there is a single part and the types differ, this must be
755 if (PartVT != ValueVT) {
756 if (MVT::isVector(PartVT)) {
757 assert(MVT::isVector(ValueVT) &&
758 "Not a vector-vector cast?");
759 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
760 } else if (MVT::isVector(ValueVT)) {
761 assert(NumParts == 1 &&
762 MVT::getVectorElementType(ValueVT) == PartVT &&
763 MVT::getVectorNumElements(ValueVT) == 1 &&
764 "Only trivial vector-to-scalar conversions should get here!");
765 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
766 DAG.getConstant(0, PtrVT));
767 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
768 if (PartVT < ValueVT)
769 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val);
771 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val);
772 } else if (MVT::isFloatingPoint(PartVT) &&
773 MVT::isFloatingPoint(ValueVT)) {
774 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
775 } else if (MVT::getSizeInBits(PartVT) ==
776 MVT::getSizeInBits(ValueVT)) {
777 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
779 assert(0 && "Unknown mismatch!");
786 // Handle a multi-element vector.
787 MVT::ValueType IntermediateVT, RegisterVT;
788 unsigned NumIntermediates;
790 DAG.getTargetLoweringInfo()
791 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
793 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
795 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
796 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
798 // Split the vector into intermediate operands.
799 SmallVector<SDOperand, 8> Ops(NumIntermediates);
800 for (unsigned i = 0; i != NumIntermediates; ++i)
801 if (MVT::isVector(IntermediateVT))
802 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
804 DAG.getConstant(i * (NumElements / NumIntermediates),
807 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
809 DAG.getConstant(i, PtrVT));
811 // Split the intermediate operands into legal parts.
812 if (NumParts == NumIntermediates) {
813 // If the register was not expanded, promote or copy the value,
815 for (unsigned i = 0; i != NumParts; ++i)
816 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
817 } else if (NumParts > 0) {
818 // If the intermediate type was expanded, split each the value into
820 assert(NumParts % NumIntermediates == 0 &&
821 "Must expand into a divisible number of parts!");
822 unsigned Factor = NumParts / NumIntermediates;
823 for (unsigned i = 0; i != NumIntermediates; ++i)
824 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
829 SDOperand SelectionDAGLowering::getValue(const Value *V) {
830 SDOperand &N = NodeMap[V];
833 const Type *VTy = V->getType();
834 MVT::ValueType VT = TLI.getValueType(VTy);
835 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
836 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
837 visit(CE->getOpcode(), *CE);
838 SDOperand N1 = NodeMap[V];
839 assert(N1.Val && "visit didn't populate the ValueMap!");
841 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
842 return N = DAG.getGlobalAddress(GV, VT);
843 } else if (isa<ConstantPointerNull>(C)) {
844 return N = DAG.getConstant(0, TLI.getPointerTy());
845 } else if (isa<UndefValue>(C)) {
846 if (!isa<VectorType>(VTy))
847 return N = DAG.getNode(ISD::UNDEF, VT);
849 // Create a BUILD_VECTOR of undef nodes.
850 const VectorType *PTy = cast<VectorType>(VTy);
851 unsigned NumElements = PTy->getNumElements();
852 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
854 SmallVector<SDOperand, 8> Ops;
855 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
857 // Create a VConstant node with generic Vector type.
858 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
859 return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
860 &Ops[0], Ops.size());
861 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
862 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
863 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
864 unsigned NumElements = PTy->getNumElements();
865 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
867 // Now that we know the number and type of the elements, push a
868 // Constant or ConstantFP node onto the ops list for each element of
869 // the vector constant.
870 SmallVector<SDOperand, 8> Ops;
871 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
872 for (unsigned i = 0; i != NumElements; ++i)
873 Ops.push_back(getValue(CP->getOperand(i)));
875 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
877 if (MVT::isFloatingPoint(PVT))
878 Op = DAG.getConstantFP(0, PVT);
880 Op = DAG.getConstant(0, PVT);
881 Ops.assign(NumElements, Op);
884 // Create a BUILD_VECTOR node.
885 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
886 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
889 // Canonicalize all constant ints to be unsigned.
890 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
894 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
895 std::map<const AllocaInst*, int>::iterator SI =
896 FuncInfo.StaticAllocaMap.find(AI);
897 if (SI != FuncInfo.StaticAllocaMap.end())
898 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
901 unsigned InReg = FuncInfo.ValueMap[V];
902 assert(InReg && "Value not in map!");
904 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
905 unsigned NumRegs = TLI.getNumRegisters(VT);
907 std::vector<unsigned> Regs(NumRegs);
908 for (unsigned i = 0; i != NumRegs; ++i)
911 RegsForValue RFV(Regs, RegisterVT, VT);
912 SDOperand Chain = DAG.getEntryNode();
914 return RFV.getCopyFromRegs(DAG, Chain, NULL);
918 void SelectionDAGLowering::visitRet(ReturnInst &I) {
919 if (I.getNumOperands() == 0) {
920 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
923 SmallVector<SDOperand, 8> NewValues;
924 NewValues.push_back(getRoot());
925 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
926 SDOperand RetOp = getValue(I.getOperand(i));
928 // If this is an integer return value, we need to promote it ourselves to
929 // the full width of a register, since getCopyToParts and Legalize will use
930 // ANY_EXTEND rather than sign/zero.
931 // FIXME: C calling convention requires the return type to be promoted to
932 // at least 32-bit. But this is not necessary for non-C calling conventions.
933 if (MVT::isInteger(RetOp.getValueType()) &&
934 RetOp.getValueType() < MVT::i64) {
935 MVT::ValueType TmpVT;
936 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
937 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
940 const Function *F = I.getParent()->getParent();
941 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
942 if (F->paramHasAttr(0, ParamAttr::SExt))
943 ExtendKind = ISD::SIGN_EXTEND;
944 if (F->paramHasAttr(0, ParamAttr::ZExt))
945 ExtendKind = ISD::ZERO_EXTEND;
946 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
947 NewValues.push_back(RetOp);
948 NewValues.push_back(DAG.getConstant(false, MVT::i32));
950 MVT::ValueType VT = RetOp.getValueType();
951 unsigned NumParts = TLI.getNumRegisters(VT);
952 MVT::ValueType PartVT = TLI.getRegisterType(VT);
953 SmallVector<SDOperand, 4> Parts(NumParts);
954 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT);
955 for (unsigned i = 0; i < NumParts; ++i) {
956 NewValues.push_back(Parts[i]);
957 NewValues.push_back(DAG.getConstant(false, MVT::i32));
961 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
962 &NewValues[0], NewValues.size()));
965 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
966 /// the current basic block, add it to ValueMap now so that we'll get a
968 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
969 // No need to export constants.
970 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
973 if (FuncInfo.isExportedInst(V)) return;
975 unsigned Reg = FuncInfo.InitializeRegForValue(V);
976 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
979 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
980 const BasicBlock *FromBB) {
981 // The operands of the setcc have to be in this block. We don't know
982 // how to export them from some other block.
983 if (Instruction *VI = dyn_cast<Instruction>(V)) {
984 // Can export from current BB.
985 if (VI->getParent() == FromBB)
988 // Is already exported, noop.
989 return FuncInfo.isExportedInst(V);
992 // If this is an argument, we can export it if the BB is the entry block or
993 // if it is already exported.
994 if (isa<Argument>(V)) {
995 if (FromBB == &FromBB->getParent()->getEntryBlock())
998 // Otherwise, can only export this if it is already exported.
999 return FuncInfo.isExportedInst(V);
1002 // Otherwise, constants can always be exported.
1006 static bool InBlock(const Value *V, const BasicBlock *BB) {
1007 if (const Instruction *I = dyn_cast<Instruction>(V))
1008 return I->getParent() == BB;
1012 /// FindMergedConditions - If Cond is an expression like
1013 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1014 MachineBasicBlock *TBB,
1015 MachineBasicBlock *FBB,
1016 MachineBasicBlock *CurBB,
1018 // If this node is not part of the or/and tree, emit it as a branch.
1019 Instruction *BOp = dyn_cast<Instruction>(Cond);
1021 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1022 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1023 BOp->getParent() != CurBB->getBasicBlock() ||
1024 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1025 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1026 const BasicBlock *BB = CurBB->getBasicBlock();
1028 // If the leaf of the tree is a comparison, merge the condition into
1030 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1031 // The operands of the cmp have to be in this block. We don't know
1032 // how to export them from some other block. If this is the first block
1033 // of the sequence, no exporting is needed.
1035 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1036 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1037 BOp = cast<Instruction>(Cond);
1038 ISD::CondCode Condition;
1039 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1040 switch (IC->getPredicate()) {
1041 default: assert(0 && "Unknown icmp predicate opcode!");
1042 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1043 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1044 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1045 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1046 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1047 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1048 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1049 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1050 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1051 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1053 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1054 ISD::CondCode FPC, FOC;
1055 switch (FC->getPredicate()) {
1056 default: assert(0 && "Unknown fcmp predicate opcode!");
1057 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1058 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1059 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1060 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1061 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1062 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1063 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1064 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1065 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1066 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1067 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1068 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1069 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1070 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1071 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1072 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1074 if (FiniteOnlyFPMath())
1079 Condition = ISD::SETEQ; // silence warning.
1080 assert(0 && "Unknown compare instruction");
1083 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1084 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1085 SwitchCases.push_back(CB);
1089 // Create a CaseBlock record representing this branch.
1090 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1091 NULL, TBB, FBB, CurBB);
1092 SwitchCases.push_back(CB);
1097 // Create TmpBB after CurBB.
1098 MachineFunction::iterator BBI = CurBB;
1099 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1100 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1102 if (Opc == Instruction::Or) {
1103 // Codegen X | Y as:
1111 // Emit the LHS condition.
1112 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1114 // Emit the RHS condition into TmpBB.
1115 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1117 assert(Opc == Instruction::And && "Unknown merge op!");
1118 // Codegen X & Y as:
1125 // This requires creation of TmpBB after CurBB.
1127 // Emit the LHS condition.
1128 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1130 // Emit the RHS condition into TmpBB.
1131 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1135 /// If the set of cases should be emitted as a series of branches, return true.
1136 /// If we should emit this as a bunch of and/or'd together conditions, return
1139 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1140 if (Cases.size() != 2) return true;
1142 // If this is two comparisons of the same values or'd or and'd together, they
1143 // will get folded into a single comparison, so don't emit two blocks.
1144 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1145 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1146 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1147 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1154 void SelectionDAGLowering::visitBr(BranchInst &I) {
1155 // Update machine-CFG edges.
1156 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1158 // Figure out which block is immediately after the current one.
1159 MachineBasicBlock *NextBlock = 0;
1160 MachineFunction::iterator BBI = CurMBB;
1161 if (++BBI != CurMBB->getParent()->end())
1164 if (I.isUnconditional()) {
1165 // If this is not a fall-through branch, emit the branch.
1166 if (Succ0MBB != NextBlock)
1167 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1168 DAG.getBasicBlock(Succ0MBB)));
1170 // Update machine-CFG edges.
1171 CurMBB->addSuccessor(Succ0MBB);
1175 // If this condition is one of the special cases we handle, do special stuff
1177 Value *CondVal = I.getCondition();
1178 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1180 // If this is a series of conditions that are or'd or and'd together, emit
1181 // this as a sequence of branches instead of setcc's with and/or operations.
1182 // For example, instead of something like:
1195 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1196 if (BOp->hasOneUse() &&
1197 (BOp->getOpcode() == Instruction::And ||
1198 BOp->getOpcode() == Instruction::Or)) {
1199 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1200 // If the compares in later blocks need to use values not currently
1201 // exported from this block, export them now. This block should always
1202 // be the first entry.
1203 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1205 // Allow some cases to be rejected.
1206 if (ShouldEmitAsBranches(SwitchCases)) {
1207 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1208 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1209 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1212 // Emit the branch for this block.
1213 visitSwitchCase(SwitchCases[0]);
1214 SwitchCases.erase(SwitchCases.begin());
1218 // Okay, we decided not to do this, remove any inserted MBB's and clear
1220 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1221 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1223 SwitchCases.clear();
1227 // Create a CaseBlock record representing this branch.
1228 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1229 NULL, Succ0MBB, Succ1MBB, CurMBB);
1230 // Use visitSwitchCase to actually insert the fast branch sequence for this
1232 visitSwitchCase(CB);
1235 /// visitSwitchCase - Emits the necessary code to represent a single node in
1236 /// the binary search tree resulting from lowering a switch instruction.
1237 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1239 SDOperand CondLHS = getValue(CB.CmpLHS);
1241 // Build the setcc now.
1242 if (CB.CmpMHS == NULL) {
1243 // Fold "(X == true)" to X and "(X == false)" to !X to
1244 // handle common cases produced by branch lowering.
1245 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1247 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1248 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1249 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1251 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1253 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1255 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1256 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1258 SDOperand CmpOp = getValue(CB.CmpMHS);
1259 MVT::ValueType VT = CmpOp.getValueType();
1261 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1262 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1264 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1265 Cond = DAG.getSetCC(MVT::i1, SUB,
1266 DAG.getConstant(High-Low, VT), ISD::SETULE);
1271 // Set NextBlock to be the MBB immediately after the current one, if any.
1272 // This is used to avoid emitting unnecessary branches to the next block.
1273 MachineBasicBlock *NextBlock = 0;
1274 MachineFunction::iterator BBI = CurMBB;
1275 if (++BBI != CurMBB->getParent()->end())
1278 // If the lhs block is the next block, invert the condition so that we can
1279 // fall through to the lhs instead of the rhs block.
1280 if (CB.TrueBB == NextBlock) {
1281 std::swap(CB.TrueBB, CB.FalseBB);
1282 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1283 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1285 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1286 DAG.getBasicBlock(CB.TrueBB));
1287 if (CB.FalseBB == NextBlock)
1288 DAG.setRoot(BrCond);
1290 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1291 DAG.getBasicBlock(CB.FalseBB)));
1292 // Update successor info
1293 CurMBB->addSuccessor(CB.TrueBB);
1294 CurMBB->addSuccessor(CB.FalseBB);
1297 /// visitJumpTable - Emit JumpTable node in the current MBB
1298 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1299 // Emit the code for the jump table
1300 assert(JT.Reg != -1U && "Should lower JT Header first!");
1301 MVT::ValueType PTy = TLI.getPointerTy();
1302 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1303 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1304 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1309 /// visitJumpTableHeader - This function emits necessary code to produce index
1310 /// in the JumpTable from switch case.
1311 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1312 SelectionDAGISel::JumpTableHeader &JTH) {
1313 // Subtract the lowest switch case value from the value being switched on
1314 // and conditional branch to default mbb if the result is greater than the
1315 // difference between smallest and largest cases.
1316 SDOperand SwitchOp = getValue(JTH.SValue);
1317 MVT::ValueType VT = SwitchOp.getValueType();
1318 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1319 DAG.getConstant(JTH.First, VT));
1321 // The SDNode we just created, which holds the value being switched on
1322 // minus the the smallest case value, needs to be copied to a virtual
1323 // register so it can be used as an index into the jump table in a
1324 // subsequent basic block. This value may be smaller or larger than the
1325 // target's pointer type, and therefore require extension or truncating.
1326 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
1327 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1329 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1331 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1332 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1333 JT.Reg = JumpTableReg;
1335 // Emit the range check for the jump table, and branch to the default
1336 // block for the switch statement if the value being switched on exceeds
1337 // the largest case in the switch.
1338 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1339 DAG.getConstant(JTH.Last-JTH.First,VT),
1342 // Set NextBlock to be the MBB immediately after the current one, if any.
1343 // This is used to avoid emitting unnecessary branches to the next block.
1344 MachineBasicBlock *NextBlock = 0;
1345 MachineFunction::iterator BBI = CurMBB;
1346 if (++BBI != CurMBB->getParent()->end())
1349 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1350 DAG.getBasicBlock(JT.Default));
1352 if (JT.MBB == NextBlock)
1353 DAG.setRoot(BrCond);
1355 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1356 DAG.getBasicBlock(JT.MBB)));
1361 /// visitBitTestHeader - This function emits necessary code to produce value
1362 /// suitable for "bit tests"
1363 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1364 // Subtract the minimum value
1365 SDOperand SwitchOp = getValue(B.SValue);
1366 MVT::ValueType VT = SwitchOp.getValueType();
1367 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1368 DAG.getConstant(B.First, VT));
1371 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1372 DAG.getConstant(B.Range, VT),
1376 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
1377 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1379 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1381 // Make desired shift
1382 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1383 DAG.getConstant(1, TLI.getPointerTy()),
1386 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1387 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
1390 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1391 DAG.getBasicBlock(B.Default));
1393 // Set NextBlock to be the MBB immediately after the current one, if any.
1394 // This is used to avoid emitting unnecessary branches to the next block.
1395 MachineBasicBlock *NextBlock = 0;
1396 MachineFunction::iterator BBI = CurMBB;
1397 if (++BBI != CurMBB->getParent()->end())
1400 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1401 if (MBB == NextBlock)
1402 DAG.setRoot(BrRange);
1404 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1405 DAG.getBasicBlock(MBB)));
1407 CurMBB->addSuccessor(B.Default);
1408 CurMBB->addSuccessor(MBB);
1413 /// visitBitTestCase - this function produces one "bit test"
1414 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1416 SelectionDAGISel::BitTestCase &B) {
1417 // Emit bit tests and jumps
1418 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
1420 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1422 DAG.getConstant(B.Mask,
1423 TLI.getPointerTy()));
1424 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
1425 DAG.getConstant(0, TLI.getPointerTy()),
1427 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
1428 AndCmp, DAG.getBasicBlock(B.TargetBB));
1430 // Set NextBlock to be the MBB immediately after the current one, if any.
1431 // This is used to avoid emitting unnecessary branches to the next block.
1432 MachineBasicBlock *NextBlock = 0;
1433 MachineFunction::iterator BBI = CurMBB;
1434 if (++BBI != CurMBB->getParent()->end())
1437 if (NextMBB == NextBlock)
1440 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1441 DAG.getBasicBlock(NextMBB)));
1443 CurMBB->addSuccessor(B.TargetBB);
1444 CurMBB->addSuccessor(NextMBB);
1449 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1450 // Retrieve successors.
1451 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1452 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1454 if (isa<InlineAsm>(I.getCalledValue()))
1457 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1459 // If the value of the invoke is used outside of its defining block, make it
1460 // available as a virtual register.
1461 if (!I.use_empty()) {
1462 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1463 if (VMI != FuncInfo.ValueMap.end())
1464 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second));
1467 // Drop into normal successor.
1468 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1469 DAG.getBasicBlock(Return)));
1471 // Update successor info
1472 CurMBB->addSuccessor(Return);
1473 CurMBB->addSuccessor(LandingPad);
1476 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1479 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1480 /// small case ranges).
1481 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1482 CaseRecVector& WorkList,
1484 MachineBasicBlock* Default) {
1485 Case& BackCase = *(CR.Range.second-1);
1487 // Size is the number of Cases represented by this range.
1488 unsigned Size = CR.Range.second - CR.Range.first;
1492 // Get the MachineFunction which holds the current MBB. This is used when
1493 // inserting any additional MBBs necessary to represent the switch.
1494 MachineFunction *CurMF = CurMBB->getParent();
1496 // Figure out which block is immediately after the current one.
1497 MachineBasicBlock *NextBlock = 0;
1498 MachineFunction::iterator BBI = CR.CaseBB;
1500 if (++BBI != CurMBB->getParent()->end())
1503 // TODO: If any two of the cases has the same destination, and if one value
1504 // is the same as the other, but has one bit unset that the other has set,
1505 // use bit manipulation to do two compares at once. For example:
1506 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1508 // Rearrange the case blocks so that the last one falls through if possible.
1509 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1510 // The last case block won't fall through into 'NextBlock' if we emit the
1511 // branches in this order. See if rearranging a case value would help.
1512 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1513 if (I->BB == NextBlock) {
1514 std::swap(*I, BackCase);
1520 // Create a CaseBlock record representing a conditional branch to
1521 // the Case's target mbb if the value being switched on SV is equal
1523 MachineBasicBlock *CurBlock = CR.CaseBB;
1524 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1525 MachineBasicBlock *FallThrough;
1527 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1528 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1530 // If the last case doesn't match, go to the default block.
1531 FallThrough = Default;
1534 Value *RHS, *LHS, *MHS;
1536 if (I->High == I->Low) {
1537 // This is just small small case range :) containing exactly 1 case
1539 LHS = SV; RHS = I->High; MHS = NULL;
1542 LHS = I->Low; MHS = SV; RHS = I->High;
1544 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1545 I->BB, FallThrough, CurBlock);
1547 // If emitting the first comparison, just call visitSwitchCase to emit the
1548 // code into the current block. Otherwise, push the CaseBlock onto the
1549 // vector to be later processed by SDISel, and insert the node's MBB
1550 // before the next MBB.
1551 if (CurBlock == CurMBB)
1552 visitSwitchCase(CB);
1554 SwitchCases.push_back(CB);
1556 CurBlock = FallThrough;
1562 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1563 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1564 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1567 /// handleJTSwitchCase - Emit jumptable for current switch case range
1568 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1569 CaseRecVector& WorkList,
1571 MachineBasicBlock* Default) {
1572 Case& FrontCase = *CR.Range.first;
1573 Case& BackCase = *(CR.Range.second-1);
1575 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1576 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1579 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1583 if (!areJTsAllowed(TLI) || TSize <= 3)
1586 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1590 DOUT << "Lowering jump table\n"
1591 << "First entry: " << First << ". Last entry: " << Last << "\n"
1592 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1594 // Get the MachineFunction which holds the current MBB. This is used when
1595 // inserting any additional MBBs necessary to represent the switch.
1596 MachineFunction *CurMF = CurMBB->getParent();
1598 // Figure out which block is immediately after the current one.
1599 MachineBasicBlock *NextBlock = 0;
1600 MachineFunction::iterator BBI = CR.CaseBB;
1602 if (++BBI != CurMBB->getParent()->end())
1605 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1607 // Create a new basic block to hold the code for loading the address
1608 // of the jump table, and jumping to it. Update successor information;
1609 // we will either branch to the default case for the switch, or the jump
1611 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1612 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1613 CR.CaseBB->addSuccessor(Default);
1614 CR.CaseBB->addSuccessor(JumpTableBB);
1616 // Build a vector of destination BBs, corresponding to each target
1617 // of the jump table. If the value of the jump table slot corresponds to
1618 // a case statement, push the case's BB onto the vector, otherwise, push
1620 std::vector<MachineBasicBlock*> DestBBs;
1621 int64_t TEI = First;
1622 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1623 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1624 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1626 if ((Low <= TEI) && (TEI <= High)) {
1627 DestBBs.push_back(I->BB);
1631 DestBBs.push_back(Default);
1635 // Update successor info. Add one edge to each unique successor.
1636 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1637 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1638 E = DestBBs.end(); I != E; ++I) {
1639 if (!SuccsHandled[(*I)->getNumber()]) {
1640 SuccsHandled[(*I)->getNumber()] = true;
1641 JumpTableBB->addSuccessor(*I);
1645 // Create a jump table index for this jump table, or return an existing
1647 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1649 // Set the jump table information so that we can codegen it as a second
1650 // MachineBasicBlock
1651 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1652 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1653 (CR.CaseBB == CurMBB));
1654 if (CR.CaseBB == CurMBB)
1655 visitJumpTableHeader(JT, JTH);
1657 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1662 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1664 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1665 CaseRecVector& WorkList,
1667 MachineBasicBlock* Default) {
1668 // Get the MachineFunction which holds the current MBB. This is used when
1669 // inserting any additional MBBs necessary to represent the switch.
1670 MachineFunction *CurMF = CurMBB->getParent();
1672 // Figure out which block is immediately after the current one.
1673 MachineBasicBlock *NextBlock = 0;
1674 MachineFunction::iterator BBI = CR.CaseBB;
1676 if (++BBI != CurMBB->getParent()->end())
1679 Case& FrontCase = *CR.Range.first;
1680 Case& BackCase = *(CR.Range.second-1);
1681 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1683 // Size is the number of Cases represented by this range.
1684 unsigned Size = CR.Range.second - CR.Range.first;
1686 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1687 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1689 CaseItr Pivot = CR.Range.first + Size/2;
1691 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1692 // (heuristically) allow us to emit JumpTable's later.
1694 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1698 uint64_t LSize = FrontCase.size();
1699 uint64_t RSize = TSize-LSize;
1700 DOUT << "Selecting best pivot: \n"
1701 << "First: " << First << ", Last: " << Last <<"\n"
1702 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1703 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1705 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1706 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1707 assert((RBegin-LEnd>=1) && "Invalid case distance");
1708 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1709 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1710 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1711 // Should always split in some non-trivial place
1713 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1714 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1715 << "Metric: " << Metric << "\n";
1716 if (FMetric < Metric) {
1719 DOUT << "Current metric set to: " << FMetric << "\n";
1725 if (areJTsAllowed(TLI)) {
1726 // If our case is dense we *really* should handle it earlier!
1727 assert((FMetric > 0) && "Should handle dense range earlier!");
1729 Pivot = CR.Range.first + Size/2;
1732 CaseRange LHSR(CR.Range.first, Pivot);
1733 CaseRange RHSR(Pivot, CR.Range.second);
1734 Constant *C = Pivot->Low;
1735 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1737 // We know that we branch to the LHS if the Value being switched on is
1738 // less than the Pivot value, C. We use this to optimize our binary
1739 // tree a bit, by recognizing that if SV is greater than or equal to the
1740 // LHS's Case Value, and that Case Value is exactly one less than the
1741 // Pivot's Value, then we can branch directly to the LHS's Target,
1742 // rather than creating a leaf node for it.
1743 if ((LHSR.second - LHSR.first) == 1 &&
1744 LHSR.first->High == CR.GE &&
1745 cast<ConstantInt>(C)->getSExtValue() ==
1746 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1747 TrueBB = LHSR.first->BB;
1749 TrueBB = new MachineBasicBlock(LLVMBB);
1750 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1751 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1754 // Similar to the optimization above, if the Value being switched on is
1755 // known to be less than the Constant CR.LT, and the current Case Value
1756 // is CR.LT - 1, then we can branch directly to the target block for
1757 // the current Case Value, rather than emitting a RHS leaf node for it.
1758 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1759 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1760 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1761 FalseBB = RHSR.first->BB;
1763 FalseBB = new MachineBasicBlock(LLVMBB);
1764 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1765 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1768 // Create a CaseBlock record representing a conditional branch to
1769 // the LHS node if the value being switched on SV is less than C.
1770 // Otherwise, branch to LHS.
1771 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1772 TrueBB, FalseBB, CR.CaseBB);
1774 if (CR.CaseBB == CurMBB)
1775 visitSwitchCase(CB);
1777 SwitchCases.push_back(CB);
1782 /// handleBitTestsSwitchCase - if current case range has few destination and
1783 /// range span less, than machine word bitwidth, encode case range into series
1784 /// of masks and emit bit tests with these masks.
1785 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1786 CaseRecVector& WorkList,
1788 MachineBasicBlock* Default){
1789 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
1791 Case& FrontCase = *CR.Range.first;
1792 Case& BackCase = *(CR.Range.second-1);
1794 // Get the MachineFunction which holds the current MBB. This is used when
1795 // inserting any additional MBBs necessary to represent the switch.
1796 MachineFunction *CurMF = CurMBB->getParent();
1798 unsigned numCmps = 0;
1799 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1801 // Single case counts one, case range - two.
1802 if (I->Low == I->High)
1808 // Count unique destinations
1809 SmallSet<MachineBasicBlock*, 4> Dests;
1810 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1811 Dests.insert(I->BB);
1812 if (Dests.size() > 3)
1813 // Don't bother the code below, if there are too much unique destinations
1816 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1817 << "Total number of comparisons: " << numCmps << "\n";
1819 // Compute span of values.
1820 Constant* minValue = FrontCase.Low;
1821 Constant* maxValue = BackCase.High;
1822 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1823 cast<ConstantInt>(minValue)->getSExtValue();
1824 DOUT << "Compare range: " << range << "\n"
1825 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1826 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1828 if (range>=IntPtrBits ||
1829 (!(Dests.size() == 1 && numCmps >= 3) &&
1830 !(Dests.size() == 2 && numCmps >= 5) &&
1831 !(Dests.size() >= 3 && numCmps >= 6)))
1834 DOUT << "Emitting bit tests\n";
1835 int64_t lowBound = 0;
1837 // Optimize the case where all the case values fit in a
1838 // word without having to subtract minValue. In this case,
1839 // we can optimize away the subtraction.
1840 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1841 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1842 range = cast<ConstantInt>(maxValue)->getSExtValue();
1844 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1847 CaseBitsVector CasesBits;
1848 unsigned i, count = 0;
1850 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1851 MachineBasicBlock* Dest = I->BB;
1852 for (i = 0; i < count; ++i)
1853 if (Dest == CasesBits[i].BB)
1857 assert((count < 3) && "Too much destinations to test!");
1858 CasesBits.push_back(CaseBits(0, Dest, 0));
1862 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1863 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1865 for (uint64_t j = lo; j <= hi; j++) {
1866 CasesBits[i].Mask |= 1ULL << j;
1867 CasesBits[i].Bits++;
1871 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1873 SelectionDAGISel::BitTestInfo BTC;
1875 // Figure out which block is immediately after the current one.
1876 MachineFunction::iterator BBI = CR.CaseBB;
1879 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1882 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1883 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1884 << ", BB: " << CasesBits[i].BB << "\n";
1886 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
1887 CurMF->getBasicBlockList().insert(BBI, CaseBB);
1888 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
1893 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
1894 -1U, (CR.CaseBB == CurMBB),
1895 CR.CaseBB, Default, BTC);
1897 if (CR.CaseBB == CurMBB)
1898 visitBitTestHeader(BTB);
1900 BitTestCases.push_back(BTB);
1906 // Clusterify - Transform simple list of Cases into list of CaseRange's
1907 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
1908 const SwitchInst& SI) {
1909 unsigned numCmps = 0;
1911 // Start with "simple" cases
1912 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
1913 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1914 Cases.push_back(Case(SI.getSuccessorValue(i),
1915 SI.getSuccessorValue(i),
1918 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1920 // Merge case into clusters
1921 if (Cases.size()>=2)
1922 // Must recompute end() each iteration because it may be
1923 // invalidated by erase if we hold on to it
1924 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
1925 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
1926 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
1927 MachineBasicBlock* nextBB = J->BB;
1928 MachineBasicBlock* currentBB = I->BB;
1930 // If the two neighboring cases go to the same destination, merge them
1931 // into a single case.
1932 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
1940 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1941 if (I->Low != I->High)
1942 // A range counts double, since it requires two compares.
1949 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
1950 // Figure out which block is immediately after the current one.
1951 MachineBasicBlock *NextBlock = 0;
1952 MachineFunction::iterator BBI = CurMBB;
1954 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1956 // If there is only the default destination, branch to it if it is not the
1957 // next basic block. Otherwise, just fall through.
1958 if (SI.getNumOperands() == 2) {
1959 // Update machine-CFG edges.
1961 // If this is not a fall-through branch, emit the branch.
1962 if (Default != NextBlock)
1963 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1964 DAG.getBasicBlock(Default)));
1966 CurMBB->addSuccessor(Default);
1970 // If there are any non-default case statements, create a vector of Cases
1971 // representing each one, and sort the vector so that we can efficiently
1972 // create a binary search tree from them.
1974 unsigned numCmps = Clusterify(Cases, SI);
1975 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
1976 << ". Total compares: " << numCmps << "\n";
1978 // Get the Value to be switched on and default basic blocks, which will be
1979 // inserted into CaseBlock records, representing basic blocks in the binary
1981 Value *SV = SI.getOperand(0);
1983 // Push the initial CaseRec onto the worklist
1984 CaseRecVector WorkList;
1985 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1987 while (!WorkList.empty()) {
1988 // Grab a record representing a case range to process off the worklist
1989 CaseRec CR = WorkList.back();
1990 WorkList.pop_back();
1992 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
1995 // If the range has few cases (two or less) emit a series of specific
1997 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2000 // If the switch has more than 5 blocks, and at least 40% dense, and the
2001 // target supports indirect branches, then emit a jump table rather than
2002 // lowering the switch to a binary tree of conditional branches.
2003 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2006 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2007 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2008 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2013 void SelectionDAGLowering::visitSub(User &I) {
2014 // -0.0 - X --> fneg
2015 const Type *Ty = I.getType();
2016 if (isa<VectorType>(Ty)) {
2017 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2018 const VectorType *DestTy = cast<VectorType>(I.getType());
2019 const Type *ElTy = DestTy->getElementType();
2020 if (ElTy->isFloatingPoint()) {
2021 unsigned VL = DestTy->getNumElements();
2022 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2023 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2025 SDOperand Op2 = getValue(I.getOperand(1));
2026 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2032 if (Ty->isFloatingPoint()) {
2033 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2034 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2035 SDOperand Op2 = getValue(I.getOperand(1));
2036 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2041 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2044 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2045 SDOperand Op1 = getValue(I.getOperand(0));
2046 SDOperand Op2 = getValue(I.getOperand(1));
2048 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2051 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2052 SDOperand Op1 = getValue(I.getOperand(0));
2053 SDOperand Op2 = getValue(I.getOperand(1));
2055 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2056 MVT::getSizeInBits(Op2.getValueType()))
2057 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2058 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2059 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2061 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2064 void SelectionDAGLowering::visitICmp(User &I) {
2065 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2066 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2067 predicate = IC->getPredicate();
2068 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2069 predicate = ICmpInst::Predicate(IC->getPredicate());
2070 SDOperand Op1 = getValue(I.getOperand(0));
2071 SDOperand Op2 = getValue(I.getOperand(1));
2072 ISD::CondCode Opcode;
2073 switch (predicate) {
2074 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2075 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2076 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2077 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2078 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2079 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2080 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2081 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2082 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2083 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2085 assert(!"Invalid ICmp predicate value");
2086 Opcode = ISD::SETEQ;
2089 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2092 void SelectionDAGLowering::visitFCmp(User &I) {
2093 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2094 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2095 predicate = FC->getPredicate();
2096 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2097 predicate = FCmpInst::Predicate(FC->getPredicate());
2098 SDOperand Op1 = getValue(I.getOperand(0));
2099 SDOperand Op2 = getValue(I.getOperand(1));
2100 ISD::CondCode Condition, FOC, FPC;
2101 switch (predicate) {
2102 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2103 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2104 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2105 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2106 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2107 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2108 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2109 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2110 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2111 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2112 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2113 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2114 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2115 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2116 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2117 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2119 assert(!"Invalid FCmp predicate value");
2120 FOC = FPC = ISD::SETFALSE;
2123 if (FiniteOnlyFPMath())
2127 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2130 void SelectionDAGLowering::visitSelect(User &I) {
2131 SDOperand Cond = getValue(I.getOperand(0));
2132 SDOperand TrueVal = getValue(I.getOperand(1));
2133 SDOperand FalseVal = getValue(I.getOperand(2));
2134 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2135 TrueVal, FalseVal));
2139 void SelectionDAGLowering::visitTrunc(User &I) {
2140 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2141 SDOperand N = getValue(I.getOperand(0));
2142 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2143 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2146 void SelectionDAGLowering::visitZExt(User &I) {
2147 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2148 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2149 SDOperand N = getValue(I.getOperand(0));
2150 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2151 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2154 void SelectionDAGLowering::visitSExt(User &I) {
2155 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2156 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2157 SDOperand N = getValue(I.getOperand(0));
2158 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2159 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2162 void SelectionDAGLowering::visitFPTrunc(User &I) {
2163 // FPTrunc is never a no-op cast, no need to check
2164 SDOperand N = getValue(I.getOperand(0));
2165 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2166 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
2169 void SelectionDAGLowering::visitFPExt(User &I){
2170 // FPTrunc is never a no-op cast, no need to check
2171 SDOperand N = getValue(I.getOperand(0));
2172 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2173 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2176 void SelectionDAGLowering::visitFPToUI(User &I) {
2177 // FPToUI is never a no-op cast, no need to check
2178 SDOperand N = getValue(I.getOperand(0));
2179 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2180 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2183 void SelectionDAGLowering::visitFPToSI(User &I) {
2184 // FPToSI is never a no-op cast, no need to check
2185 SDOperand N = getValue(I.getOperand(0));
2186 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2187 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2190 void SelectionDAGLowering::visitUIToFP(User &I) {
2191 // UIToFP is never a no-op cast, no need to check
2192 SDOperand N = getValue(I.getOperand(0));
2193 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2194 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2197 void SelectionDAGLowering::visitSIToFP(User &I){
2198 // UIToFP is never a no-op cast, no need to check
2199 SDOperand N = getValue(I.getOperand(0));
2200 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2201 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2204 void SelectionDAGLowering::visitPtrToInt(User &I) {
2205 // What to do depends on the size of the integer and the size of the pointer.
2206 // We can either truncate, zero extend, or no-op, accordingly.
2207 SDOperand N = getValue(I.getOperand(0));
2208 MVT::ValueType SrcVT = N.getValueType();
2209 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2211 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2212 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2214 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2215 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2216 setValue(&I, Result);
2219 void SelectionDAGLowering::visitIntToPtr(User &I) {
2220 // What to do depends on the size of the integer and the size of the pointer.
2221 // We can either truncate, zero extend, or no-op, accordingly.
2222 SDOperand N = getValue(I.getOperand(0));
2223 MVT::ValueType SrcVT = N.getValueType();
2224 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2225 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2226 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2228 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2229 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2232 void SelectionDAGLowering::visitBitCast(User &I) {
2233 SDOperand N = getValue(I.getOperand(0));
2234 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2236 // BitCast assures us that source and destination are the same size so this
2237 // is either a BIT_CONVERT or a no-op.
2238 if (DestVT != N.getValueType())
2239 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2241 setValue(&I, N); // noop cast.
2244 void SelectionDAGLowering::visitInsertElement(User &I) {
2245 SDOperand InVec = getValue(I.getOperand(0));
2246 SDOperand InVal = getValue(I.getOperand(1));
2247 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2248 getValue(I.getOperand(2)));
2250 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2251 TLI.getValueType(I.getType()),
2252 InVec, InVal, InIdx));
2255 void SelectionDAGLowering::visitExtractElement(User &I) {
2256 SDOperand InVec = getValue(I.getOperand(0));
2257 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2258 getValue(I.getOperand(1)));
2259 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2260 TLI.getValueType(I.getType()), InVec, InIdx));
2263 void SelectionDAGLowering::visitShuffleVector(User &I) {
2264 SDOperand V1 = getValue(I.getOperand(0));
2265 SDOperand V2 = getValue(I.getOperand(1));
2266 SDOperand Mask = getValue(I.getOperand(2));
2268 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2269 TLI.getValueType(I.getType()),
2274 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2275 SDOperand N = getValue(I.getOperand(0));
2276 const Type *Ty = I.getOperand(0)->getType();
2278 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2281 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2282 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2285 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2286 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2287 getIntPtrConstant(Offset));
2289 Ty = StTy->getElementType(Field);
2291 Ty = cast<SequentialType>(Ty)->getElementType();
2293 // If this is a constant subscript, handle it quickly.
2294 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2295 if (CI->getZExtValue() == 0) continue;
2297 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2298 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
2302 // N = N + Idx * ElementSize;
2303 uint64_t ElementSize = TD->getABITypeSize(Ty);
2304 SDOperand IdxN = getValue(Idx);
2306 // If the index is smaller or larger than intptr_t, truncate or extend
2308 if (IdxN.getValueType() < N.getValueType()) {
2309 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2310 } else if (IdxN.getValueType() > N.getValueType())
2311 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2313 // If this is a multiply by a power of two, turn it into a shl
2314 // immediately. This is a very common case.
2315 if (isPowerOf2_64(ElementSize)) {
2316 unsigned Amt = Log2_64(ElementSize);
2317 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2318 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2319 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2323 SDOperand Scale = getIntPtrConstant(ElementSize);
2324 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2325 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2331 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2332 // If this is a fixed sized alloca in the entry block of the function,
2333 // allocate it statically on the stack.
2334 if (FuncInfo.StaticAllocaMap.count(&I))
2335 return; // getValue will auto-populate this.
2337 const Type *Ty = I.getAllocatedType();
2338 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2340 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2343 SDOperand AllocSize = getValue(I.getArraySize());
2344 MVT::ValueType IntPtr = TLI.getPointerTy();
2345 if (IntPtr < AllocSize.getValueType())
2346 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2347 else if (IntPtr > AllocSize.getValueType())
2348 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2350 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2351 getIntPtrConstant(TySize));
2353 // Handle alignment. If the requested alignment is less than or equal to
2354 // the stack alignment, ignore it. If the size is greater than or equal to
2355 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2356 unsigned StackAlign =
2357 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2358 if (Align <= StackAlign)
2361 // Round the size of the allocation up to the stack alignment size
2362 // by add SA-1 to the size.
2363 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2364 getIntPtrConstant(StackAlign-1));
2365 // Mask out the low bits for alignment purposes.
2366 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2367 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2369 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
2370 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2372 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2374 DAG.setRoot(DSA.getValue(1));
2376 // Inform the Frame Information that we have just allocated a variable-sized
2378 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2381 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2382 SDOperand Ptr = getValue(I.getOperand(0));
2388 // Do not serialize non-volatile loads against each other.
2389 Root = DAG.getRoot();
2392 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2393 Root, I.isVolatile(), I.getAlignment()));
2396 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2397 const Value *SV, SDOperand Root,
2399 unsigned Alignment) {
2401 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2402 isVolatile, Alignment);
2405 DAG.setRoot(L.getValue(1));
2407 PendingLoads.push_back(L.getValue(1));
2413 void SelectionDAGLowering::visitStore(StoreInst &I) {
2414 Value *SrcV = I.getOperand(0);
2415 SDOperand Src = getValue(SrcV);
2416 SDOperand Ptr = getValue(I.getOperand(1));
2417 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2418 I.isVolatile(), I.getAlignment()));
2421 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2423 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2424 unsigned Intrinsic) {
2425 bool HasChain = !I.doesNotAccessMemory();
2426 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2428 // Build the operand list.
2429 SmallVector<SDOperand, 8> Ops;
2430 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2432 // We don't need to serialize loads against other loads.
2433 Ops.push_back(DAG.getRoot());
2435 Ops.push_back(getRoot());
2439 // Add the intrinsic ID as an integer operand.
2440 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2442 // Add all operands of the call to the operand list.
2443 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2444 SDOperand Op = getValue(I.getOperand(i));
2445 assert(TLI.isTypeLegal(Op.getValueType()) &&
2446 "Intrinsic uses a non-legal type?");
2450 std::vector<MVT::ValueType> VTs;
2451 if (I.getType() != Type::VoidTy) {
2452 MVT::ValueType VT = TLI.getValueType(I.getType());
2453 if (MVT::isVector(VT)) {
2454 const VectorType *DestTy = cast<VectorType>(I.getType());
2455 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2457 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2458 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2461 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2465 VTs.push_back(MVT::Other);
2467 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2472 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2473 &Ops[0], Ops.size());
2474 else if (I.getType() != Type::VoidTy)
2475 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2476 &Ops[0], Ops.size());
2478 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2479 &Ops[0], Ops.size());
2482 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2484 PendingLoads.push_back(Chain);
2488 if (I.getType() != Type::VoidTy) {
2489 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2490 MVT::ValueType VT = TLI.getValueType(PTy);
2491 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2493 setValue(&I, Result);
2497 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2498 static GlobalVariable *ExtractTypeInfo (Value *V) {
2499 V = IntrinsicInst::StripPointerCasts(V);
2500 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2501 assert (GV || isa<ConstantPointerNull>(V) &&
2502 "TypeInfo must be a global variable or NULL");
2506 /// addCatchInfo - Extract the personality and type infos from an eh.selector
2507 /// call, and add them to the specified machine basic block.
2508 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2509 MachineBasicBlock *MBB) {
2510 // Inform the MachineModuleInfo of the personality for this landing pad.
2511 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2512 assert(CE->getOpcode() == Instruction::BitCast &&
2513 isa<Function>(CE->getOperand(0)) &&
2514 "Personality should be a function");
2515 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2517 // Gather all the type infos for this landing pad and pass them along to
2518 // MachineModuleInfo.
2519 std::vector<GlobalVariable *> TyInfo;
2520 unsigned N = I.getNumOperands();
2522 for (unsigned i = N - 1; i > 2; --i) {
2523 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2524 unsigned FilterLength = CI->getZExtValue();
2525 unsigned FirstCatch = i + FilterLength + !FilterLength;
2526 assert (FirstCatch <= N && "Invalid filter length");
2528 if (FirstCatch < N) {
2529 TyInfo.reserve(N - FirstCatch);
2530 for (unsigned j = FirstCatch; j < N; ++j)
2531 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2532 MMI->addCatchTypeInfo(MBB, TyInfo);
2536 if (!FilterLength) {
2538 MMI->addCleanup(MBB);
2541 TyInfo.reserve(FilterLength - 1);
2542 for (unsigned j = i + 1; j < FirstCatch; ++j)
2543 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2544 MMI->addFilterTypeInfo(MBB, TyInfo);
2553 TyInfo.reserve(N - 3);
2554 for (unsigned j = 3; j < N; ++j)
2555 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2556 MMI->addCatchTypeInfo(MBB, TyInfo);
2560 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2561 /// we want to emit this as a call to a named external function, return the name
2562 /// otherwise lower it and return null.
2564 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2565 switch (Intrinsic) {
2567 // By default, turn this into a target intrinsic node.
2568 visitTargetIntrinsic(I, Intrinsic);
2570 case Intrinsic::vastart: visitVAStart(I); return 0;
2571 case Intrinsic::vaend: visitVAEnd(I); return 0;
2572 case Intrinsic::vacopy: visitVACopy(I); return 0;
2573 case Intrinsic::returnaddress:
2574 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2575 getValue(I.getOperand(1))));
2577 case Intrinsic::frameaddress:
2578 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2579 getValue(I.getOperand(1))));
2581 case Intrinsic::setjmp:
2582 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2584 case Intrinsic::longjmp:
2585 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2587 case Intrinsic::memcpy_i32:
2588 case Intrinsic::memcpy_i64:
2589 visitMemIntrinsic(I, ISD::MEMCPY);
2591 case Intrinsic::memset_i32:
2592 case Intrinsic::memset_i64:
2593 visitMemIntrinsic(I, ISD::MEMSET);
2595 case Intrinsic::memmove_i32:
2596 case Intrinsic::memmove_i64:
2597 visitMemIntrinsic(I, ISD::MEMMOVE);
2600 case Intrinsic::dbg_stoppoint: {
2601 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2602 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2603 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2607 Ops[1] = getValue(SPI.getLineValue());
2608 Ops[2] = getValue(SPI.getColumnValue());
2610 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2611 assert(DD && "Not a debug information descriptor");
2612 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2614 Ops[3] = DAG.getString(CompileUnit->getFileName());
2615 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2617 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2622 case Intrinsic::dbg_region_start: {
2623 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2624 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2625 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2626 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2627 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2628 DAG.getConstant(LabelID, MVT::i32)));
2633 case Intrinsic::dbg_region_end: {
2634 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2635 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2636 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2637 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2638 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2639 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2644 case Intrinsic::dbg_func_start: {
2645 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2646 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2647 if (MMI && FSI.getSubprogram() &&
2648 MMI->Verify(FSI.getSubprogram())) {
2649 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram());
2650 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2651 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2656 case Intrinsic::dbg_declare: {
2657 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2658 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2659 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) {
2660 SDOperand AddressOp = getValue(DI.getAddress());
2661 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
2662 MMI->RecordVariable(DI.getVariable(), FI->getIndex());
2668 case Intrinsic::eh_exception: {
2669 if (ExceptionHandling) {
2670 if (!CurMBB->isLandingPad()) {
2671 // FIXME: Mark exception register as live in. Hack for PR1508.
2672 unsigned Reg = TLI.getExceptionAddressRegister();
2673 if (Reg) CurMBB->addLiveIn(Reg);
2675 // Insert the EXCEPTIONADDR instruction.
2676 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2678 Ops[0] = DAG.getRoot();
2679 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2681 DAG.setRoot(Op.getValue(1));
2683 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2688 case Intrinsic::eh_selector_i32:
2689 case Intrinsic::eh_selector_i64: {
2690 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2691 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
2692 MVT::i32 : MVT::i64);
2694 if (ExceptionHandling && MMI) {
2695 if (CurMBB->isLandingPad())
2696 addCatchInfo(I, MMI, CurMBB);
2699 FuncInfo.CatchInfoLost.insert(&I);
2701 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2702 unsigned Reg = TLI.getExceptionSelectorRegister();
2703 if (Reg) CurMBB->addLiveIn(Reg);
2706 // Insert the EHSELECTION instruction.
2707 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
2709 Ops[0] = getValue(I.getOperand(1));
2711 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2713 DAG.setRoot(Op.getValue(1));
2715 setValue(&I, DAG.getConstant(0, VT));
2721 case Intrinsic::eh_typeid_for_i32:
2722 case Intrinsic::eh_typeid_for_i64: {
2723 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2724 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
2725 MVT::i32 : MVT::i64);
2728 // Find the type id for the given typeinfo.
2729 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
2731 unsigned TypeID = MMI->getTypeIDFor(GV);
2732 setValue(&I, DAG.getConstant(TypeID, VT));
2734 // Return something different to eh_selector.
2735 setValue(&I, DAG.getConstant(1, VT));
2741 case Intrinsic::eh_return: {
2742 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2744 if (MMI && ExceptionHandling) {
2745 MMI->setCallsEHReturn(true);
2746 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2749 getValue(I.getOperand(1)),
2750 getValue(I.getOperand(2))));
2752 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2758 case Intrinsic::eh_unwind_init: {
2759 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2760 MMI->setCallsUnwindInit(true);
2766 case Intrinsic::eh_dwarf_cfa: {
2767 if (ExceptionHandling) {
2768 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
2770 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
2771 CfaArg = DAG.getNode(ISD::TRUNCATE,
2772 TLI.getPointerTy(), getValue(I.getOperand(1)));
2774 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
2775 TLI.getPointerTy(), getValue(I.getOperand(1)));
2777 SDOperand Offset = DAG.getNode(ISD::ADD,
2779 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
2780 TLI.getPointerTy()),
2782 setValue(&I, DAG.getNode(ISD::ADD,
2784 DAG.getNode(ISD::FRAMEADDR,
2787 TLI.getPointerTy())),
2790 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2796 case Intrinsic::sqrt:
2797 setValue(&I, DAG.getNode(ISD::FSQRT,
2798 getValue(I.getOperand(1)).getValueType(),
2799 getValue(I.getOperand(1))));
2801 case Intrinsic::powi:
2802 setValue(&I, DAG.getNode(ISD::FPOWI,
2803 getValue(I.getOperand(1)).getValueType(),
2804 getValue(I.getOperand(1)),
2805 getValue(I.getOperand(2))));
2807 case Intrinsic::sin:
2808 setValue(&I, DAG.getNode(ISD::FSIN,
2809 getValue(I.getOperand(1)).getValueType(),
2810 getValue(I.getOperand(1))));
2812 case Intrinsic::cos:
2813 setValue(&I, DAG.getNode(ISD::FCOS,
2814 getValue(I.getOperand(1)).getValueType(),
2815 getValue(I.getOperand(1))));
2817 case Intrinsic::pow:
2818 setValue(&I, DAG.getNode(ISD::FPOW,
2819 getValue(I.getOperand(1)).getValueType(),
2820 getValue(I.getOperand(1)),
2821 getValue(I.getOperand(2))));
2823 case Intrinsic::pcmarker: {
2824 SDOperand Tmp = getValue(I.getOperand(1));
2825 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2828 case Intrinsic::readcyclecounter: {
2829 SDOperand Op = getRoot();
2830 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2831 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2834 DAG.setRoot(Tmp.getValue(1));
2837 case Intrinsic::part_select: {
2838 // Currently not implemented: just abort
2839 assert(0 && "part_select intrinsic not implemented");
2842 case Intrinsic::part_set: {
2843 // Currently not implemented: just abort
2844 assert(0 && "part_set intrinsic not implemented");
2847 case Intrinsic::bswap:
2848 setValue(&I, DAG.getNode(ISD::BSWAP,
2849 getValue(I.getOperand(1)).getValueType(),
2850 getValue(I.getOperand(1))));
2852 case Intrinsic::cttz: {
2853 SDOperand Arg = getValue(I.getOperand(1));
2854 MVT::ValueType Ty = Arg.getValueType();
2855 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
2856 setValue(&I, result);
2859 case Intrinsic::ctlz: {
2860 SDOperand Arg = getValue(I.getOperand(1));
2861 MVT::ValueType Ty = Arg.getValueType();
2862 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
2863 setValue(&I, result);
2866 case Intrinsic::ctpop: {
2867 SDOperand Arg = getValue(I.getOperand(1));
2868 MVT::ValueType Ty = Arg.getValueType();
2869 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
2870 setValue(&I, result);
2873 case Intrinsic::stacksave: {
2874 SDOperand Op = getRoot();
2875 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2876 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2878 DAG.setRoot(Tmp.getValue(1));
2881 case Intrinsic::stackrestore: {
2882 SDOperand Tmp = getValue(I.getOperand(1));
2883 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
2886 case Intrinsic::prefetch:
2887 // FIXME: Currently discarding prefetches.
2890 case Intrinsic::var_annotation:
2891 // Discard annotate attributes
2894 case Intrinsic::init_trampoline: {
2896 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2)));
2900 Ops[1] = getValue(I.getOperand(1));
2901 Ops[2] = getValue(I.getOperand(2));
2902 Ops[3] = getValue(I.getOperand(3));
2903 Ops[4] = DAG.getSrcValue(I.getOperand(1));
2904 Ops[5] = DAG.getSrcValue(F);
2906 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
2907 DAG.getNodeValueTypes(TLI.getPointerTy(),
2912 DAG.setRoot(Tmp.getValue(1));
2916 case Intrinsic::gcroot:
2918 Value *Alloca = I.getOperand(1);
2919 Constant *TypeMap = cast<Constant>(I.getOperand(2));
2921 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
2922 GCI->addStackRoot(FI->getIndex(), TypeMap);
2926 case Intrinsic::gcread:
2927 case Intrinsic::gcwrite:
2928 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
2931 case Intrinsic::flt_rounds: {
2932 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS, MVT::i32));
2936 case Intrinsic::trap: {
2937 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
2944 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
2946 MachineBasicBlock *LandingPad) {
2947 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2948 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2949 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2950 unsigned BeginLabel = 0, EndLabel = 0;
2952 TargetLowering::ArgListTy Args;
2953 TargetLowering::ArgListEntry Entry;
2954 Args.reserve(CS.arg_size());
2955 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2957 SDOperand ArgNode = getValue(*i);
2958 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
2960 unsigned attrInd = i - CS.arg_begin() + 1;
2961 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
2962 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
2963 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
2964 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
2965 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
2966 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
2967 Args.push_back(Entry);
2970 bool MarkTryRange = LandingPad ||
2971 // C++ requires special handling of 'nounwind' calls.
2972 (CS.doesNotThrow());
2974 if (MarkTryRange && ExceptionHandling && MMI) {
2975 // Insert a label before the invoke call to mark the try range. This can be
2976 // used to detect deletion of the invoke via the MachineModuleInfo.
2977 BeginLabel = MMI->NextLabelID();
2978 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2979 DAG.getConstant(BeginLabel, MVT::i32)));
2982 std::pair<SDOperand,SDOperand> Result =
2983 TLI.LowerCallTo(getRoot(), CS.getType(),
2984 CS.paramHasAttr(0, ParamAttr::SExt),
2985 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
2987 if (CS.getType() != Type::VoidTy)
2988 setValue(CS.getInstruction(), Result.first);
2989 DAG.setRoot(Result.second);
2991 if (MarkTryRange && ExceptionHandling && MMI) {
2992 // Insert a label at the end of the invoke call to mark the try range. This
2993 // can be used to detect deletion of the invoke via the MachineModuleInfo.
2994 EndLabel = MMI->NextLabelID();
2995 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2996 DAG.getConstant(EndLabel, MVT::i32)));
2998 // Inform MachineModuleInfo of range.
2999 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3004 void SelectionDAGLowering::visitCall(CallInst &I) {
3005 const char *RenameFn = 0;
3006 if (Function *F = I.getCalledFunction()) {
3007 if (F->isDeclaration()) {
3008 if (unsigned IID = F->getIntrinsicID()) {
3009 RenameFn = visitIntrinsicCall(I, IID);
3015 // Check for well-known libc/libm calls. If the function is internal, it
3016 // can't be a library call.
3017 unsigned NameLen = F->getNameLen();
3018 if (!F->hasInternalLinkage() && NameLen) {
3019 const char *NameStr = F->getNameStart();
3020 if (NameStr[0] == 'c' &&
3021 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3022 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3023 if (I.getNumOperands() == 3 && // Basic sanity checks.
3024 I.getOperand(1)->getType()->isFloatingPoint() &&
3025 I.getType() == I.getOperand(1)->getType() &&
3026 I.getType() == I.getOperand(2)->getType()) {
3027 SDOperand LHS = getValue(I.getOperand(1));
3028 SDOperand RHS = getValue(I.getOperand(2));
3029 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3033 } else if (NameStr[0] == 'f' &&
3034 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3035 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3036 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3037 if (I.getNumOperands() == 2 && // Basic sanity checks.
3038 I.getOperand(1)->getType()->isFloatingPoint() &&
3039 I.getType() == I.getOperand(1)->getType()) {
3040 SDOperand Tmp = getValue(I.getOperand(1));
3041 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3044 } else if (NameStr[0] == 's' &&
3045 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3046 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3047 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3048 if (I.getNumOperands() == 2 && // Basic sanity checks.
3049 I.getOperand(1)->getType()->isFloatingPoint() &&
3050 I.getType() == I.getOperand(1)->getType()) {
3051 SDOperand Tmp = getValue(I.getOperand(1));
3052 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3055 } else if (NameStr[0] == 'c' &&
3056 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3057 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3058 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3059 if (I.getNumOperands() == 2 && // Basic sanity checks.
3060 I.getOperand(1)->getType()->isFloatingPoint() &&
3061 I.getType() == I.getOperand(1)->getType()) {
3062 SDOperand Tmp = getValue(I.getOperand(1));
3063 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3068 } else if (isa<InlineAsm>(I.getOperand(0))) {
3075 Callee = getValue(I.getOperand(0));
3077 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3079 LowerCallTo(&I, Callee, I.isTailCall());
3083 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3084 /// this value and returns the result as a ValueVT value. This uses
3085 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3086 /// If the Flag pointer is NULL, no flag is used.
3087 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3088 SDOperand &Chain, SDOperand *Flag)const{
3089 // Copy the legal parts from the registers.
3090 unsigned NumParts = Regs.size();
3091 SmallVector<SDOperand, 8> Parts(NumParts);
3092 for (unsigned i = 0; i != NumParts; ++i) {
3093 SDOperand Part = Flag ?
3094 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3095 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3096 Chain = Part.getValue(1);
3098 *Flag = Part.getValue(2);
3102 // Assemble the legal parts into the final value.
3103 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
3106 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3107 /// specified value into the registers specified by this object. This uses
3108 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3109 /// If the Flag pointer is NULL, no flag is used.
3110 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3111 SDOperand &Chain, SDOperand *Flag) const {
3112 // Get the list of the values's legal parts.
3113 unsigned NumParts = Regs.size();
3114 SmallVector<SDOperand, 8> Parts(NumParts);
3115 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
3117 // Copy the parts into the registers.
3118 for (unsigned i = 0; i != NumParts; ++i) {
3119 SDOperand Part = Flag ?
3120 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
3121 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3122 Chain = Part.getValue(0);
3124 *Flag = Part.getValue(1);
3128 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3129 /// operand list. This adds the code marker and includes the number of
3130 /// values added into it.
3131 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3132 std::vector<SDOperand> &Ops) const {
3133 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3134 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3135 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3136 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3139 /// isAllocatableRegister - If the specified register is safe to allocate,
3140 /// i.e. it isn't a stack pointer or some other special register, return the
3141 /// register class for the register. Otherwise, return null.
3142 static const TargetRegisterClass *
3143 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3144 const TargetLowering &TLI, const MRegisterInfo *MRI) {
3145 MVT::ValueType FoundVT = MVT::Other;
3146 const TargetRegisterClass *FoundRC = 0;
3147 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
3148 E = MRI->regclass_end(); RCI != E; ++RCI) {
3149 MVT::ValueType ThisVT = MVT::Other;
3151 const TargetRegisterClass *RC = *RCI;
3152 // If none of the the value types for this register class are valid, we
3153 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3154 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3156 if (TLI.isTypeLegal(*I)) {
3157 // If we have already found this register in a different register class,
3158 // choose the one with the largest VT specified. For example, on
3159 // PowerPC, we favor f64 register classes over f32.
3160 if (FoundVT == MVT::Other ||
3161 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3168 if (ThisVT == MVT::Other) continue;
3170 // NOTE: This isn't ideal. In particular, this might allocate the
3171 // frame pointer in functions that need it (due to them not being taken
3172 // out of allocation, because a variable sized allocation hasn't been seen
3173 // yet). This is a slight code pessimization, but should still work.
3174 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3175 E = RC->allocation_order_end(MF); I != E; ++I)
3177 // We found a matching register class. Keep looking at others in case
3178 // we find one with larger registers that this physreg is also in.
3189 /// AsmOperandInfo - This contains information for each constraint that we are
3191 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3192 /// ConstraintCode - This contains the actual string for the code, like "m".
3193 std::string ConstraintCode;
3195 /// ConstraintType - Information about the constraint code, e.g. Register,
3196 /// RegisterClass, Memory, Other, Unknown.
3197 TargetLowering::ConstraintType ConstraintType;
3199 /// CallOperand/CallOperandval - If this is the result output operand or a
3200 /// clobber, this is null, otherwise it is the incoming operand to the
3201 /// CallInst. This gets modified as the asm is processed.
3202 SDOperand CallOperand;
3203 Value *CallOperandVal;
3205 /// ConstraintVT - The ValueType for the operand value.
3206 MVT::ValueType ConstraintVT;
3208 /// AssignedRegs - If this is a register or register class operand, this
3209 /// contains the set of register corresponding to the operand.
3210 RegsForValue AssignedRegs;
3212 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3213 : InlineAsm::ConstraintInfo(info),
3214 ConstraintType(TargetLowering::C_Unknown),
3215 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
3218 void ComputeConstraintToUse(const TargetLowering &TLI);
3220 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3221 /// busy in OutputRegs/InputRegs.
3222 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3223 std::set<unsigned> &OutputRegs,
3224 std::set<unsigned> &InputRegs) const {
3226 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3228 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3231 } // end anon namespace.
3233 /// getConstraintGenerality - Return an integer indicating how general CT is.
3234 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3236 default: assert(0 && "Unknown constraint type!");
3237 case TargetLowering::C_Other:
3238 case TargetLowering::C_Unknown:
3240 case TargetLowering::C_Register:
3242 case TargetLowering::C_RegisterClass:
3244 case TargetLowering::C_Memory:
3249 void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) {
3250 assert(!Codes.empty() && "Must have at least one constraint");
3252 std::string *Current = &Codes[0];
3253 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
3254 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common.
3255 ConstraintCode = *Current;
3256 ConstraintType = CurType;
3260 unsigned CurGenerality = getConstraintGenerality(CurType);
3262 // If we have multiple constraints, try to pick the most general one ahead
3263 // of time. This isn't a wonderful solution, but handles common cases.
3264 for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
3265 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
3266 unsigned ThisGenerality = getConstraintGenerality(ThisType);
3267 if (ThisGenerality > CurGenerality) {
3268 // This constraint letter is more general than the previous one,
3271 Current = &Codes[j];
3272 CurGenerality = ThisGenerality;
3276 ConstraintCode = *Current;
3277 ConstraintType = CurType;
3281 void SelectionDAGLowering::
3282 GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
3283 std::set<unsigned> &OutputRegs,
3284 std::set<unsigned> &InputRegs) {
3285 // Compute whether this value requires an input register, an output register,
3287 bool isOutReg = false;
3288 bool isInReg = false;
3289 switch (OpInfo.Type) {
3290 case InlineAsm::isOutput:
3293 // If this is an early-clobber output, or if there is an input
3294 // constraint that matches this, we need to reserve the input register
3295 // so no other inputs allocate to it.
3296 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3298 case InlineAsm::isInput:
3302 case InlineAsm::isClobber:
3309 MachineFunction &MF = DAG.getMachineFunction();
3310 std::vector<unsigned> Regs;
3312 // If this is a constraint for a single physreg, or a constraint for a
3313 // register class, find it.
3314 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3315 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3316 OpInfo.ConstraintVT);
3318 unsigned NumRegs = 1;
3319 if (OpInfo.ConstraintVT != MVT::Other)
3320 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3321 MVT::ValueType RegVT;
3322 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3325 // If this is a constraint for a specific physical register, like {r17},
3327 if (PhysReg.first) {
3328 if (OpInfo.ConstraintVT == MVT::Other)
3329 ValueVT = *PhysReg.second->vt_begin();
3331 // Get the actual register value type. This is important, because the user
3332 // may have asked for (e.g.) the AX register in i32 type. We need to
3333 // remember that AX is actually i16 to get the right extension.
3334 RegVT = *PhysReg.second->vt_begin();
3336 // This is a explicit reference to a physical register.
3337 Regs.push_back(PhysReg.first);
3339 // If this is an expanded reference, add the rest of the regs to Regs.
3341 TargetRegisterClass::iterator I = PhysReg.second->begin();
3342 TargetRegisterClass::iterator E = PhysReg.second->end();
3343 for (; *I != PhysReg.first; ++I)
3344 assert(I != E && "Didn't find reg!");
3346 // Already added the first reg.
3348 for (; NumRegs; --NumRegs, ++I) {
3349 assert(I != E && "Ran out of registers to allocate!");
3353 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3354 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3358 // Otherwise, if this was a reference to an LLVM register class, create vregs
3359 // for this reference.
3360 std::vector<unsigned> RegClassRegs;
3361 const TargetRegisterClass *RC = PhysReg.second;
3363 // If this is an early clobber or tied register, our regalloc doesn't know
3364 // how to maintain the constraint. If it isn't, go ahead and create vreg
3365 // and let the regalloc do the right thing.
3366 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3367 // If there is some other early clobber and this is an input register,
3368 // then we are forced to pre-allocate the input reg so it doesn't
3369 // conflict with the earlyclobber.
3370 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
3371 RegVT = *PhysReg.second->vt_begin();
3373 if (OpInfo.ConstraintVT == MVT::Other)
3376 // Create the appropriate number of virtual registers.
3377 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3378 for (; NumRegs; --NumRegs)
3379 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
3381 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3382 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3386 // Otherwise, we can't allocate it. Let the code below figure out how to
3387 // maintain these constraints.
3388 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3391 // This is a reference to a register class that doesn't directly correspond
3392 // to an LLVM register class. Allocate NumRegs consecutive, available,
3393 // registers from the class.
3394 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3395 OpInfo.ConstraintVT);
3398 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
3399 unsigned NumAllocated = 0;
3400 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3401 unsigned Reg = RegClassRegs[i];
3402 // See if this register is available.
3403 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3404 (isInReg && InputRegs.count(Reg))) { // Already used.
3405 // Make sure we find consecutive registers.
3410 // Check to see if this register is allocatable (i.e. don't give out the
3413 RC = isAllocatableRegister(Reg, MF, TLI, MRI);
3414 if (!RC) { // Couldn't allocate this register.
3415 // Reset NumAllocated to make sure we return consecutive registers.
3421 // Okay, this register is good, we can use it.
3424 // If we allocated enough consecutive registers, succeed.
3425 if (NumAllocated == NumRegs) {
3426 unsigned RegStart = (i-NumAllocated)+1;
3427 unsigned RegEnd = i+1;
3428 // Mark all of the allocated registers used.
3429 for (unsigned i = RegStart; i != RegEnd; ++i)
3430 Regs.push_back(RegClassRegs[i]);
3432 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3433 OpInfo.ConstraintVT);
3434 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3439 // Otherwise, we couldn't allocate enough registers for this.
3444 /// visitInlineAsm - Handle a call to an InlineAsm object.
3446 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
3447 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
3449 /// ConstraintOperands - Information about all of the constraints.
3450 std::vector<AsmOperandInfo> ConstraintOperands;
3452 SDOperand Chain = getRoot();
3455 std::set<unsigned> OutputRegs, InputRegs;
3457 // Do a prepass over the constraints, canonicalizing them, and building up the
3458 // ConstraintOperands list.
3459 std::vector<InlineAsm::ConstraintInfo>
3460 ConstraintInfos = IA->ParseConstraints();
3462 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3463 // constraint. If so, we can't let the register allocator allocate any input
3464 // registers, because it will not know to avoid the earlyclobbered output reg.
3465 bool SawEarlyClobber = false;
3467 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3468 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3469 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
3470 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3472 MVT::ValueType OpVT = MVT::Other;
3474 // Compute the value type for each operand.
3475 switch (OpInfo.Type) {
3476 case InlineAsm::isOutput:
3477 if (!OpInfo.isIndirect) {
3478 // The return value of the call is this value. As such, there is no
3479 // corresponding argument.
3480 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3481 OpVT = TLI.getValueType(CS.getType());
3483 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3486 case InlineAsm::isInput:
3487 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3489 case InlineAsm::isClobber:
3494 // If this is an input or an indirect output, process the call argument.
3495 // BasicBlocks are labels, currently appearing only in asm's.
3496 if (OpInfo.CallOperandVal) {
3497 if (isa<BasicBlock>(OpInfo.CallOperandVal))
3498 OpInfo.CallOperand =
3499 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>(OpInfo.CallOperandVal)]);
3501 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3502 const Type *OpTy = OpInfo.CallOperandVal->getType();
3503 // If this is an indirect operand, the operand is a pointer to the
3505 if (OpInfo.isIndirect)
3506 OpTy = cast<PointerType>(OpTy)->getElementType();
3508 // If OpTy is not a first-class value, it may be a struct/union that we
3509 // can tile with integers.
3510 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3511 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3519 OpTy = IntegerType::get(BitSize);
3524 OpVT = TLI.getValueType(OpTy, true);
3528 OpInfo.ConstraintVT = OpVT;
3530 // Compute the constraint code and ConstraintType to use.
3531 OpInfo.ComputeConstraintToUse(TLI);
3533 // Keep track of whether we see an earlyclobber.
3534 SawEarlyClobber |= OpInfo.isEarlyClobber;
3536 // If this is a memory input, and if the operand is not indirect, do what we
3537 // need to to provide an address for the memory input.
3538 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3539 !OpInfo.isIndirect) {
3540 assert(OpInfo.Type == InlineAsm::isInput &&
3541 "Can only indirectify direct input operands!");
3543 // Memory operands really want the address of the value. If we don't have
3544 // an indirect input, put it in the constpool if we can, otherwise spill
3545 // it to a stack slot.
3547 // If the operand is a float, integer, or vector constant, spill to a
3548 // constant pool entry to get its address.
3549 Value *OpVal = OpInfo.CallOperandVal;
3550 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3551 isa<ConstantVector>(OpVal)) {
3552 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3553 TLI.getPointerTy());
3555 // Otherwise, create a stack slot and emit a store to it before the
3557 const Type *Ty = OpVal->getType();
3558 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3559 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3560 MachineFunction &MF = DAG.getMachineFunction();
3561 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3562 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3563 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3564 OpInfo.CallOperand = StackSlot;
3567 // There is no longer a Value* corresponding to this operand.
3568 OpInfo.CallOperandVal = 0;
3569 // It is now an indirect operand.
3570 OpInfo.isIndirect = true;
3573 // If this constraint is for a specific register, allocate it before
3575 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3576 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3578 ConstraintInfos.clear();
3581 // Second pass - Loop over all of the operands, assigning virtual or physregs
3582 // to registerclass operands.
3583 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3584 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3586 // C_Register operands have already been allocated, Other/Memory don't need
3588 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3589 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3592 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3593 std::vector<SDOperand> AsmNodeOperands;
3594 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3595 AsmNodeOperands.push_back(
3596 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3599 // Loop over all of the inputs, copying the operand values into the
3600 // appropriate registers and processing the output regs.
3601 RegsForValue RetValRegs;
3603 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3604 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3606 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3607 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3609 switch (OpInfo.Type) {
3610 case InlineAsm::isOutput: {
3611 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3612 OpInfo.ConstraintType != TargetLowering::C_Register) {
3613 // Memory output, or 'other' output (e.g. 'X' constraint).
3614 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
3616 // Add information to the INLINEASM node to know about this output.
3617 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3618 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3619 TLI.getPointerTy()));
3620 AsmNodeOperands.push_back(OpInfo.CallOperand);
3624 // Otherwise, this is a register or register class output.
3626 // Copy the output from the appropriate register. Find a register that
3628 if (OpInfo.AssignedRegs.Regs.empty()) {
3629 cerr << "Couldn't allocate output reg for contraint '"
3630 << OpInfo.ConstraintCode << "'!\n";
3634 if (!OpInfo.isIndirect) {
3635 // This is the result value of the call.
3636 assert(RetValRegs.Regs.empty() &&
3637 "Cannot have multiple output constraints yet!");
3638 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3639 RetValRegs = OpInfo.AssignedRegs;
3641 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
3642 OpInfo.CallOperandVal));
3645 // Add information to the INLINEASM node to know that this register is
3647 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3651 case InlineAsm::isInput: {
3652 SDOperand InOperandVal = OpInfo.CallOperand;
3654 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
3655 // If this is required to match an output register we have already set,
3656 // just use its register.
3657 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
3659 // Scan until we find the definition we already emitted of this operand.
3660 // When we find it, create a RegsForValue operand.
3661 unsigned CurOp = 2; // The first operand.
3662 for (; OperandNo; --OperandNo) {
3663 // Advance to the next operand.
3665 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3666 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3667 (NumOps & 7) == 4 /*MEM*/) &&
3668 "Skipped past definitions?");
3669 CurOp += (NumOps>>3)+1;
3673 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3674 if ((NumOps & 7) == 2 /*REGDEF*/) {
3675 // Add NumOps>>3 registers to MatchedRegs.
3676 RegsForValue MatchedRegs;
3677 MatchedRegs.ValueVT = InOperandVal.getValueType();
3678 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3679 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3681 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3682 MatchedRegs.Regs.push_back(Reg);
3685 // Use the produced MatchedRegs object to
3686 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3687 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3690 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3691 assert(0 && "matching constraints for memory operands unimp");
3695 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
3696 assert(!OpInfo.isIndirect &&
3697 "Don't know how to handle indirect other inputs yet!");
3699 std::vector<SDOperand> Ops;
3700 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
3703 cerr << "Invalid operand for inline asm constraint '"
3704 << OpInfo.ConstraintCode << "'!\n";
3708 // Add information to the INLINEASM node to know about this input.
3709 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
3710 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3711 TLI.getPointerTy()));
3712 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
3714 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
3715 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
3716 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3717 "Memory operands expect pointer values");
3719 // Add information to the INLINEASM node to know about this input.
3720 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3721 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3722 TLI.getPointerTy()));
3723 AsmNodeOperands.push_back(InOperandVal);
3727 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3728 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3729 "Unknown constraint type!");
3730 assert(!OpInfo.isIndirect &&
3731 "Don't know how to handle indirect register inputs yet!");
3733 // Copy the input into the appropriate registers.
3734 assert(!OpInfo.AssignedRegs.Regs.empty() &&
3735 "Couldn't allocate input reg!");
3737 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3739 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
3743 case InlineAsm::isClobber: {
3744 // Add the clobbered value to the operand list, so that the register
3745 // allocator is aware that the physreg got clobbered.
3746 if (!OpInfo.AssignedRegs.Regs.empty())
3747 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
3754 // Finish up input operands.
3755 AsmNodeOperands[0] = Chain;
3756 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3758 Chain = DAG.getNode(ISD::INLINEASM,
3759 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
3760 &AsmNodeOperands[0], AsmNodeOperands.size());
3761 Flag = Chain.getValue(1);
3763 // If this asm returns a register value, copy the result from that register
3764 // and set it as the value of the call.
3765 if (!RetValRegs.Regs.empty()) {
3766 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
3768 // If the result of the inline asm is a vector, it may have the wrong
3769 // width/num elts. Make sure to convert it to the right type with
3771 if (MVT::isVector(Val.getValueType())) {
3772 const VectorType *VTy = cast<VectorType>(CS.getType());
3773 MVT::ValueType DesiredVT = TLI.getValueType(VTy);
3775 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
3778 setValue(CS.getInstruction(), Val);
3781 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
3783 // Process indirect outputs, first output all of the flagged copies out of
3785 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
3786 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
3787 Value *Ptr = IndirectStoresToEmit[i].second;
3788 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
3789 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
3792 // Emit the non-flagged stores from the physregs.
3793 SmallVector<SDOperand, 8> OutChains;
3794 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
3795 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
3796 getValue(StoresToEmit[i].second),
3797 StoresToEmit[i].second, 0));
3798 if (!OutChains.empty())
3799 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3800 &OutChains[0], OutChains.size());
3805 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
3806 SDOperand Src = getValue(I.getOperand(0));
3808 MVT::ValueType IntPtr = TLI.getPointerTy();
3810 if (IntPtr < Src.getValueType())
3811 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
3812 else if (IntPtr > Src.getValueType())
3813 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
3815 // Scale the source by the type size.
3816 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
3817 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
3818 Src, getIntPtrConstant(ElementSize));
3820 TargetLowering::ArgListTy Args;
3821 TargetLowering::ArgListEntry Entry;
3823 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3824 Args.push_back(Entry);
3826 std::pair<SDOperand,SDOperand> Result =
3827 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
3828 DAG.getExternalSymbol("malloc", IntPtr),
3830 setValue(&I, Result.first); // Pointers always fit in registers
3831 DAG.setRoot(Result.second);
3834 void SelectionDAGLowering::visitFree(FreeInst &I) {
3835 TargetLowering::ArgListTy Args;
3836 TargetLowering::ArgListEntry Entry;
3837 Entry.Node = getValue(I.getOperand(0));
3838 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3839 Args.push_back(Entry);
3840 MVT::ValueType IntPtr = TLI.getPointerTy();
3841 std::pair<SDOperand,SDOperand> Result =
3842 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
3843 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
3844 DAG.setRoot(Result.second);
3847 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
3848 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
3849 // instructions are special in various ways, which require special support to
3850 // insert. The specified MachineInstr is created but not inserted into any
3851 // basic blocks, and the scheduler passes ownership of it to this method.
3852 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
3853 MachineBasicBlock *MBB) {
3854 cerr << "If a target marks an instruction with "
3855 << "'usesCustomDAGSchedInserter', it must implement "
3856 << "TargetLowering::InsertAtEndOfBasicBlock!\n";
3861 void SelectionDAGLowering::visitVAStart(CallInst &I) {
3862 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
3863 getValue(I.getOperand(1)),
3864 DAG.getSrcValue(I.getOperand(1))));
3867 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
3868 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
3869 getValue(I.getOperand(0)),
3870 DAG.getSrcValue(I.getOperand(0)));
3872 DAG.setRoot(V.getValue(1));
3875 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
3876 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
3877 getValue(I.getOperand(1)),
3878 DAG.getSrcValue(I.getOperand(1))));
3881 void SelectionDAGLowering::visitVACopy(CallInst &I) {
3882 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
3883 getValue(I.getOperand(1)),
3884 getValue(I.getOperand(2)),
3885 DAG.getSrcValue(I.getOperand(1)),
3886 DAG.getSrcValue(I.getOperand(2))));
3889 /// TargetLowering::LowerArguments - This is the default LowerArguments
3890 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
3891 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
3892 /// integrated into SDISel.
3893 std::vector<SDOperand>
3894 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
3895 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
3896 std::vector<SDOperand> Ops;
3897 Ops.push_back(DAG.getRoot());
3898 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
3899 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
3901 // Add one result value for each formal argument.
3902 std::vector<MVT::ValueType> RetVals;
3904 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
3906 MVT::ValueType VT = getValueType(I->getType());
3907 unsigned Flags = ISD::ParamFlags::NoFlagSet;
3908 unsigned OriginalAlignment =
3909 getTargetData()->getABITypeAlignment(I->getType());
3911 // FIXME: Distinguish between a formal with no [sz]ext attribute from one
3912 // that is zero extended!
3913 if (F.paramHasAttr(j, ParamAttr::ZExt))
3914 Flags &= ~(ISD::ParamFlags::SExt);
3915 if (F.paramHasAttr(j, ParamAttr::SExt))
3916 Flags |= ISD::ParamFlags::SExt;
3917 if (F.paramHasAttr(j, ParamAttr::InReg))
3918 Flags |= ISD::ParamFlags::InReg;
3919 if (F.paramHasAttr(j, ParamAttr::StructRet))
3920 Flags |= ISD::ParamFlags::StructReturn;
3921 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
3922 Flags |= ISD::ParamFlags::ByVal;
3923 const PointerType *Ty = cast<PointerType>(I->getType());
3924 const Type *ElementTy = Ty->getElementType();
3925 unsigned FrameAlign =
3926 Log2_32(getTargetData()->getCallFrameTypeAlignment(ElementTy));
3927 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
3928 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs);
3929 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs);
3931 if (F.paramHasAttr(j, ParamAttr::Nest))
3932 Flags |= ISD::ParamFlags::Nest;
3933 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
3935 switch (getTypeAction(VT)) {
3936 default: assert(0 && "Unknown type action!");
3938 RetVals.push_back(VT);
3939 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3942 RetVals.push_back(getTypeToTransformTo(VT));
3943 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3946 // If this is an illegal type, it needs to be broken up to fit into
3948 MVT::ValueType RegisterVT = getRegisterType(VT);
3949 unsigned NumRegs = getNumRegisters(VT);
3950 for (unsigned i = 0; i != NumRegs; ++i) {
3951 RetVals.push_back(RegisterVT);
3952 // if it isn't first piece, alignment must be 1
3954 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
3955 (1 << ISD::ParamFlags::OrigAlignmentOffs);
3956 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3963 RetVals.push_back(MVT::Other);
3966 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
3967 DAG.getNodeValueTypes(RetVals), RetVals.size(),
3968 &Ops[0], Ops.size()).Val;
3969 unsigned NumArgRegs = Result->getNumValues() - 1;
3970 DAG.setRoot(SDOperand(Result, NumArgRegs));
3972 // Set up the return result vector.
3976 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
3978 MVT::ValueType VT = getValueType(I->getType());
3980 switch (getTypeAction(VT)) {
3981 default: assert(0 && "Unknown type action!");
3983 Ops.push_back(SDOperand(Result, i++));
3986 SDOperand Op(Result, i++);
3987 if (MVT::isInteger(VT)) {
3988 if (F.paramHasAttr(Idx, ParamAttr::SExt))
3989 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
3990 DAG.getValueType(VT));
3991 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
3992 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
3993 DAG.getValueType(VT));
3994 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
3996 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
3997 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
4003 MVT::ValueType PartVT = getRegisterType(VT);
4004 unsigned NumParts = getNumRegisters(VT);
4005 SmallVector<SDOperand, 4> Parts(NumParts);
4006 for (unsigned j = 0; j != NumParts; ++j)
4007 Parts[j] = SDOperand(Result, i++);
4008 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT));
4013 assert(i == NumArgRegs && "Argument register count mismatch!");
4018 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4019 /// implementation, which just inserts an ISD::CALL node, which is later custom
4020 /// lowered by the target to something concrete. FIXME: When all targets are
4021 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4022 std::pair<SDOperand, SDOperand>
4023 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4024 bool RetTyIsSigned, bool isVarArg,
4025 unsigned CallingConv, bool isTailCall,
4027 ArgListTy &Args, SelectionDAG &DAG) {
4028 SmallVector<SDOperand, 32> Ops;
4029 Ops.push_back(Chain); // Op#0 - Chain
4030 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4031 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4032 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4033 Ops.push_back(Callee);
4035 // Handle all of the outgoing arguments.
4036 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4037 MVT::ValueType VT = getValueType(Args[i].Ty);
4038 SDOperand Op = Args[i].Node;
4039 unsigned Flags = ISD::ParamFlags::NoFlagSet;
4040 unsigned OriginalAlignment =
4041 getTargetData()->getABITypeAlignment(Args[i].Ty);
4044 Flags |= ISD::ParamFlags::SExt;
4046 Flags |= ISD::ParamFlags::ZExt;
4047 if (Args[i].isInReg)
4048 Flags |= ISD::ParamFlags::InReg;
4050 Flags |= ISD::ParamFlags::StructReturn;
4051 if (Args[i].isByVal) {
4052 Flags |= ISD::ParamFlags::ByVal;
4053 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4054 const Type *ElementTy = Ty->getElementType();
4055 unsigned FrameAlign =
4056 Log2_32(getTargetData()->getCallFrameTypeAlignment(ElementTy));
4057 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4058 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs);
4059 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs);
4062 Flags |= ISD::ParamFlags::Nest;
4063 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;
4065 switch (getTypeAction(VT)) {
4066 default: assert(0 && "Unknown type action!");
4069 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
4072 if (MVT::isInteger(VT)) {
4075 ExtOp = ISD::SIGN_EXTEND;
4076 else if (Args[i].isZExt)
4077 ExtOp = ISD::ZERO_EXTEND;
4079 ExtOp = ISD::ANY_EXTEND;
4080 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
4082 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
4083 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
4086 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
4089 MVT::ValueType PartVT = getRegisterType(VT);
4090 unsigned NumParts = getNumRegisters(VT);
4091 SmallVector<SDOperand, 4> Parts(NumParts);
4092 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT);
4093 for (unsigned i = 0; i != NumParts; ++i) {
4094 // if it isn't first piece, alignment must be 1
4095 unsigned MyFlags = Flags;
4097 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) |
4098 (1 << ISD::ParamFlags::OrigAlignmentOffs);
4100 Ops.push_back(Parts[i]);
4101 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32));
4108 // Figure out the result value types.
4109 MVT::ValueType VT = getValueType(RetTy);
4110 MVT::ValueType RegisterVT = getRegisterType(VT);
4111 unsigned NumRegs = getNumRegisters(VT);
4112 SmallVector<MVT::ValueType, 4> RetTys(NumRegs);
4113 for (unsigned i = 0; i != NumRegs; ++i)
4114 RetTys[i] = RegisterVT;
4116 RetTys.push_back(MVT::Other); // Always has a chain.
4118 // Create the CALL node.
4119 SDOperand Res = DAG.getNode(ISD::CALL,
4120 DAG.getVTList(&RetTys[0], NumRegs + 1),
4121 &Ops[0], Ops.size());
4122 Chain = Res.getValue(NumRegs);
4124 // Gather up the call result into a single value.
4125 if (RetTy != Type::VoidTy) {
4126 ISD::NodeType AssertOp = ISD::AssertSext;
4128 AssertOp = ISD::AssertZext;
4129 SmallVector<SDOperand, 4> Results(NumRegs);
4130 for (unsigned i = 0; i != NumRegs; ++i)
4131 Results[i] = Res.getValue(i);
4132 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp);
4135 return std::make_pair(Res, Chain);
4138 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4139 assert(0 && "LowerOperation not implemented for this target!");
4144 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4145 SelectionDAG &DAG) {
4146 assert(0 && "CustomPromoteOperation not implemented for this target!");
4151 /// getMemsetValue - Vectorized representation of the memset value
4153 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
4154 SelectionDAG &DAG) {
4155 MVT::ValueType CurVT = VT;
4156 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4157 uint64_t Val = C->getValue() & 255;
4159 while (CurVT != MVT::i8) {
4160 Val = (Val << Shift) | Val;
4162 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4164 return DAG.getConstant(Val, VT);
4166 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4168 while (CurVT != MVT::i8) {
4170 DAG.getNode(ISD::OR, VT,
4171 DAG.getNode(ISD::SHL, VT, Value,
4172 DAG.getConstant(Shift, MVT::i8)), Value);
4174 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4181 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4182 /// used when a memcpy is turned into a memset when the source is a constant
4184 static SDOperand getMemsetStringVal(MVT::ValueType VT,
4185 SelectionDAG &DAG, TargetLowering &TLI,
4186 std::string &Str, unsigned Offset) {
4188 unsigned MSB = MVT::getSizeInBits(VT) / 8;
4189 if (TLI.isLittleEndian())
4190 Offset = Offset + MSB - 1;
4191 for (unsigned i = 0; i != MSB; ++i) {
4192 Val = (Val << 8) | (unsigned char)Str[Offset];
4193 Offset += TLI.isLittleEndian() ? -1 : 1;
4195 return DAG.getConstant(Val, VT);
4198 /// getMemBasePlusOffset - Returns base and offset node for the
4199 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4200 SelectionDAG &DAG, TargetLowering &TLI) {
4201 MVT::ValueType VT = Base.getValueType();
4202 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4205 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
4206 /// to replace the memset / memcpy is below the threshold. It also returns the
4207 /// types of the sequence of memory ops to perform memset / memcpy.
4208 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4209 unsigned Limit, uint64_t Size,
4210 unsigned Align, TargetLowering &TLI) {
4213 if (TLI.allowsUnalignedMemoryAccesses()) {
4216 switch (Align & 7) {
4232 MVT::ValueType LVT = MVT::i64;
4233 while (!TLI.isTypeLegal(LVT))
4234 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4235 assert(MVT::isInteger(LVT));
4240 unsigned NumMemOps = 0;
4242 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4243 while (VTSize > Size) {
4244 VT = (MVT::ValueType)((unsigned)VT - 1);
4247 assert(MVT::isInteger(VT));
4249 if (++NumMemOps > Limit)
4251 MemOps.push_back(VT);
4258 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
4259 SDOperand Op1 = getValue(I.getOperand(1));
4260 SDOperand Op2 = getValue(I.getOperand(2));
4261 SDOperand Op3 = getValue(I.getOperand(3));
4262 SDOperand Op4 = getValue(I.getOperand(4));
4263 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4264 if (Align == 0) Align = 1;
4266 // If the source and destination are known to not be aliases, we can
4267 // lower memmove as memcpy.
4268 if (Op == ISD::MEMMOVE) {
4269 uint64_t Size = -1ULL;
4270 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4271 Size = C->getValue();
4272 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
4273 AliasAnalysis::NoAlias)
4277 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4278 std::vector<MVT::ValueType> MemOps;
4280 // Expand memset / memcpy to a series of load / store ops
4281 // if the size operand falls below a certain threshold.
4282 SmallVector<SDOperand, 8> OutChains;
4284 default: break; // Do nothing for now.
4286 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4287 Size->getValue(), Align, TLI)) {
4288 unsigned NumMemOps = MemOps.size();
4289 unsigned Offset = 0;
4290 for (unsigned i = 0; i < NumMemOps; i++) {
4291 MVT::ValueType VT = MemOps[i];
4292 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4293 SDOperand Value = getMemsetValue(Op2, VT, DAG);
4294 SDOperand Store = DAG.getStore(getRoot(), Value,
4295 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
4296 I.getOperand(1), Offset);
4297 OutChains.push_back(Store);
4304 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4305 Size->getValue(), Align, TLI)) {
4306 unsigned NumMemOps = MemOps.size();
4307 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
4308 GlobalAddressSDNode *G = NULL;
4310 bool CopyFromStr = false;
4312 if (Op2.getOpcode() == ISD::GlobalAddress)
4313 G = cast<GlobalAddressSDNode>(Op2);
4314 else if (Op2.getOpcode() == ISD::ADD &&
4315 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4316 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4317 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
4318 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
4321 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
4322 if (GV && GV->isConstant()) {
4323 Str = GV->getStringValue(false);
4331 for (unsigned i = 0; i < NumMemOps; i++) {
4332 MVT::ValueType VT = MemOps[i];
4333 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4334 SDOperand Value, Chain, Store;
4337 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4340 DAG.getStore(Chain, Value,
4341 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4342 I.getOperand(1), DstOff);
4344 Value = DAG.getLoad(VT, getRoot(),
4345 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4346 I.getOperand(2), SrcOff, false, Align);
4347 Chain = Value.getValue(1);
4349 DAG.getStore(Chain, Value,
4350 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4351 I.getOperand(1), DstOff, false, Align);
4353 OutChains.push_back(Store);
4362 if (!OutChains.empty()) {
4363 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4364 &OutChains[0], OutChains.size()));
4369 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1);
4373 assert(0 && "Unknown Op");
4375 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4378 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4381 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4387 //===----------------------------------------------------------------------===//
4388 // SelectionDAGISel code
4389 //===----------------------------------------------------------------------===//
4391 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4392 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4395 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4396 AU.addRequired<AliasAnalysis>();
4397 AU.addRequired<CollectorModuleMetadata>();
4398 AU.setPreservesAll();
4403 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4404 // Get alias analysis for load/store combining.
4405 AA = &getAnalysis<AliasAnalysis>();
4407 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4408 if (MF.getFunction()->hasCollector())
4409 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4412 RegInfo = &MF.getRegInfo();
4413 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4415 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4417 if (ExceptionHandling)
4418 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4419 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4420 // Mark landing pad.
4421 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4423 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4424 SelectBasicBlock(I, MF, FuncInfo);
4426 // Add function live-ins to entry block live-in set.
4427 BasicBlock *EntryBB = &Fn.getEntryBlock();
4428 BB = FuncInfo.MBBMap[EntryBB];
4429 if (!RegInfo->livein_empty())
4430 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4431 E = RegInfo->livein_end(); I != E; ++I)
4432 BB->addLiveIn(I->first);
4435 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4436 "Not all catch info was assigned to a landing pad!");
4442 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4444 SDOperand Op = getValue(V);
4445 assert((Op.getOpcode() != ISD::CopyFromReg ||
4446 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4447 "Copy from a reg to the same reg!");
4449 MVT::ValueType SrcVT = Op.getValueType();
4450 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4451 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4452 SmallVector<SDOperand, 8> Regs(NumRegs);
4453 SmallVector<SDOperand, 8> Chains(NumRegs);
4455 // Copy the value by legal parts into sequential virtual registers.
4456 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
4457 for (unsigned i = 0; i != NumRegs; ++i)
4458 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
4459 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4462 void SelectionDAGISel::
4463 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
4464 std::vector<SDOperand> &UnorderedChains) {
4465 // If this is the entry block, emit arguments.
4466 Function &F = *LLVMBB->getParent();
4467 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4468 SDOperand OldRoot = SDL.DAG.getRoot();
4469 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4472 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4474 if (!AI->use_empty()) {
4475 SDL.setValue(AI, Args[a]);
4477 // If this argument is live outside of the entry block, insert a copy from
4478 // whereever we got it to the vreg that other BB's will reference it as.
4479 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4480 if (VMI != FuncInfo.ValueMap.end()) {
4481 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second);
4482 UnorderedChains.push_back(Copy);
4486 // Finally, if the target has anything special to do, allow it to do so.
4487 // FIXME: this should insert code into the DAG!
4488 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4491 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4492 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4493 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4494 if (isSelector(I)) {
4495 // Apply the catch info to DestBB.
4496 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4498 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4499 FLI.CatchInfoFound.insert(I);
4504 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
4505 /// DAG and fixes their tailcall attribute operand.
4506 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4507 TargetLowering& TLI) {
4508 SDNode * Ret = NULL;
4509 SDOperand Terminator = DAG.getRoot();
4512 if (Terminator.getOpcode() == ISD::RET) {
4513 Ret = Terminator.Val;
4516 // Fix tail call attribute of CALL nodes.
4517 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
4518 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
4519 if (BI->getOpcode() == ISD::CALL) {
4520 SDOperand OpRet(Ret, 0);
4521 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
4522 bool isMarkedTailCall =
4523 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
4524 // If CALL node has tail call attribute set to true and the call is not
4525 // eligible (no RET or the target rejects) the attribute is fixed to
4526 // false. The TargetLowering::IsEligibleForTailCallOptimization function
4527 // must correctly identify tail call optimizable calls.
4528 if (isMarkedTailCall &&
4530 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) {
4531 SmallVector<SDOperand, 32> Ops;
4533 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
4534 E=OpCall.Val->op_end(); I!=E; I++, idx++) {
4538 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
4540 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4546 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4547 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4548 FunctionLoweringInfo &FuncInfo) {
4549 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
4551 std::vector<SDOperand> UnorderedChains;
4553 // Lower any arguments needed in this block if this is the entry block.
4554 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4555 LowerArguments(LLVMBB, SDL, UnorderedChains);
4557 BB = FuncInfo.MBBMap[LLVMBB];
4558 SDL.setCurrentBasicBlock(BB);
4560 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4562 if (ExceptionHandling && MMI && BB->isLandingPad()) {
4563 // Add a label to mark the beginning of the landing pad. Deletion of the
4564 // landing pad can thus be detected via the MachineModuleInfo.
4565 unsigned LabelID = MMI->addLandingPad(BB);
4566 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4567 DAG.getConstant(LabelID, MVT::i32)));
4569 // Mark exception register as live in.
4570 unsigned Reg = TLI.getExceptionAddressRegister();
4571 if (Reg) BB->addLiveIn(Reg);
4573 // Mark exception selector register as live in.
4574 Reg = TLI.getExceptionSelectorRegister();
4575 if (Reg) BB->addLiveIn(Reg);
4577 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4578 // function and list of typeids logically belong to the invoke (or, if you
4579 // like, the basic block containing the invoke), and need to be associated
4580 // with it in the dwarf exception handling tables. Currently however the
4581 // information is provided by an intrinsic (eh.selector) that can be moved
4582 // to unexpected places by the optimizers: if the unwind edge is critical,
4583 // then breaking it can result in the intrinsics being in the successor of
4584 // the landing pad, not the landing pad itself. This results in exceptions
4585 // not being caught because no typeids are associated with the invoke.
4586 // This may not be the only way things can go wrong, but it is the only way
4587 // we try to work around for the moment.
4588 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4590 if (Br && Br->isUnconditional()) { // Critical edge?
4591 BasicBlock::iterator I, E;
4592 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
4597 // No catch info found - try to extract some from the successor.
4598 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
4602 // Lower all of the non-terminator instructions.
4603 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4607 // Ensure that all instructions which are used outside of their defining
4608 // blocks are available as virtual registers. Invoke is handled elsewhere.
4609 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4610 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
4611 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4612 if (VMI != FuncInfo.ValueMap.end())
4613 UnorderedChains.push_back(
4614 SDL.CopyValueToVirtualRegister(I, VMI->second));
4617 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4618 // ensure constants are generated when needed. Remember the virtual registers
4619 // that need to be added to the Machine PHI nodes as input. We cannot just
4620 // directly add them, because expansion might result in multiple MBB's for one
4621 // BB. As such, the start of the BB might correspond to a different MBB than
4624 TerminatorInst *TI = LLVMBB->getTerminator();
4626 // Emit constants only once even if used by multiple PHI nodes.
4627 std::map<Constant*, unsigned> ConstantsOut;
4629 // Vector bool would be better, but vector<bool> is really slow.
4630 std::vector<unsigned char> SuccsHandled;
4631 if (TI->getNumSuccessors())
4632 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4634 // Check successor nodes' PHI nodes that expect a constant to be available
4636 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4637 BasicBlock *SuccBB = TI->getSuccessor(succ);
4638 if (!isa<PHINode>(SuccBB->begin())) continue;
4639 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4641 // If this terminator has multiple identical successors (common for
4642 // switches), only handle each succ once.
4643 unsigned SuccMBBNo = SuccMBB->getNumber();
4644 if (SuccsHandled[SuccMBBNo]) continue;
4645 SuccsHandled[SuccMBBNo] = true;
4647 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4650 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4651 // nodes and Machine PHI nodes, but the incoming operands have not been
4653 for (BasicBlock::iterator I = SuccBB->begin();
4654 (PN = dyn_cast<PHINode>(I)); ++I) {
4655 // Ignore dead phi's.
4656 if (PN->use_empty()) continue;
4659 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4661 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4662 unsigned &RegOut = ConstantsOut[C];
4664 RegOut = FuncInfo.CreateRegForValue(C);
4665 UnorderedChains.push_back(
4666 SDL.CopyValueToVirtualRegister(C, RegOut));
4670 Reg = FuncInfo.ValueMap[PHIOp];
4672 assert(isa<AllocaInst>(PHIOp) &&
4673 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4674 "Didn't codegen value into a register!??");
4675 Reg = FuncInfo.CreateRegForValue(PHIOp);
4676 UnorderedChains.push_back(
4677 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
4681 // Remember that this register needs to added to the machine PHI node as
4682 // the input for this MBB.
4683 MVT::ValueType VT = TLI.getValueType(PN->getType());
4684 unsigned NumRegisters = TLI.getNumRegisters(VT);
4685 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
4686 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4689 ConstantsOut.clear();
4691 // Turn all of the unordered chains into one factored node.
4692 if (!UnorderedChains.empty()) {
4693 SDOperand Root = SDL.getRoot();
4694 if (Root.getOpcode() != ISD::EntryToken) {
4695 unsigned i = 0, e = UnorderedChains.size();
4696 for (; i != e; ++i) {
4697 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4698 if (UnorderedChains[i].Val->getOperand(0) == Root)
4699 break; // Don't add the root if we already indirectly depend on it.
4703 UnorderedChains.push_back(Root);
4705 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4706 &UnorderedChains[0], UnorderedChains.size()));
4709 // Lower the terminator after the copies are emitted.
4710 SDL.visit(*LLVMBB->getTerminator());
4712 // Copy over any CaseBlock records that may now exist due to SwitchInst
4713 // lowering, as well as any jump table information.
4714 SwitchCases.clear();
4715 SwitchCases = SDL.SwitchCases;
4717 JTCases = SDL.JTCases;
4718 BitTestCases.clear();
4719 BitTestCases = SDL.BitTestCases;
4721 // Make sure the root of the DAG is up-to-date.
4722 DAG.setRoot(SDL.getRoot());
4724 // Check whether calls in this block are real tail calls. Fix up CALL nodes
4725 // with correct tailcall attribute so that the target can rely on the tailcall
4726 // attribute indicating whether the call is really eligible for tail call
4728 CheckDAGForTailCallsAndFixThem(DAG, TLI);
4731 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4732 DOUT << "Lowered selection DAG:\n";
4735 // Run the DAG combiner in pre-legalize mode.
4736 DAG.Combine(false, *AA);
4738 DOUT << "Optimized lowered selection DAG:\n";
4741 // Second step, hack on the DAG until it only uses operations and types that
4742 // the target supports.
4743 #if 0 // Enable this some day.
4744 DAG.LegalizeTypes();
4745 // Someday even later, enable a dag combine pass here.
4749 DOUT << "Legalized selection DAG:\n";
4752 // Run the DAG combiner in post-legalize mode.
4753 DAG.Combine(true, *AA);
4755 DOUT << "Optimized legalized selection DAG:\n";
4758 if (ViewISelDAGs) DAG.viewGraph();
4760 // Third, instruction select all of the operations to machine code, adding the
4761 // code to the MachineBasicBlock.
4762 InstructionSelectBasicBlock(DAG);
4764 DOUT << "Selected machine code:\n";
4768 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4769 FunctionLoweringInfo &FuncInfo) {
4770 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4772 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4775 // First step, lower LLVM code to some DAG. This DAG may use operations and
4776 // types that are not supported by the target.
4777 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4779 // Second step, emit the lowered DAG as machine code.
4780 CodeGenAndEmitDAG(DAG);
4783 DOUT << "Total amount of phi nodes to update: "
4784 << PHINodesToUpdate.size() << "\n";
4785 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4786 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4787 << ", " << PHINodesToUpdate[i].second << ")\n";);
4789 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4790 // PHI nodes in successors.
4791 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
4792 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4793 MachineInstr *PHI = PHINodesToUpdate[i].first;
4794 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4795 "This is not a machine PHI node that we are updating!");
4796 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4798 PHI->addOperand(MachineOperand::CreateMBB(BB));
4803 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4804 // Lower header first, if it wasn't already lowered
4805 if (!BitTestCases[i].Emitted) {
4806 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4808 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
4809 // Set the current basic block to the mbb we wish to insert the code into
4810 BB = BitTestCases[i].Parent;
4811 HSDL.setCurrentBasicBlock(BB);
4813 HSDL.visitBitTestHeader(BitTestCases[i]);
4814 HSDAG.setRoot(HSDL.getRoot());
4815 CodeGenAndEmitDAG(HSDAG);
4818 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4819 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4821 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
4822 // Set the current basic block to the mbb we wish to insert the code into
4823 BB = BitTestCases[i].Cases[j].ThisBB;
4824 BSDL.setCurrentBasicBlock(BB);
4827 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
4828 BitTestCases[i].Reg,
4829 BitTestCases[i].Cases[j]);
4831 BSDL.visitBitTestCase(BitTestCases[i].Default,
4832 BitTestCases[i].Reg,
4833 BitTestCases[i].Cases[j]);
4836 BSDAG.setRoot(BSDL.getRoot());
4837 CodeGenAndEmitDAG(BSDAG);
4841 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4842 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4843 MachineBasicBlock *PHIBB = PHI->getParent();
4844 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4845 "This is not a machine PHI node that we are updating!");
4846 // This is "default" BB. We have two jumps to it. From "header" BB and
4847 // from last "case" BB.
4848 if (PHIBB == BitTestCases[i].Default) {
4849 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4851 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
4852 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4854 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
4857 // One of "cases" BB.
4858 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4859 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
4860 if (cBB->succ_end() !=
4861 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
4862 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4864 PHI->addOperand(MachineOperand::CreateMBB(cBB));
4870 // If the JumpTable record is filled in, then we need to emit a jump table.
4871 // Updating the PHI nodes is tricky in this case, since we need to determine
4872 // whether the PHI is a successor of the range check MBB or the jump table MBB
4873 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
4874 // Lower header first, if it wasn't already lowered
4875 if (!JTCases[i].first.Emitted) {
4876 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4878 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
4879 // Set the current basic block to the mbb we wish to insert the code into
4880 BB = JTCases[i].first.HeaderBB;
4881 HSDL.setCurrentBasicBlock(BB);
4883 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
4884 HSDAG.setRoot(HSDL.getRoot());
4885 CodeGenAndEmitDAG(HSDAG);
4888 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4890 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
4891 // Set the current basic block to the mbb we wish to insert the code into
4892 BB = JTCases[i].second.MBB;
4893 JSDL.setCurrentBasicBlock(BB);
4895 JSDL.visitJumpTable(JTCases[i].second);
4896 JSDAG.setRoot(JSDL.getRoot());
4897 CodeGenAndEmitDAG(JSDAG);
4900 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4901 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4902 MachineBasicBlock *PHIBB = PHI->getParent();
4903 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4904 "This is not a machine PHI node that we are updating!");
4905 // "default" BB. We can go there only from header BB.
4906 if (PHIBB == JTCases[i].second.Default) {
4907 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4909 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
4911 // JT BB. Just iterate over successors here
4912 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
4913 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4915 PHI->addOperand(MachineOperand::CreateMBB(BB));
4920 // If the switch block involved a branch to one of the actual successors, we
4921 // need to update PHI nodes in that block.
4922 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4923 MachineInstr *PHI = PHINodesToUpdate[i].first;
4924 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4925 "This is not a machine PHI node that we are updating!");
4926 if (BB->isSuccessor(PHI->getParent())) {
4927 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4929 PHI->addOperand(MachineOperand::CreateMBB(BB));
4933 // If we generated any switch lowering information, build and codegen any
4934 // additional DAGs necessary.
4935 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
4936 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4938 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
4940 // Set the current basic block to the mbb we wish to insert the code into
4941 BB = SwitchCases[i].ThisBB;
4942 SDL.setCurrentBasicBlock(BB);
4945 SDL.visitSwitchCase(SwitchCases[i]);
4946 SDAG.setRoot(SDL.getRoot());
4947 CodeGenAndEmitDAG(SDAG);
4949 // Handle any PHI nodes in successors of this chunk, as if we were coming
4950 // from the original BB before switch expansion. Note that PHI nodes can
4951 // occur multiple times in PHINodesToUpdate. We have to be very careful to
4952 // handle them the right number of times.
4953 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
4954 for (MachineBasicBlock::iterator Phi = BB->begin();
4955 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
4956 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
4957 for (unsigned pn = 0; ; ++pn) {
4958 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
4959 if (PHINodesToUpdate[pn].first == Phi) {
4960 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
4962 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
4968 // Don't process RHS if same block as LHS.
4969 if (BB == SwitchCases[i].FalseBB)
4970 SwitchCases[i].FalseBB = 0;
4972 // If we haven't handled the RHS, do so now. Otherwise, we're done.
4973 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
4974 SwitchCases[i].FalseBB = 0;
4976 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
4981 //===----------------------------------------------------------------------===//
4982 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
4983 /// target node in the graph.
4984 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
4985 if (ViewSchedDAGs) DAG.viewGraph();
4987 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
4991 RegisterScheduler::setDefault(Ctor);
4994 ScheduleDAG *SL = Ctor(this, &DAG, BB);
4997 if (ViewSUnitDAGs) SL->viewGraph();
5003 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5004 return new HazardRecognizer();
5007 //===----------------------------------------------------------------------===//
5008 // Helper functions used by the generated instruction selector.
5009 //===----------------------------------------------------------------------===//
5010 // Calls to these methods are generated by tblgen.
5012 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5013 /// the dag combiner simplified the 255, we still want to match. RHS is the
5014 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5015 /// specified in the .td file (e.g. 255).
5016 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
5017 int64_t DesiredMaskS) const {
5018 uint64_t ActualMask = RHS->getValue();
5019 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5021 // If the actual mask exactly matches, success!
5022 if (ActualMask == DesiredMask)
5025 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5026 if (ActualMask & ~DesiredMask)
5029 // Otherwise, the DAG Combiner may have proven that the value coming in is
5030 // either already zero or is not demanded. Check for known zero input bits.
5031 uint64_t NeededMask = DesiredMask & ~ActualMask;
5032 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5035 // TODO: check to see if missing bits are just not demanded.
5037 // Otherwise, this pattern doesn't match.
5041 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5042 /// the dag combiner simplified the 255, we still want to match. RHS is the
5043 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5044 /// specified in the .td file (e.g. 255).
5045 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5046 int64_t DesiredMaskS) const {
5047 uint64_t ActualMask = RHS->getValue();
5048 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5050 // If the actual mask exactly matches, success!
5051 if (ActualMask == DesiredMask)
5054 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5055 if (ActualMask & ~DesiredMask)
5058 // Otherwise, the DAG Combiner may have proven that the value coming in is
5059 // either already zero or is not demanded. Check for known zero input bits.
5060 uint64_t NeededMask = DesiredMask & ~ActualMask;
5062 uint64_t KnownZero, KnownOne;
5063 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5065 // If all the missing bits in the or are already known to be set, match!
5066 if ((NeededMask & KnownOne) == NeededMask)
5069 // TODO: check to see if missing bits are just not demanded.
5071 // Otherwise, this pattern doesn't match.
5076 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5077 /// by tblgen. Others should not call it.
5078 void SelectionDAGISel::
5079 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5080 std::vector<SDOperand> InOps;
5081 std::swap(InOps, Ops);
5083 Ops.push_back(InOps[0]); // input chain.
5084 Ops.push_back(InOps[1]); // input asm string.
5086 unsigned i = 2, e = InOps.size();
5087 if (InOps[e-1].getValueType() == MVT::Flag)
5088 --e; // Don't process a flag operand if it is here.
5091 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5092 if ((Flags & 7) != 4 /*MEM*/) {
5093 // Just skip over this operand, copying the operands verbatim.
5094 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5095 i += (Flags >> 3) + 1;
5097 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5098 // Otherwise, this is a memory operand. Ask the target to select it.
5099 std::vector<SDOperand> SelOps;
5100 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5101 cerr << "Could not match memory address. Inline asm failure!\n";
5105 // Add this to the output node.
5106 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5107 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5109 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5114 // Add the flag input back if present.
5115 if (e != InOps.size())
5116 Ops.push_back(InOps.back());
5119 char SelectionDAGISel::ID = 0;