1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/GCStrategy.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/LibCallSemantics.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SelectionDAGISel.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DebugInfo.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/InlineAsm.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/IntrinsicInst.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/IR/LLVMContext.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/MC/MCAsmInfo.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/Timer.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetIntrinsicInfo.h"
55 #include "llvm/Target/TargetLowering.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include "llvm/Target/TargetOptions.h"
58 #include "llvm/Target/TargetRegisterInfo.h"
59 #include "llvm/Target/TargetSubtargetInfo.h"
60 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
64 #define DEBUG_TYPE "isel"
66 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
67 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
68 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
69 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
70 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
71 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
72 STATISTIC(NumFastIselFailLowerArguments,
73 "Number of entry blocks where fast isel failed to lower arguments");
77 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
78 cl::desc("Enable extra verbose messages in the \"fast\" "
79 "instruction selector"));
82 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
83 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
84 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
85 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
86 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
87 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
88 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
90 // Standard binary operators...
91 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
92 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
93 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
94 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
95 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
96 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
97 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
98 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
99 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
100 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
101 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
102 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
104 // Logical operators...
105 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
106 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
107 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
109 // Memory instructions...
110 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
111 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
112 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
113 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
114 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
115 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
116 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
118 // Convert instructions...
119 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
120 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
121 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
122 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
123 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
124 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
125 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
126 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
127 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
128 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
129 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
130 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
132 // Other instructions...
133 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
134 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
135 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
136 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
137 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
138 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
139 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
140 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
141 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
142 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
143 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
144 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
145 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
146 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
147 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
149 // Intrinsic instructions...
150 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
151 STATISTIC(NumFastIselFailSAddWithOverflow,
152 "Fast isel fails on sadd.with.overflow");
153 STATISTIC(NumFastIselFailUAddWithOverflow,
154 "Fast isel fails on uadd.with.overflow");
155 STATISTIC(NumFastIselFailSSubWithOverflow,
156 "Fast isel fails on ssub.with.overflow");
157 STATISTIC(NumFastIselFailUSubWithOverflow,
158 "Fast isel fails on usub.with.overflow");
159 STATISTIC(NumFastIselFailSMulWithOverflow,
160 "Fast isel fails on smul.with.overflow");
161 STATISTIC(NumFastIselFailUMulWithOverflow,
162 "Fast isel fails on umul.with.overflow");
163 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
164 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
165 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
166 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
170 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
171 cl::desc("Enable verbose messages in the \"fast\" "
172 "instruction selector"));
173 static cl::opt<int> EnableFastISelAbort(
174 "fast-isel-abort", cl::Hidden,
175 cl::desc("Enable abort calls when \"fast\" instruction selection "
176 "fails to lower an instruction: 0 disable the abort, 1 will "
177 "abort but for args, calls and terminators, 2 will also "
178 "abort for argument lowering, and 3 will never fallback "
179 "to SelectionDAG."));
183 cl::desc("use Machine Branch Probability Info"),
184 cl::init(true), cl::Hidden);
187 static cl::opt<std::string>
188 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
189 cl::desc("Only display the basic block whose name "
190 "matches this for all view-*-dags options"));
192 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
193 cl::desc("Pop up a window to show dags before the first "
194 "dag combine pass"));
196 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
197 cl::desc("Pop up a window to show dags before legalize types"));
199 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
200 cl::desc("Pop up a window to show dags before legalize"));
202 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
203 cl::desc("Pop up a window to show dags before the second "
204 "dag combine pass"));
206 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
207 cl::desc("Pop up a window to show dags before the post legalize types"
208 " dag combine pass"));
210 ViewISelDAGs("view-isel-dags", cl::Hidden,
211 cl::desc("Pop up a window to show isel dags as they are selected"));
213 ViewSchedDAGs("view-sched-dags", cl::Hidden,
214 cl::desc("Pop up a window to show sched dags as they are processed"));
216 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
217 cl::desc("Pop up a window to show SUnit dags after they are processed"));
219 static const bool ViewDAGCombine1 = false,
220 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
221 ViewDAGCombine2 = false,
222 ViewDAGCombineLT = false,
223 ViewISelDAGs = false, ViewSchedDAGs = false,
224 ViewSUnitDAGs = false;
227 //===---------------------------------------------------------------------===//
229 /// RegisterScheduler class - Track the registration of instruction schedulers.
231 //===---------------------------------------------------------------------===//
232 MachinePassRegistry RegisterScheduler::Registry;
234 //===---------------------------------------------------------------------===//
236 /// ISHeuristic command line option for instruction schedulers.
238 //===---------------------------------------------------------------------===//
239 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
240 RegisterPassParser<RegisterScheduler> >
241 ISHeuristic("pre-RA-sched",
242 cl::init(&createDefaultScheduler), cl::Hidden,
243 cl::desc("Instruction schedulers available (before register"
246 static RegisterScheduler
247 defaultListDAGScheduler("default", "Best scheduler for the target",
248 createDefaultScheduler);
251 //===--------------------------------------------------------------------===//
252 /// \brief This class is used by SelectionDAGISel to temporarily override
253 /// the optimization level on a per-function basis.
254 class OptLevelChanger {
255 SelectionDAGISel &IS;
256 CodeGenOpt::Level SavedOptLevel;
260 OptLevelChanger(SelectionDAGISel &ISel,
261 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
262 SavedOptLevel = IS.OptLevel;
263 if (NewOptLevel == SavedOptLevel)
265 IS.OptLevel = NewOptLevel;
266 IS.TM.setOptLevel(NewOptLevel);
267 SavedFastISel = IS.TM.Options.EnableFastISel;
268 if (NewOptLevel == CodeGenOpt::None)
269 IS.TM.setFastISel(true);
270 DEBUG(dbgs() << "\nChanging optimization level for Function "
271 << IS.MF->getFunction()->getName() << "\n");
272 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
273 << " ; After: -O" << NewOptLevel << "\n");
277 if (IS.OptLevel == SavedOptLevel)
279 DEBUG(dbgs() << "\nRestoring optimization level for Function "
280 << IS.MF->getFunction()->getName() << "\n");
281 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
282 << " ; After: -O" << SavedOptLevel << "\n");
283 IS.OptLevel = SavedOptLevel;
284 IS.TM.setOptLevel(SavedOptLevel);
285 IS.TM.setFastISel(SavedFastISel);
289 //===--------------------------------------------------------------------===//
290 /// createDefaultScheduler - This creates an instruction scheduler appropriate
292 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
293 CodeGenOpt::Level OptLevel) {
294 const TargetLowering *TLI = IS->TLI;
295 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
297 // Try first to see if the Target has its own way of selecting a scheduler
298 if (auto *SchedulerCtor = ST.getDAGScheduler(OptLevel)) {
299 return SchedulerCtor(IS, OptLevel);
302 if (OptLevel == CodeGenOpt::None ||
303 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
304 TLI->getSchedulingPreference() == Sched::Source)
305 return createSourceListDAGScheduler(IS, OptLevel);
306 if (TLI->getSchedulingPreference() == Sched::RegPressure)
307 return createBURRListDAGScheduler(IS, OptLevel);
308 if (TLI->getSchedulingPreference() == Sched::Hybrid)
309 return createHybridListDAGScheduler(IS, OptLevel);
310 if (TLI->getSchedulingPreference() == Sched::VLIW)
311 return createVLIWDAGScheduler(IS, OptLevel);
312 assert(TLI->getSchedulingPreference() == Sched::ILP &&
313 "Unknown sched type!");
314 return createILPListDAGScheduler(IS, OptLevel);
318 // EmitInstrWithCustomInserter - This method should be implemented by targets
319 // that mark instructions with the 'usesCustomInserter' flag. These
320 // instructions are special in various ways, which require special support to
321 // insert. The specified MachineInstr is created but not inserted into any
322 // basic blocks, and this method is called to expand it into a sequence of
323 // instructions, potentially also creating new basic blocks and control flow.
324 // When new basic blocks are inserted and the edges from MBB to its successors
325 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
328 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
329 MachineBasicBlock *MBB) const {
331 dbgs() << "If a target marks an instruction with "
332 "'usesCustomInserter', it must implement "
333 "TargetLowering::EmitInstrWithCustomInserter!";
335 llvm_unreachable(nullptr);
338 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
339 SDNode *Node) const {
340 assert(!MI->hasPostISelHook() &&
341 "If a target marks an instruction with 'hasPostISelHook', "
342 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
345 //===----------------------------------------------------------------------===//
346 // SelectionDAGISel code
347 //===----------------------------------------------------------------------===//
349 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
350 CodeGenOpt::Level OL) :
351 MachineFunctionPass(ID), TM(tm),
352 FuncInfo(new FunctionLoweringInfo()),
353 CurDAG(new SelectionDAG(tm, OL)),
354 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
358 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
359 initializeBranchProbabilityInfoWrapperPassPass(
360 *PassRegistry::getPassRegistry());
361 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
362 initializeTargetLibraryInfoWrapperPassPass(
363 *PassRegistry::getPassRegistry());
366 SelectionDAGISel::~SelectionDAGISel() {
372 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
373 AU.addRequired<AAResultsWrapperPass>();
374 AU.addRequired<GCModuleInfo>();
375 AU.addPreserved<GCModuleInfo>();
376 AU.addRequired<TargetLibraryInfoWrapperPass>();
377 if (UseMBPI && OptLevel != CodeGenOpt::None)
378 AU.addRequired<BranchProbabilityInfoWrapperPass>();
379 MachineFunctionPass::getAnalysisUsage(AU);
382 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
383 /// may trap on it. In this case we have to split the edge so that the path
384 /// through the predecessor block that doesn't go to the phi block doesn't
385 /// execute the possibly trapping instruction.
387 /// This is required for correctness, so it must be done at -O0.
389 static void SplitCriticalSideEffectEdges(Function &Fn) {
390 // Loop for blocks with phi nodes.
391 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
392 PHINode *PN = dyn_cast<PHINode>(BB->begin());
396 // For each block with a PHI node, check to see if any of the input values
397 // are potentially trapping constant expressions. Constant expressions are
398 // the only potentially trapping value that can occur as the argument to a
400 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
401 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
402 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
403 if (!CE || !CE->canTrap()) continue;
405 // The only case we have to worry about is when the edge is critical.
406 // Since this block has a PHI Node, we assume it has multiple input
407 // edges: check to see if the pred has multiple successors.
408 BasicBlock *Pred = PN->getIncomingBlock(i);
409 if (Pred->getTerminator()->getNumSuccessors() == 1)
412 // Okay, we have to split this edge.
414 Pred->getTerminator(), GetSuccessorNumber(Pred, BB),
415 CriticalEdgeSplittingOptions().setMergeIdenticalEdges());
421 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
422 // Do some sanity-checking on the command-line options.
423 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
424 "-fast-isel-verbose requires -fast-isel");
425 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
426 "-fast-isel-abort > 0 requires -fast-isel");
428 const Function &Fn = *mf.getFunction();
431 // Reset the target options before resetting the optimization
433 // FIXME: This is a horrible hack and should be processed via
434 // codegen looking at the optimization level explicitly when
435 // it wants to look at it.
436 TM.resetTargetOptions(Fn);
437 // Reset OptLevel to None for optnone functions.
438 CodeGenOpt::Level NewOptLevel = OptLevel;
439 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
440 NewOptLevel = CodeGenOpt::None;
441 OptLevelChanger OLC(*this, NewOptLevel);
443 TII = MF->getSubtarget().getInstrInfo();
444 TLI = MF->getSubtarget().getTargetLowering();
445 RegInfo = &MF->getRegInfo();
446 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
447 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
448 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
450 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
452 SplitCriticalSideEffectEdges(const_cast<Function &>(Fn));
455 FuncInfo->set(Fn, *MF, CurDAG);
457 if (UseMBPI && OptLevel != CodeGenOpt::None)
458 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
460 FuncInfo->BPI = nullptr;
462 SDB->init(GFI, *AA, LibInfo);
464 MF->setHasInlineAsm(false);
466 SelectAllBasicBlocks(Fn);
468 // If the first basic block in the function has live ins that need to be
469 // copied into vregs, emit the copies into the top of the block before
470 // emitting the code for the block.
471 MachineBasicBlock *EntryMBB = MF->begin();
472 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
473 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
475 DenseMap<unsigned, unsigned> LiveInMap;
476 if (!FuncInfo->ArgDbgValues.empty())
477 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
478 E = RegInfo->livein_end(); LI != E; ++LI)
480 LiveInMap.insert(std::make_pair(LI->first, LI->second));
482 // Insert DBG_VALUE instructions for function arguments to the entry block.
483 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
484 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
485 bool hasFI = MI->getOperand(0).isFI();
487 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
488 if (TargetRegisterInfo::isPhysicalRegister(Reg))
489 EntryMBB->insert(EntryMBB->begin(), MI);
491 MachineInstr *Def = RegInfo->getVRegDef(Reg);
493 MachineBasicBlock::iterator InsertPos = Def;
494 // FIXME: VR def may not be in entry block.
495 Def->getParent()->insert(std::next(InsertPos), MI);
497 DEBUG(dbgs() << "Dropping debug info for dead vreg"
498 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
501 // If Reg is live-in then update debug info to track its copy in a vreg.
502 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
503 if (LDI != LiveInMap.end()) {
504 assert(!hasFI && "There's no handling of frame pointer updating here yet "
506 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
507 MachineBasicBlock::iterator InsertPos = Def;
508 const MDNode *Variable = MI->getDebugVariable();
509 const MDNode *Expr = MI->getDebugExpression();
510 DebugLoc DL = MI->getDebugLoc();
511 bool IsIndirect = MI->isIndirectDebugValue();
512 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
513 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
514 "Expected inlined-at fields to agree");
515 // Def is never a terminator here, so it is ok to increment InsertPos.
516 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
517 IsIndirect, LDI->second, Offset, Variable, Expr);
519 // If this vreg is directly copied into an exported register then
520 // that COPY instructions also need DBG_VALUE, if it is the only
521 // user of LDI->second.
522 MachineInstr *CopyUseMI = nullptr;
523 for (MachineRegisterInfo::use_instr_iterator
524 UI = RegInfo->use_instr_begin(LDI->second),
525 E = RegInfo->use_instr_end(); UI != E; ) {
526 MachineInstr *UseMI = &*(UI++);
527 if (UseMI->isDebugValue()) continue;
528 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
529 CopyUseMI = UseMI; continue;
531 // Otherwise this is another use or second copy use.
532 CopyUseMI = nullptr; break;
535 // Use MI's debug location, which describes where Variable was
536 // declared, rather than whatever is attached to CopyUseMI.
537 MachineInstr *NewMI =
538 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
539 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
540 MachineBasicBlock::iterator Pos = CopyUseMI;
541 EntryMBB->insertAfter(Pos, NewMI);
546 // Determine if there are any calls in this machine function.
547 MachineFrameInfo *MFI = MF->getFrameInfo();
548 for (const auto &MBB : *MF) {
549 if (MFI->hasCalls() && MF->hasInlineAsm())
552 for (const auto &MI : MBB) {
553 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
554 if ((MCID.isCall() && !MCID.isReturn()) ||
555 MI.isStackAligningInlineAsm()) {
556 MFI->setHasCalls(true);
558 if (MI.isInlineAsm()) {
559 MF->setHasInlineAsm(true);
564 // Determine if there is a call to setjmp in the machine function.
565 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
567 // Replace forward-declared registers with the registers containing
568 // the desired value.
569 MachineRegisterInfo &MRI = MF->getRegInfo();
570 for (DenseMap<unsigned, unsigned>::iterator
571 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
573 unsigned From = I->first;
574 unsigned To = I->second;
575 // If To is also scheduled to be replaced, find what its ultimate
578 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
582 // Make sure the new register has a sufficiently constrained register class.
583 if (TargetRegisterInfo::isVirtualRegister(From) &&
584 TargetRegisterInfo::isVirtualRegister(To))
585 MRI.constrainRegClass(To, MRI.getRegClass(From));
589 // Replacing one register with another won't touch the kill flags.
590 // We need to conservatively clear the kill flags as a kill on the old
591 // register might dominate existing uses of the new register.
592 if (!MRI.use_empty(To))
593 MRI.clearKillFlags(From);
594 MRI.replaceRegWith(From, To);
597 // Freeze the set of reserved registers now that MachineFrameInfo has been
598 // set up. All the information required by getReservedRegs() should be
600 MRI.freezeReservedRegs(*MF);
602 // Release function-specific state. SDB and CurDAG are already cleared
606 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
607 DEBUG(MF->print(dbgs()));
612 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
613 BasicBlock::const_iterator End,
615 // Lower the instructions. If a call is emitted as a tail call, cease emitting
616 // nodes for this block.
617 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
620 // Make sure the root of the DAG is up-to-date.
621 CurDAG->setRoot(SDB->getControlRoot());
622 HadTailCall = SDB->HasTailCall;
625 // Final step, emit the lowered DAG as machine code.
629 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
630 SmallPtrSet<SDNode*, 128> VisitedNodes;
631 SmallVector<SDNode*, 128> Worklist;
633 Worklist.push_back(CurDAG->getRoot().getNode());
639 SDNode *N = Worklist.pop_back_val();
641 // If we've already seen this node, ignore it.
642 if (!VisitedNodes.insert(N).second)
645 // Otherwise, add all chain operands to the worklist.
646 for (const SDValue &Op : N->op_values())
647 if (Op.getValueType() == MVT::Other)
648 Worklist.push_back(Op.getNode());
650 // If this is a CopyToReg with a vreg dest, process it.
651 if (N->getOpcode() != ISD::CopyToReg)
654 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
655 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
658 // Ignore non-scalar or non-integer values.
659 SDValue Src = N->getOperand(2);
660 EVT SrcVT = Src.getValueType();
661 if (!SrcVT.isInteger() || SrcVT.isVector())
664 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
665 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
666 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
667 } while (!Worklist.empty());
670 void SelectionDAGISel::CodeGenAndEmitDAG() {
671 std::string GroupName;
672 if (TimePassesIsEnabled)
673 GroupName = "Instruction Selection and Scheduling";
674 std::string BlockName;
675 int BlockNumber = -1;
677 bool MatchFilterBB = false; (void)MatchFilterBB;
679 MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
680 FilterDAGBasicBlockName ==
681 FuncInfo->MBB->getBasicBlock()->getName().str());
684 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
685 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
689 BlockNumber = FuncInfo->MBB->getNumber();
691 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
693 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
694 << " '" << BlockName << "'\n"; CurDAG->dump());
696 if (ViewDAGCombine1 && MatchFilterBB)
697 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
699 // Run the DAG combiner in pre-legalize mode.
701 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
702 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
705 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
706 << " '" << BlockName << "'\n"; CurDAG->dump());
708 // Second step, hack on the DAG until it only uses operations and types that
709 // the target supports.
710 if (ViewLegalizeTypesDAGs && MatchFilterBB)
711 CurDAG->viewGraph("legalize-types input for " + BlockName);
715 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
716 Changed = CurDAG->LegalizeTypes();
719 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
720 << " '" << BlockName << "'\n"; CurDAG->dump());
722 CurDAG->NewNodesMustHaveLegalTypes = true;
725 if (ViewDAGCombineLT && MatchFilterBB)
726 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
728 // Run the DAG combiner in post-type-legalize mode.
730 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
731 TimePassesIsEnabled);
732 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
735 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
736 << " '" << BlockName << "'\n"; CurDAG->dump());
741 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
742 Changed = CurDAG->LegalizeVectors();
747 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
748 CurDAG->LegalizeTypes();
751 if (ViewDAGCombineLT && MatchFilterBB)
752 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
754 // Run the DAG combiner in post-type-legalize mode.
756 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
757 TimePassesIsEnabled);
758 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
761 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
762 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
765 if (ViewLegalizeDAGs && MatchFilterBB)
766 CurDAG->viewGraph("legalize input for " + BlockName);
769 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
773 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
774 << " '" << BlockName << "'\n"; CurDAG->dump());
776 if (ViewDAGCombine2 && MatchFilterBB)
777 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
779 // Run the DAG combiner in post-legalize mode.
781 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
782 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
785 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
786 << " '" << BlockName << "'\n"; CurDAG->dump());
788 if (OptLevel != CodeGenOpt::None)
789 ComputeLiveOutVRegInfo();
791 if (ViewISelDAGs && MatchFilterBB)
792 CurDAG->viewGraph("isel input for " + BlockName);
794 // Third, instruction select all of the operations to machine code, adding the
795 // code to the MachineBasicBlock.
797 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
798 DoInstructionSelection();
801 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
802 << " '" << BlockName << "'\n"; CurDAG->dump());
804 if (ViewSchedDAGs && MatchFilterBB)
805 CurDAG->viewGraph("scheduler input for " + BlockName);
807 // Schedule machine code.
808 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
810 NamedRegionTimer T("Instruction Scheduling", GroupName,
811 TimePassesIsEnabled);
812 Scheduler->Run(CurDAG, FuncInfo->MBB);
815 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
817 // Emit machine code to BB. This can change 'BB' to the last block being
819 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
821 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
823 // FuncInfo->InsertPt is passed by reference and set to the end of the
824 // scheduled instructions.
825 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
828 // If the block was split, make sure we update any references that are used to
829 // update PHI nodes later on.
830 if (FirstMBB != LastMBB)
831 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
833 // Free the scheduler state.
835 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
836 TimePassesIsEnabled);
840 // Free the SelectionDAG state, now that we're finished with it.
845 /// ISelUpdater - helper class to handle updates of the instruction selection
847 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
848 SelectionDAG::allnodes_iterator &ISelPosition;
850 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
851 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
853 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
854 /// deleted is the current ISelPosition node, update ISelPosition.
856 void NodeDeleted(SDNode *N, SDNode *E) override {
857 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
861 } // end anonymous namespace
863 void SelectionDAGISel::DoInstructionSelection() {
864 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
865 << FuncInfo->MBB->getNumber()
866 << " '" << FuncInfo->MBB->getName() << "'\n");
870 // Select target instructions for the DAG.
872 // Number all nodes with a topological order and set DAGSize.
873 DAGSize = CurDAG->AssignTopologicalOrder();
875 // Create a dummy node (which is not added to allnodes), that adds
876 // a reference to the root node, preventing it from being deleted,
877 // and tracking any changes of the root.
878 HandleSDNode Dummy(CurDAG->getRoot());
879 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
882 // Make sure that ISelPosition gets properly updated when nodes are deleted
883 // in calls made from this function.
884 ISelUpdater ISU(*CurDAG, ISelPosition);
886 // The AllNodes list is now topological-sorted. Visit the
887 // nodes by starting at the end of the list (the root of the
888 // graph) and preceding back toward the beginning (the entry
890 while (ISelPosition != CurDAG->allnodes_begin()) {
891 SDNode *Node = --ISelPosition;
892 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
893 // but there are currently some corner cases that it misses. Also, this
894 // makes it theoretically possible to disable the DAGCombiner.
895 if (Node->use_empty())
898 SDNode *ResNode = Select(Node);
900 // FIXME: This is pretty gross. 'Select' should be changed to not return
901 // anything at all and this code should be nuked with a tactical strike.
903 // If node should not be replaced, continue with the next one.
904 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
908 ReplaceUses(Node, ResNode);
911 // If after the replacement this node is not used any more,
912 // remove this dead node.
913 if (Node->use_empty()) // Don't delete EntryToken, etc.
914 CurDAG->RemoveDeadNode(Node);
917 CurDAG->setRoot(Dummy.getValue());
920 DEBUG(dbgs() << "===== Instruction selection ends:\n");
922 PostprocessISelDAG();
925 static bool hasExceptionPointerOrCodeUser(const CatchPadInst *CPI) {
926 for (const User *U : CPI->users()) {
927 if (const IntrinsicInst *EHPtrCall = dyn_cast<IntrinsicInst>(U)) {
928 Intrinsic::ID IID = EHPtrCall->getIntrinsicID();
929 if (IID == Intrinsic::eh_exceptionpointer ||
930 IID == Intrinsic::eh_exceptioncode)
937 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
938 /// do other setup for EH landing-pad blocks.
939 bool SelectionDAGISel::PrepareEHLandingPad() {
940 MachineBasicBlock *MBB = FuncInfo->MBB;
941 const BasicBlock *LLVMBB = MBB->getBasicBlock();
942 const TargetRegisterClass *PtrRC =
943 TLI->getRegClassFor(TLI->getPointerTy(CurDAG->getDataLayout()));
945 // Catchpads have one live-in register, which typically holds the exception
947 if (const auto *CPI = dyn_cast<CatchPadInst>(LLVMBB->getFirstNonPHI())) {
948 if (hasExceptionPointerOrCodeUser(CPI)) {
949 // Get or create the virtual register to hold the pointer or code. Mark
950 // the live in physreg and copy into the vreg.
951 MCPhysReg EHPhysReg = TLI->getExceptionPointerRegister();
952 assert(EHPhysReg && "target lacks exception pointer register");
953 MBB->addLiveIn(EHPhysReg);
954 unsigned VReg = FuncInfo->getCatchPadExceptionPointerVReg(CPI, PtrRC);
955 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(),
956 TII->get(TargetOpcode::COPY), VReg)
957 .addReg(EHPhysReg, RegState::Kill);
962 if (!LLVMBB->isLandingPad())
965 // Add a label to mark the beginning of the landing pad. Deletion of the
966 // landing pad can thus be detected via the MachineModuleInfo.
967 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
969 // Assign the call site to the landing pad's begin label.
970 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
972 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
973 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
976 // Mark exception register as live in.
977 if (unsigned Reg = TLI->getExceptionPointerRegister())
978 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
980 // Mark exception selector register as live in.
981 if (unsigned Reg = TLI->getExceptionSelectorRegister())
982 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
987 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
988 /// side-effect free and is either dead or folded into a generated instruction.
989 /// Return false if it needs to be emitted.
990 static bool isFoldedOrDeadInstruction(const Instruction *I,
991 FunctionLoweringInfo *FuncInfo) {
992 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
993 !isa<TerminatorInst>(I) && // Terminators aren't folded.
994 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
995 !I->isEHPad() && // EH pad instructions aren't folded.
996 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1000 // Collect per Instruction statistics for fast-isel misses. Only those
1001 // instructions that cause the bail are accounted for. It does not account for
1002 // instructions higher in the block. Thus, summing the per instructions stats
1003 // will not add up to what is reported by NumFastIselFailures.
1004 static void collectFailStats(const Instruction *I) {
1005 switch (I->getOpcode()) {
1006 default: assert (0 && "<Invalid operator> ");
1009 case Instruction::Ret: NumFastIselFailRet++; return;
1010 case Instruction::Br: NumFastIselFailBr++; return;
1011 case Instruction::Switch: NumFastIselFailSwitch++; return;
1012 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1013 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1014 case Instruction::Resume: NumFastIselFailResume++; return;
1015 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1017 // Standard binary operators...
1018 case Instruction::Add: NumFastIselFailAdd++; return;
1019 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1020 case Instruction::Sub: NumFastIselFailSub++; return;
1021 case Instruction::FSub: NumFastIselFailFSub++; return;
1022 case Instruction::Mul: NumFastIselFailMul++; return;
1023 case Instruction::FMul: NumFastIselFailFMul++; return;
1024 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1025 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1026 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1027 case Instruction::URem: NumFastIselFailURem++; return;
1028 case Instruction::SRem: NumFastIselFailSRem++; return;
1029 case Instruction::FRem: NumFastIselFailFRem++; return;
1031 // Logical operators...
1032 case Instruction::And: NumFastIselFailAnd++; return;
1033 case Instruction::Or: NumFastIselFailOr++; return;
1034 case Instruction::Xor: NumFastIselFailXor++; return;
1036 // Memory instructions...
1037 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1038 case Instruction::Load: NumFastIselFailLoad++; return;
1039 case Instruction::Store: NumFastIselFailStore++; return;
1040 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1041 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1042 case Instruction::Fence: NumFastIselFailFence++; return;
1043 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1045 // Convert instructions...
1046 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1047 case Instruction::ZExt: NumFastIselFailZExt++; return;
1048 case Instruction::SExt: NumFastIselFailSExt++; return;
1049 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1050 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1051 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1052 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1053 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1054 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1055 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1056 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1057 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1059 // Other instructions...
1060 case Instruction::ICmp: NumFastIselFailICmp++; return;
1061 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1062 case Instruction::PHI: NumFastIselFailPHI++; return;
1063 case Instruction::Select: NumFastIselFailSelect++; return;
1064 case Instruction::Call: {
1065 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1066 switch (Intrinsic->getIntrinsicID()) {
1068 NumFastIselFailIntrinsicCall++; return;
1069 case Intrinsic::sadd_with_overflow:
1070 NumFastIselFailSAddWithOverflow++; return;
1071 case Intrinsic::uadd_with_overflow:
1072 NumFastIselFailUAddWithOverflow++; return;
1073 case Intrinsic::ssub_with_overflow:
1074 NumFastIselFailSSubWithOverflow++; return;
1075 case Intrinsic::usub_with_overflow:
1076 NumFastIselFailUSubWithOverflow++; return;
1077 case Intrinsic::smul_with_overflow:
1078 NumFastIselFailSMulWithOverflow++; return;
1079 case Intrinsic::umul_with_overflow:
1080 NumFastIselFailUMulWithOverflow++; return;
1081 case Intrinsic::frameaddress:
1082 NumFastIselFailFrameaddress++; return;
1083 case Intrinsic::sqrt:
1084 NumFastIselFailSqrt++; return;
1085 case Intrinsic::experimental_stackmap:
1086 NumFastIselFailStackMap++; return;
1087 case Intrinsic::experimental_patchpoint_void: // fall-through
1088 case Intrinsic::experimental_patchpoint_i64:
1089 NumFastIselFailPatchPoint++; return;
1092 NumFastIselFailCall++;
1095 case Instruction::Shl: NumFastIselFailShl++; return;
1096 case Instruction::LShr: NumFastIselFailLShr++; return;
1097 case Instruction::AShr: NumFastIselFailAShr++; return;
1098 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1099 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1100 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1101 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1102 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1103 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1104 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1109 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1110 // Initialize the Fast-ISel state, if needed.
1111 FastISel *FastIS = nullptr;
1112 if (TM.Options.EnableFastISel)
1113 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1115 // Iterate over all basic blocks in the function.
1116 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1117 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1118 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1119 const BasicBlock *LLVMBB = *I;
1121 if (OptLevel != CodeGenOpt::None) {
1122 bool AllPredsVisited = true;
1123 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1125 if (!FuncInfo->VisitedBBs.count(*PI)) {
1126 AllPredsVisited = false;
1131 if (AllPredsVisited) {
1132 for (BasicBlock::const_iterator I = LLVMBB->begin();
1133 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1134 FuncInfo->ComputePHILiveOutRegInfo(PN);
1136 for (BasicBlock::const_iterator I = LLVMBB->begin();
1137 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1138 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1141 FuncInfo->VisitedBBs.insert(LLVMBB);
1144 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1145 BasicBlock::const_iterator const End = LLVMBB->end();
1146 BasicBlock::const_iterator BI = End;
1148 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1150 continue; // Some blocks like catchpads have no code or MBB.
1151 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1153 // Setup an EH landing-pad block.
1154 FuncInfo->ExceptionPointerVirtReg = 0;
1155 FuncInfo->ExceptionSelectorVirtReg = 0;
1156 if (LLVMBB->isEHPad())
1157 if (!PrepareEHLandingPad())
1160 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1162 FastIS->startNewBlock();
1164 // Emit code for any incoming arguments. This must happen before
1165 // beginning FastISel on the entry block.
1166 if (LLVMBB == &Fn.getEntryBlock()) {
1169 // Lower any arguments needed in this block if this is the entry block.
1170 if (!FastIS->lowerArguments()) {
1171 // Fast isel failed to lower these arguments
1172 ++NumFastIselFailLowerArguments;
1173 if (EnableFastISelAbort > 1)
1174 report_fatal_error("FastISel didn't lower all arguments");
1176 // Use SelectionDAG argument lowering
1178 CurDAG->setRoot(SDB->getControlRoot());
1180 CodeGenAndEmitDAG();
1183 // If we inserted any instructions at the beginning, make a note of
1184 // where they are, so we can be sure to emit subsequent instructions
1186 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1187 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1189 FastIS->setLastLocalValue(nullptr);
1192 unsigned NumFastIselRemaining = std::distance(Begin, End);
1193 // Do FastISel on as many instructions as possible.
1194 for (; BI != Begin; --BI) {
1195 const Instruction *Inst = std::prev(BI);
1197 // If we no longer require this instruction, skip it.
1198 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1199 --NumFastIselRemaining;
1203 // Bottom-up: reset the insert pos at the top, after any local-value
1205 FastIS->recomputeInsertPt();
1207 // Try to select the instruction with FastISel.
1208 if (FastIS->selectInstruction(Inst)) {
1209 --NumFastIselRemaining;
1210 ++NumFastIselSuccess;
1211 // If fast isel succeeded, skip over all the folded instructions, and
1212 // then see if there is a load right before the selected instructions.
1213 // Try to fold the load if so.
1214 const Instruction *BeforeInst = Inst;
1215 while (BeforeInst != Begin) {
1216 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1217 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1220 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1221 BeforeInst->hasOneUse() &&
1222 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1223 // If we succeeded, don't re-select the load.
1224 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1225 --NumFastIselRemaining;
1226 ++NumFastIselSuccess;
1232 if (EnableFastISelVerbose2)
1233 collectFailStats(Inst);
1236 // Then handle certain instructions as single-LLVM-Instruction blocks.
1237 if (isa<CallInst>(Inst)) {
1239 if (EnableFastISelVerbose || EnableFastISelAbort) {
1240 dbgs() << "FastISel missed call: ";
1243 if (EnableFastISelAbort > 2)
1244 // FastISel selector couldn't handle something and bailed.
1245 // For the purpose of debugging, just abort.
1246 report_fatal_error("FastISel didn't select the entire block");
1248 if (!Inst->getType()->isVoidTy() && !Inst->getType()->isTokenTy() &&
1249 !Inst->use_empty()) {
1250 unsigned &R = FuncInfo->ValueMap[Inst];
1252 R = FuncInfo->CreateRegs(Inst->getType());
1255 bool HadTailCall = false;
1256 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1257 SelectBasicBlock(Inst, BI, HadTailCall);
1259 // If the call was emitted as a tail call, we're done with the block.
1260 // We also need to delete any previously emitted instructions.
1262 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1267 // Recompute NumFastIselRemaining as Selection DAG instruction
1268 // selection may have handled the call, input args, etc.
1269 unsigned RemainingNow = std::distance(Begin, BI);
1270 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1271 NumFastIselRemaining = RemainingNow;
1275 bool ShouldAbort = EnableFastISelAbort;
1276 if (EnableFastISelVerbose || EnableFastISelAbort) {
1277 if (isa<TerminatorInst>(Inst)) {
1278 // Use a different message for terminator misses.
1279 dbgs() << "FastISel missed terminator: ";
1280 // Don't abort unless for terminator unless the level is really high
1281 ShouldAbort = (EnableFastISelAbort > 2);
1283 dbgs() << "FastISel miss: ";
1288 // FastISel selector couldn't handle something and bailed.
1289 // For the purpose of debugging, just abort.
1290 report_fatal_error("FastISel didn't select the entire block");
1292 NumFastIselFailures += NumFastIselRemaining;
1296 FastIS->recomputeInsertPt();
1298 // Lower any arguments needed in this block if this is the entry block.
1299 if (LLVMBB == &Fn.getEntryBlock()) {
1308 ++NumFastIselBlocks;
1311 // Run SelectionDAG instruction selection on the remainder of the block
1312 // not handled by FastISel. If FastISel is not run, this is the entire
1315 SelectBasicBlock(Begin, BI, HadTailCall);
1319 FuncInfo->PHINodesToUpdate.clear();
1323 SDB->clearDanglingDebugInfo();
1324 SDB->SPDescriptor.resetPerFunctionState();
1327 /// Given that the input MI is before a partial terminator sequence TSeq, return
1328 /// true if M + TSeq also a partial terminator sequence.
1330 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1331 /// lowering copy vregs into physical registers, which are then passed into
1332 /// terminator instructors so we can satisfy ABI constraints. A partial
1333 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1334 /// may be the whole terminator sequence).
1335 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1336 // If we do not have a copy or an implicit def, we return true if and only if
1337 // MI is a debug value.
1338 if (!MI->isCopy() && !MI->isImplicitDef())
1339 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1340 // physical registers if there is debug info associated with the terminator
1341 // of our mbb. We want to include said debug info in our terminator
1342 // sequence, so we return true in that case.
1343 return MI->isDebugValue();
1345 // We have left the terminator sequence if we are not doing one of the
1348 // 1. Copying a vreg into a physical register.
1349 // 2. Copying a vreg into a vreg.
1350 // 3. Defining a register via an implicit def.
1352 // OPI should always be a register definition...
1353 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1354 if (!OPI->isReg() || !OPI->isDef())
1357 // Defining any register via an implicit def is always ok.
1358 if (MI->isImplicitDef())
1361 // Grab the copy source...
1362 MachineInstr::const_mop_iterator OPI2 = OPI;
1364 assert(OPI2 != MI->operands_end()
1365 && "Should have a copy implying we should have 2 arguments.");
1367 // Make sure that the copy dest is not a vreg when the copy source is a
1368 // physical register.
1369 if (!OPI2->isReg() ||
1370 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1371 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1377 /// Find the split point at which to splice the end of BB into its success stack
1378 /// protector check machine basic block.
1380 /// On many platforms, due to ABI constraints, terminators, even before register
1381 /// allocation, use physical registers. This creates an issue for us since
1382 /// physical registers at this point can not travel across basic
1383 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1384 /// when they enter functions and moves them through a sequence of copies back
1385 /// into the physical registers right before the terminator creating a
1386 /// ``Terminator Sequence''. This function is searching for the beginning of the
1387 /// terminator sequence so that we can ensure that we splice off not just the
1388 /// terminator, but additionally the copies that move the vregs into the
1389 /// physical registers.
1390 static MachineBasicBlock::iterator
1391 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1392 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1394 if (SplitPoint == BB->begin())
1397 MachineBasicBlock::iterator Start = BB->begin();
1398 MachineBasicBlock::iterator Previous = SplitPoint;
1401 while (MIIsInTerminatorSequence(Previous)) {
1402 SplitPoint = Previous;
1403 if (Previous == Start)
1412 SelectionDAGISel::FinishBasicBlock() {
1414 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1415 << FuncInfo->PHINodesToUpdate.size() << "\n";
1416 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1417 dbgs() << "Node " << i << " : ("
1418 << FuncInfo->PHINodesToUpdate[i].first
1419 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1421 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1422 // PHI nodes in successors.
1423 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1424 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1425 assert(PHI->isPHI() &&
1426 "This is not a machine PHI node that we are updating!");
1427 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1429 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1432 // Handle stack protector.
1433 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1434 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1435 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1437 // Find the split point to split the parent mbb. At the same time copy all
1438 // physical registers used in the tail of parent mbb into virtual registers
1439 // before the split point and back into physical registers after the split
1440 // point. This prevents us needing to deal with Live-ins and many other
1441 // register allocation issues caused by us splitting the parent mbb. The
1442 // register allocator will clean up said virtual copies later on.
1443 MachineBasicBlock::iterator SplitPoint =
1444 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1446 // Splice the terminator of ParentMBB into SuccessMBB.
1447 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1451 // Add compare/jump on neq/jump to the parent BB.
1452 FuncInfo->MBB = ParentMBB;
1453 FuncInfo->InsertPt = ParentMBB->end();
1454 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1455 CurDAG->setRoot(SDB->getRoot());
1457 CodeGenAndEmitDAG();
1459 // CodeGen Failure MBB if we have not codegened it yet.
1460 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1461 if (!FailureMBB->size()) {
1462 FuncInfo->MBB = FailureMBB;
1463 FuncInfo->InsertPt = FailureMBB->end();
1464 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1465 CurDAG->setRoot(SDB->getRoot());
1467 CodeGenAndEmitDAG();
1470 // Clear the Per-BB State.
1471 SDB->SPDescriptor.resetPerBBState();
1474 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1475 // Lower header first, if it wasn't already lowered
1476 if (!SDB->BitTestCases[i].Emitted) {
1477 // Set the current basic block to the mbb we wish to insert the code into
1478 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1479 FuncInfo->InsertPt = FuncInfo->MBB->end();
1481 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1482 CurDAG->setRoot(SDB->getRoot());
1484 CodeGenAndEmitDAG();
1487 uint32_t UnhandledWeight = SDB->BitTestCases[i].Weight;
1489 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1490 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1491 // Set the current basic block to the mbb we wish to insert the code into
1492 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1493 FuncInfo->InsertPt = FuncInfo->MBB->end();
1496 // If all cases cover a contiguous range, it is not necessary to jump to
1497 // the default block after the last bit test fails. This is because the
1498 // range check during bit test header creation has guaranteed that every
1499 // case here doesn't go outside the range.
1500 MachineBasicBlock *NextMBB;
1501 if (SDB->BitTestCases[i].ContiguousRange && j + 2 == ej)
1502 NextMBB = SDB->BitTestCases[i].Cases[j + 1].TargetBB;
1503 else if (j + 1 != ej)
1504 NextMBB = SDB->BitTestCases[i].Cases[j + 1].ThisBB;
1506 NextMBB = SDB->BitTestCases[i].Default;
1508 SDB->visitBitTestCase(SDB->BitTestCases[i],
1511 SDB->BitTestCases[i].Reg,
1512 SDB->BitTestCases[i].Cases[j],
1515 CurDAG->setRoot(SDB->getRoot());
1517 CodeGenAndEmitDAG();
1519 if (SDB->BitTestCases[i].ContiguousRange && j + 2 == ej)
1524 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1526 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1527 MachineBasicBlock *PHIBB = PHI->getParent();
1528 assert(PHI->isPHI() &&
1529 "This is not a machine PHI node that we are updating!");
1530 // This is "default" BB. We have two jumps to it. From "header" BB and
1531 // from last "case" BB.
1532 if (PHIBB == SDB->BitTestCases[i].Default)
1533 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1534 .addMBB(SDB->BitTestCases[i].Parent)
1535 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1536 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1537 // One of "cases" BB.
1538 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1540 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1541 if (cBB->isSuccessor(PHIBB))
1542 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1546 SDB->BitTestCases.clear();
1548 // If the JumpTable record is filled in, then we need to emit a jump table.
1549 // Updating the PHI nodes is tricky in this case, since we need to determine
1550 // whether the PHI is a successor of the range check MBB or the jump table MBB
1551 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1552 // Lower header first, if it wasn't already lowered
1553 if (!SDB->JTCases[i].first.Emitted) {
1554 // Set the current basic block to the mbb we wish to insert the code into
1555 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1556 FuncInfo->InsertPt = FuncInfo->MBB->end();
1558 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1560 CurDAG->setRoot(SDB->getRoot());
1562 CodeGenAndEmitDAG();
1565 // Set the current basic block to the mbb we wish to insert the code into
1566 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1567 FuncInfo->InsertPt = FuncInfo->MBB->end();
1569 SDB->visitJumpTable(SDB->JTCases[i].second);
1570 CurDAG->setRoot(SDB->getRoot());
1572 CodeGenAndEmitDAG();
1575 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1577 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1578 MachineBasicBlock *PHIBB = PHI->getParent();
1579 assert(PHI->isPHI() &&
1580 "This is not a machine PHI node that we are updating!");
1581 // "default" BB. We can go there only from header BB.
1582 if (PHIBB == SDB->JTCases[i].second.Default)
1583 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1584 .addMBB(SDB->JTCases[i].first.HeaderBB);
1585 // JT BB. Just iterate over successors here
1586 if (FuncInfo->MBB->isSuccessor(PHIBB))
1587 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1590 SDB->JTCases.clear();
1592 // If we generated any switch lowering information, build and codegen any
1593 // additional DAGs necessary.
1594 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1595 // Set the current basic block to the mbb we wish to insert the code into
1596 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1597 FuncInfo->InsertPt = FuncInfo->MBB->end();
1599 // Determine the unique successors.
1600 SmallVector<MachineBasicBlock *, 2> Succs;
1601 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1602 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1603 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1605 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1606 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1607 CurDAG->setRoot(SDB->getRoot());
1609 CodeGenAndEmitDAG();
1611 // Remember the last block, now that any splitting is done, for use in
1612 // populating PHI nodes in successors.
1613 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1615 // Handle any PHI nodes in successors of this chunk, as if we were coming
1616 // from the original BB before switch expansion. Note that PHI nodes can
1617 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1618 // handle them the right number of times.
1619 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1620 FuncInfo->MBB = Succs[i];
1621 FuncInfo->InsertPt = FuncInfo->MBB->end();
1622 // FuncInfo->MBB may have been removed from the CFG if a branch was
1624 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1625 for (MachineBasicBlock::iterator
1626 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1627 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1628 MachineInstrBuilder PHI(*MF, MBBI);
1629 // This value for this PHI node is recorded in PHINodesToUpdate.
1630 for (unsigned pn = 0; ; ++pn) {
1631 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1632 "Didn't find PHI entry!");
1633 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1634 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1642 SDB->SwitchCases.clear();
1646 /// Create the scheduler. If a specific scheduler was specified
1647 /// via the SchedulerRegistry, use it, otherwise select the
1648 /// one preferred by the target.
1650 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1651 return ISHeuristic(this, OptLevel);
1654 //===----------------------------------------------------------------------===//
1655 // Helper functions used by the generated instruction selector.
1656 //===----------------------------------------------------------------------===//
1657 // Calls to these methods are generated by tblgen.
1659 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1660 /// the dag combiner simplified the 255, we still want to match. RHS is the
1661 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1662 /// specified in the .td file (e.g. 255).
1663 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1664 int64_t DesiredMaskS) const {
1665 const APInt &ActualMask = RHS->getAPIntValue();
1666 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1668 // If the actual mask exactly matches, success!
1669 if (ActualMask == DesiredMask)
1672 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1673 if (ActualMask.intersects(~DesiredMask))
1676 // Otherwise, the DAG Combiner may have proven that the value coming in is
1677 // either already zero or is not demanded. Check for known zero input bits.
1678 APInt NeededMask = DesiredMask & ~ActualMask;
1679 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1682 // TODO: check to see if missing bits are just not demanded.
1684 // Otherwise, this pattern doesn't match.
1688 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1689 /// the dag combiner simplified the 255, we still want to match. RHS is the
1690 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1691 /// specified in the .td file (e.g. 255).
1692 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1693 int64_t DesiredMaskS) const {
1694 const APInt &ActualMask = RHS->getAPIntValue();
1695 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1697 // If the actual mask exactly matches, success!
1698 if (ActualMask == DesiredMask)
1701 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1702 if (ActualMask.intersects(~DesiredMask))
1705 // Otherwise, the DAG Combiner may have proven that the value coming in is
1706 // either already zero or is not demanded. Check for known zero input bits.
1707 APInt NeededMask = DesiredMask & ~ActualMask;
1709 APInt KnownZero, KnownOne;
1710 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1712 // If all the missing bits in the or are already known to be set, match!
1713 if ((NeededMask & KnownOne) == NeededMask)
1716 // TODO: check to see if missing bits are just not demanded.
1718 // Otherwise, this pattern doesn't match.
1722 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1723 /// by tblgen. Others should not call it.
1724 void SelectionDAGISel::
1725 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SDLoc DL) {
1726 std::vector<SDValue> InOps;
1727 std::swap(InOps, Ops);
1729 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1730 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1731 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1732 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1734 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1735 if (InOps[e-1].getValueType() == MVT::Glue)
1736 --e; // Don't process a glue operand if it is here.
1739 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1740 if (!InlineAsm::isMemKind(Flags)) {
1741 // Just skip over this operand, copying the operands verbatim.
1742 Ops.insert(Ops.end(), InOps.begin()+i,
1743 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1744 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1746 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1747 "Memory operand with multiple values?");
1749 unsigned TiedToOperand;
1750 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) {
1751 // We need the constraint ID from the operand this is tied to.
1752 unsigned CurOp = InlineAsm::Op_FirstOperand;
1753 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1754 for (; TiedToOperand; --TiedToOperand) {
1755 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
1756 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1760 // Otherwise, this is a memory operand. Ask the target to select it.
1761 std::vector<SDValue> SelOps;
1762 if (SelectInlineAsmMemoryOperand(InOps[i+1],
1763 InlineAsm::getMemoryConstraintID(Flags),
1765 report_fatal_error("Could not match memory address. Inline asm"
1768 // Add this to the output node.
1770 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1771 Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32));
1772 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1777 // Add the glue input back if present.
1778 if (e != InOps.size())
1779 Ops.push_back(InOps.back());
1782 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1785 static SDNode *findGlueUse(SDNode *N) {
1786 unsigned FlagResNo = N->getNumValues()-1;
1787 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1788 SDUse &Use = I.getUse();
1789 if (Use.getResNo() == FlagResNo)
1790 return Use.getUser();
1795 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1796 /// This function recursively traverses up the operand chain, ignoring
1798 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1799 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1800 bool IgnoreChains) {
1801 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1802 // greater than all of its (recursive) operands. If we scan to a point where
1803 // 'use' is smaller than the node we're scanning for, then we know we will
1806 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1807 // happen because we scan down to newly selected nodes in the case of glue
1809 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1812 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1813 // won't fail if we scan it again.
1814 if (!Visited.insert(Use).second)
1817 for (const SDValue &Op : Use->op_values()) {
1818 // Ignore chain uses, they are validated by HandleMergeInputChains.
1819 if (Op.getValueType() == MVT::Other && IgnoreChains)
1822 SDNode *N = Op.getNode();
1824 if (Use == ImmedUse || Use == Root)
1825 continue; // We are not looking for immediate use.
1830 // Traverse up the operand chain.
1831 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1837 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1838 /// operand node N of U during instruction selection that starts at Root.
1839 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1840 SDNode *Root) const {
1841 if (OptLevel == CodeGenOpt::None) return false;
1842 return N.hasOneUse();
1845 /// IsLegalToFold - Returns true if the specific operand node N of
1846 /// U can be folded during instruction selection that starts at Root.
1847 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1848 CodeGenOpt::Level OptLevel,
1849 bool IgnoreChains) {
1850 if (OptLevel == CodeGenOpt::None) return false;
1852 // If Root use can somehow reach N through a path that that doesn't contain
1853 // U then folding N would create a cycle. e.g. In the following
1854 // diagram, Root can reach N through X. If N is folded into into Root, then
1855 // X is both a predecessor and a successor of U.
1866 // * indicates nodes to be folded together.
1868 // If Root produces glue, then it gets (even more) interesting. Since it
1869 // will be "glued" together with its glue use in the scheduler, we need to
1870 // check if it might reach N.
1889 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1890 // (call it Fold), then X is a predecessor of GU and a successor of
1891 // Fold. But since Fold and GU are glued together, this will create
1892 // a cycle in the scheduling graph.
1894 // If the node has glue, walk down the graph to the "lowest" node in the
1896 EVT VT = Root->getValueType(Root->getNumValues()-1);
1897 while (VT == MVT::Glue) {
1898 SDNode *GU = findGlueUse(Root);
1902 VT = Root->getValueType(Root->getNumValues()-1);
1904 // If our query node has a glue result with a use, we've walked up it. If
1905 // the user (which has already been selected) has a chain or indirectly uses
1906 // the chain, our WalkChainUsers predicate will not consider it. Because of
1907 // this, we cannot ignore chains in this predicate.
1908 IgnoreChains = false;
1912 SmallPtrSet<SDNode*, 16> Visited;
1913 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1916 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1919 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1920 SelectInlineAsmMemoryOperands(Ops, DL);
1922 const EVT VTs[] = {MVT::Other, MVT::Glue};
1923 SDValue New = CurDAG->getNode(ISD::INLINEASM, DL, VTs, Ops);
1925 return New.getNode();
1929 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1931 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1932 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1934 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0),
1936 SDValue New = CurDAG->getCopyFromReg(
1937 Op->getOperand(0), dl, Reg, Op->getValueType(0));
1939 return New.getNode();
1943 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1945 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1946 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1947 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1948 Op->getOperand(2).getValueType(),
1950 SDValue New = CurDAG->getCopyToReg(
1951 Op->getOperand(0), dl, Reg, Op->getOperand(2));
1953 return New.getNode();
1958 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1959 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1962 /// GetVBR - decode a vbr encoding whose top bit is set.
1963 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline uint64_t
1964 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1965 assert(Val >= 128 && "Not a VBR");
1966 Val &= 127; // Remove first vbr bit.
1971 NextBits = MatcherTable[Idx++];
1972 Val |= (NextBits&127) << Shift;
1974 } while (NextBits & 128);
1980 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1981 /// interior glue and chain results to use the new glue and chain results.
1982 void SelectionDAGISel::
1983 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1984 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1986 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1987 bool isMorphNodeTo) {
1988 SmallVector<SDNode*, 4> NowDeadNodes;
1990 // Now that all the normal results are replaced, we replace the chain and
1991 // glue results if present.
1992 if (!ChainNodesMatched.empty()) {
1993 assert(InputChain.getNode() &&
1994 "Matched input chains but didn't produce a chain");
1995 // Loop over all of the nodes we matched that produced a chain result.
1996 // Replace all the chain results with the final chain we ended up with.
1997 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1998 SDNode *ChainNode = ChainNodesMatched[i];
2000 // If this node was already deleted, don't look at it.
2001 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2004 // Don't replace the results of the root node if we're doing a
2006 if (ChainNode == NodeToMatch && isMorphNodeTo)
2009 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2010 if (ChainVal.getValueType() == MVT::Glue)
2011 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2012 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2013 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2015 // If the node became dead and we haven't already seen it, delete it.
2016 if (ChainNode->use_empty() &&
2017 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2018 NowDeadNodes.push_back(ChainNode);
2022 // If the result produces glue, update any glue results in the matched
2023 // pattern with the glue result.
2024 if (InputGlue.getNode()) {
2025 // Handle any interior nodes explicitly marked.
2026 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2027 SDNode *FRN = GlueResultNodesMatched[i];
2029 // If this node was already deleted, don't look at it.
2030 if (FRN->getOpcode() == ISD::DELETED_NODE)
2033 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2034 "Doesn't have a glue result");
2035 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2038 // If the node became dead and we haven't already seen it, delete it.
2039 if (FRN->use_empty() &&
2040 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2041 NowDeadNodes.push_back(FRN);
2045 if (!NowDeadNodes.empty())
2046 CurDAG->RemoveDeadNodes(NowDeadNodes);
2048 DEBUG(dbgs() << "ISEL: Match complete!\n");
2054 CR_LeadsToInteriorNode
2057 /// WalkChainUsers - Walk down the users of the specified chained node that is
2058 /// part of the pattern we're matching, looking at all of the users we find.
2059 /// This determines whether something is an interior node, whether we have a
2060 /// non-pattern node in between two pattern nodes (which prevent folding because
2061 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2062 /// between pattern nodes (in which case the TF becomes part of the pattern).
2064 /// The walk we do here is guaranteed to be small because we quickly get down to
2065 /// already selected nodes "below" us.
2067 WalkChainUsers(const SDNode *ChainedNode,
2068 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2069 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2070 ChainResult Result = CR_Simple;
2072 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2073 E = ChainedNode->use_end(); UI != E; ++UI) {
2074 // Make sure the use is of the chain, not some other value we produce.
2075 if (UI.getUse().getValueType() != MVT::Other) continue;
2079 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2082 // If we see an already-selected machine node, then we've gone beyond the
2083 // pattern that we're selecting down into the already selected chunk of the
2085 unsigned UserOpcode = User->getOpcode();
2086 if (User->isMachineOpcode() ||
2087 UserOpcode == ISD::CopyToReg ||
2088 UserOpcode == ISD::CopyFromReg ||
2089 UserOpcode == ISD::INLINEASM ||
2090 UserOpcode == ISD::EH_LABEL ||
2091 UserOpcode == ISD::LIFETIME_START ||
2092 UserOpcode == ISD::LIFETIME_END) {
2093 // If their node ID got reset to -1 then they've already been selected.
2094 // Treat them like a MachineOpcode.
2095 if (User->getNodeId() == -1)
2099 // If we have a TokenFactor, we handle it specially.
2100 if (User->getOpcode() != ISD::TokenFactor) {
2101 // If the node isn't a token factor and isn't part of our pattern, then it
2102 // must be a random chained node in between two nodes we're selecting.
2103 // This happens when we have something like:
2108 // Because we structurally match the load/store as a read/modify/write,
2109 // but the call is chained between them. We cannot fold in this case
2110 // because it would induce a cycle in the graph.
2111 if (!std::count(ChainedNodesInPattern.begin(),
2112 ChainedNodesInPattern.end(), User))
2113 return CR_InducesCycle;
2115 // Otherwise we found a node that is part of our pattern. For example in:
2119 // This would happen when we're scanning down from the load and see the
2120 // store as a user. Record that there is a use of ChainedNode that is
2121 // part of the pattern and keep scanning uses.
2122 Result = CR_LeadsToInteriorNode;
2123 InteriorChainedNodes.push_back(User);
2127 // If we found a TokenFactor, there are two cases to consider: first if the
2128 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2129 // uses of the TF are in our pattern) we just want to ignore it. Second,
2130 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2136 // | \ DAG's like cheese
2139 // [TokenFactor] [Op]
2146 // In this case, the TokenFactor becomes part of our match and we rewrite it
2147 // as a new TokenFactor.
2149 // To distinguish these two cases, do a recursive walk down the uses.
2150 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2152 // If the uses of the TokenFactor are just already-selected nodes, ignore
2153 // it, it is "below" our pattern.
2155 case CR_InducesCycle:
2156 // If the uses of the TokenFactor lead to nodes that are not part of our
2157 // pattern that are not selected, folding would turn this into a cycle,
2159 return CR_InducesCycle;
2160 case CR_LeadsToInteriorNode:
2161 break; // Otherwise, keep processing.
2164 // Okay, we know we're in the interesting interior case. The TokenFactor
2165 // is now going to be considered part of the pattern so that we rewrite its
2166 // uses (it may have uses that are not part of the pattern) with the
2167 // ultimate chain result of the generated code. We will also add its chain
2168 // inputs as inputs to the ultimate TokenFactor we create.
2169 Result = CR_LeadsToInteriorNode;
2170 ChainedNodesInPattern.push_back(User);
2171 InteriorChainedNodes.push_back(User);
2178 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2179 /// operation for when the pattern matched at least one node with a chains. The
2180 /// input vector contains a list of all of the chained nodes that we match. We
2181 /// must determine if this is a valid thing to cover (i.e. matching it won't
2182 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2183 /// be used as the input node chain for the generated nodes.
2185 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2186 SelectionDAG *CurDAG) {
2187 // Walk all of the chained nodes we've matched, recursively scanning down the
2188 // users of the chain result. This adds any TokenFactor nodes that are caught
2189 // in between chained nodes to the chained and interior nodes list.
2190 SmallVector<SDNode*, 3> InteriorChainedNodes;
2191 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2192 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2193 InteriorChainedNodes) == CR_InducesCycle)
2194 return SDValue(); // Would induce a cycle.
2197 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2198 // that we are interested in. Form our input TokenFactor node.
2199 SmallVector<SDValue, 3> InputChains;
2200 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2201 // Add the input chain of this node to the InputChains list (which will be
2202 // the operands of the generated TokenFactor) if it's not an interior node.
2203 SDNode *N = ChainNodesMatched[i];
2204 if (N->getOpcode() != ISD::TokenFactor) {
2205 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2208 // Otherwise, add the input chain.
2209 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2210 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2211 InputChains.push_back(InChain);
2215 // If we have a token factor, we want to add all inputs of the token factor
2216 // that are not part of the pattern we're matching.
2217 for (const SDValue &Op : N->op_values()) {
2218 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2220 InputChains.push_back(Op);
2224 if (InputChains.size() == 1)
2225 return InputChains[0];
2226 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2227 MVT::Other, InputChains);
2230 /// MorphNode - Handle morphing a node in place for the selector.
2231 SDNode *SelectionDAGISel::
2232 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2233 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2234 // It is possible we're using MorphNodeTo to replace a node with no
2235 // normal results with one that has a normal result (or we could be
2236 // adding a chain) and the input could have glue and chains as well.
2237 // In this case we need to shift the operands down.
2238 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2239 // than the old isel though.
2240 int OldGlueResultNo = -1, OldChainResultNo = -1;
2242 unsigned NTMNumResults = Node->getNumValues();
2243 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2244 OldGlueResultNo = NTMNumResults-1;
2245 if (NTMNumResults != 1 &&
2246 Node->getValueType(NTMNumResults-2) == MVT::Other)
2247 OldChainResultNo = NTMNumResults-2;
2248 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2249 OldChainResultNo = NTMNumResults-1;
2251 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2252 // that this deletes operands of the old node that become dead.
2253 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2255 // MorphNodeTo can operate in two ways: if an existing node with the
2256 // specified operands exists, it can just return it. Otherwise, it
2257 // updates the node in place to have the requested operands.
2259 // If we updated the node in place, reset the node ID. To the isel,
2260 // this should be just like a newly allocated machine node.
2264 unsigned ResNumResults = Res->getNumValues();
2265 // Move the glue if needed.
2266 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2267 (unsigned)OldGlueResultNo != ResNumResults-1)
2268 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2269 SDValue(Res, ResNumResults-1));
2271 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2274 // Move the chain reference if needed.
2275 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2276 (unsigned)OldChainResultNo != ResNumResults-1)
2277 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2278 SDValue(Res, ResNumResults-1));
2280 // Otherwise, no replacement happened because the node already exists. Replace
2281 // Uses of the old node with the new one.
2283 CurDAG->ReplaceAllUsesWith(Node, Res);
2288 /// CheckSame - Implements OP_CheckSame.
2289 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2290 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2292 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2293 // Accept if it is exactly the same as a previously recorded node.
2294 unsigned RecNo = MatcherTable[MatcherIndex++];
2295 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2296 return N == RecordedNodes[RecNo].first;
2299 /// CheckChildSame - Implements OP_CheckChildXSame.
2300 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2301 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2303 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2305 if (ChildNo >= N.getNumOperands())
2306 return false; // Match fails if out of range child #.
2307 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2311 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2312 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2313 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2314 const SelectionDAGISel &SDISel) {
2315 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2318 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2319 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2320 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2321 const SelectionDAGISel &SDISel, SDNode *N) {
2322 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2325 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2326 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2328 uint16_t Opc = MatcherTable[MatcherIndex++];
2329 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2330 return N->getOpcode() == Opc;
2333 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2334 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N,
2335 const TargetLowering *TLI, const DataLayout &DL) {
2336 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2337 if (N.getValueType() == VT) return true;
2339 // Handle the case when VT is iPTR.
2340 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(DL);
2343 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2344 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2345 SDValue N, const TargetLowering *TLI, const DataLayout &DL,
2347 if (ChildNo >= N.getNumOperands())
2348 return false; // Match fails if out of range child #.
2349 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI,
2353 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2354 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2356 return cast<CondCodeSDNode>(N)->get() ==
2357 (ISD::CondCode)MatcherTable[MatcherIndex++];
2360 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2361 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2362 SDValue N, const TargetLowering *TLI, const DataLayout &DL) {
2363 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2364 if (cast<VTSDNode>(N)->getVT() == VT)
2367 // Handle the case when VT is iPTR.
2368 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL);
2371 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2372 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2374 int64_t Val = MatcherTable[MatcherIndex++];
2376 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2378 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2379 return C && C->getSExtValue() == Val;
2382 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2383 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2384 SDValue N, unsigned ChildNo) {
2385 if (ChildNo >= N.getNumOperands())
2386 return false; // Match fails if out of range child #.
2387 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2390 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2391 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2392 SDValue N, const SelectionDAGISel &SDISel) {
2393 int64_t Val = MatcherTable[MatcherIndex++];
2395 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2397 if (N->getOpcode() != ISD::AND) return false;
2399 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2400 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2403 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2404 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2405 SDValue N, const SelectionDAGISel &SDISel) {
2406 int64_t Val = MatcherTable[MatcherIndex++];
2408 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2410 if (N->getOpcode() != ISD::OR) return false;
2412 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2413 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2416 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2417 /// scope, evaluate the current node. If the current predicate is known to
2418 /// fail, set Result=true and return anything. If the current predicate is
2419 /// known to pass, set Result=false and return the MatcherIndex to continue
2420 /// with. If the current predicate is unknown, set Result=false and return the
2421 /// MatcherIndex to continue with.
2422 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2423 unsigned Index, SDValue N,
2425 const SelectionDAGISel &SDISel,
2426 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2427 switch (Table[Index++]) {
2430 return Index-1; // Could not evaluate this predicate.
2431 case SelectionDAGISel::OPC_CheckSame:
2432 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2434 case SelectionDAGISel::OPC_CheckChild0Same:
2435 case SelectionDAGISel::OPC_CheckChild1Same:
2436 case SelectionDAGISel::OPC_CheckChild2Same:
2437 case SelectionDAGISel::OPC_CheckChild3Same:
2438 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2439 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2441 case SelectionDAGISel::OPC_CheckPatternPredicate:
2442 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2444 case SelectionDAGISel::OPC_CheckPredicate:
2445 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2447 case SelectionDAGISel::OPC_CheckOpcode:
2448 Result = !::CheckOpcode(Table, Index, N.getNode());
2450 case SelectionDAGISel::OPC_CheckType:
2451 Result = !::CheckType(Table, Index, N, SDISel.TLI,
2452 SDISel.CurDAG->getDataLayout());
2454 case SelectionDAGISel::OPC_CheckChild0Type:
2455 case SelectionDAGISel::OPC_CheckChild1Type:
2456 case SelectionDAGISel::OPC_CheckChild2Type:
2457 case SelectionDAGISel::OPC_CheckChild3Type:
2458 case SelectionDAGISel::OPC_CheckChild4Type:
2459 case SelectionDAGISel::OPC_CheckChild5Type:
2460 case SelectionDAGISel::OPC_CheckChild6Type:
2461 case SelectionDAGISel::OPC_CheckChild7Type:
2462 Result = !::CheckChildType(
2463 Table, Index, N, SDISel.TLI, SDISel.CurDAG->getDataLayout(),
2464 Table[Index - 1] - SelectionDAGISel::OPC_CheckChild0Type);
2466 case SelectionDAGISel::OPC_CheckCondCode:
2467 Result = !::CheckCondCode(Table, Index, N);
2469 case SelectionDAGISel::OPC_CheckValueType:
2470 Result = !::CheckValueType(Table, Index, N, SDISel.TLI,
2471 SDISel.CurDAG->getDataLayout());
2473 case SelectionDAGISel::OPC_CheckInteger:
2474 Result = !::CheckInteger(Table, Index, N);
2476 case SelectionDAGISel::OPC_CheckChild0Integer:
2477 case SelectionDAGISel::OPC_CheckChild1Integer:
2478 case SelectionDAGISel::OPC_CheckChild2Integer:
2479 case SelectionDAGISel::OPC_CheckChild3Integer:
2480 case SelectionDAGISel::OPC_CheckChild4Integer:
2481 Result = !::CheckChildInteger(Table, Index, N,
2482 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2484 case SelectionDAGISel::OPC_CheckAndImm:
2485 Result = !::CheckAndImm(Table, Index, N, SDISel);
2487 case SelectionDAGISel::OPC_CheckOrImm:
2488 Result = !::CheckOrImm(Table, Index, N, SDISel);
2496 /// FailIndex - If this match fails, this is the index to continue with.
2499 /// NodeStack - The node stack when the scope was formed.
2500 SmallVector<SDValue, 4> NodeStack;
2502 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2503 unsigned NumRecordedNodes;
2505 /// NumMatchedMemRefs - The number of matched memref entries.
2506 unsigned NumMatchedMemRefs;
2508 /// InputChain/InputGlue - The current chain/glue
2509 SDValue InputChain, InputGlue;
2511 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2512 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2515 /// \\brief A DAG update listener to keep the matching state
2516 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2517 /// change the DAG while matching. X86 addressing mode matcher is an example
2519 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2521 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2522 SmallVectorImpl<MatchScope> &MatchScopes;
2524 MatchStateUpdater(SelectionDAG &DAG,
2525 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2526 SmallVectorImpl<MatchScope> &MS) :
2527 SelectionDAG::DAGUpdateListener(DAG),
2528 RecordedNodes(RN), MatchScopes(MS) { }
2530 void NodeDeleted(SDNode *N, SDNode *E) override {
2531 // Some early-returns here to avoid the search if we deleted the node or
2532 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2533 // do, so it's unnecessary to update matching state at that point).
2534 // Neither of these can occur currently because we only install this
2535 // update listener during matching a complex patterns.
2536 if (!E || E->isMachineOpcode())
2538 // Performing linear search here does not matter because we almost never
2539 // run this code. You'd have to have a CSE during complex pattern
2541 for (auto &I : RecordedNodes)
2542 if (I.first.getNode() == N)
2545 for (auto &I : MatchScopes)
2546 for (auto &J : I.NodeStack)
2547 if (J.getNode() == N)
2553 SDNode *SelectionDAGISel::
2554 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2555 unsigned TableSize) {
2556 // FIXME: Should these even be selected? Handle these cases in the caller?
2557 switch (NodeToMatch->getOpcode()) {
2560 case ISD::EntryToken: // These nodes remain the same.
2561 case ISD::BasicBlock:
2563 case ISD::RegisterMask:
2564 case ISD::HANDLENODE:
2565 case ISD::MDNODE_SDNODE:
2566 case ISD::TargetConstant:
2567 case ISD::TargetConstantFP:
2568 case ISD::TargetConstantPool:
2569 case ISD::TargetFrameIndex:
2570 case ISD::TargetExternalSymbol:
2572 case ISD::TargetBlockAddress:
2573 case ISD::TargetJumpTable:
2574 case ISD::TargetGlobalTLSAddress:
2575 case ISD::TargetGlobalAddress:
2576 case ISD::TokenFactor:
2577 case ISD::CopyFromReg:
2578 case ISD::CopyToReg:
2580 case ISD::LIFETIME_START:
2581 case ISD::LIFETIME_END:
2582 NodeToMatch->setNodeId(-1); // Mark selected.
2584 case ISD::AssertSext:
2585 case ISD::AssertZext:
2586 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2587 NodeToMatch->getOperand(0));
2589 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2590 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2591 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2592 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2595 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2597 // Set up the node stack with NodeToMatch as the only node on the stack.
2598 SmallVector<SDValue, 8> NodeStack;
2599 SDValue N = SDValue(NodeToMatch, 0);
2600 NodeStack.push_back(N);
2602 // MatchScopes - Scopes used when matching, if a match failure happens, this
2603 // indicates where to continue checking.
2604 SmallVector<MatchScope, 8> MatchScopes;
2606 // RecordedNodes - This is the set of nodes that have been recorded by the
2607 // state machine. The second value is the parent of the node, or null if the
2608 // root is recorded.
2609 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2611 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2613 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2615 // These are the current input chain and glue for use when generating nodes.
2616 // Various Emit operations change these. For example, emitting a copytoreg
2617 // uses and updates these.
2618 SDValue InputChain, InputGlue;
2620 // ChainNodesMatched - If a pattern matches nodes that have input/output
2621 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2622 // which ones they are. The result is captured into this list so that we can
2623 // update the chain results when the pattern is complete.
2624 SmallVector<SDNode*, 3> ChainNodesMatched;
2625 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2627 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2628 NodeToMatch->dump(CurDAG);
2631 // Determine where to start the interpreter. Normally we start at opcode #0,
2632 // but if the state machine starts with an OPC_SwitchOpcode, then we
2633 // accelerate the first lookup (which is guaranteed to be hot) with the
2634 // OpcodeOffset table.
2635 unsigned MatcherIndex = 0;
2637 if (!OpcodeOffset.empty()) {
2638 // Already computed the OpcodeOffset table, just index into it.
2639 if (N.getOpcode() < OpcodeOffset.size())
2640 MatcherIndex = OpcodeOffset[N.getOpcode()];
2641 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2643 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2644 // Otherwise, the table isn't computed, but the state machine does start
2645 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2646 // is the first time we're selecting an instruction.
2649 // Get the size of this case.
2650 unsigned CaseSize = MatcherTable[Idx++];
2652 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2653 if (CaseSize == 0) break;
2655 // Get the opcode, add the index to the table.
2656 uint16_t Opc = MatcherTable[Idx++];
2657 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2658 if (Opc >= OpcodeOffset.size())
2659 OpcodeOffset.resize((Opc+1)*2);
2660 OpcodeOffset[Opc] = Idx;
2664 // Okay, do the lookup for the first opcode.
2665 if (N.getOpcode() < OpcodeOffset.size())
2666 MatcherIndex = OpcodeOffset[N.getOpcode()];
2670 assert(MatcherIndex < TableSize && "Invalid index");
2672 unsigned CurrentOpcodeIndex = MatcherIndex;
2674 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2677 // Okay, the semantics of this operation are that we should push a scope
2678 // then evaluate the first child. However, pushing a scope only to have
2679 // the first check fail (which then pops it) is inefficient. If we can
2680 // determine immediately that the first check (or first several) will
2681 // immediately fail, don't even bother pushing a scope for them.
2685 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2686 if (NumToSkip & 128)
2687 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2688 // Found the end of the scope with no match.
2689 if (NumToSkip == 0) {
2694 FailIndex = MatcherIndex+NumToSkip;
2696 unsigned MatcherIndexOfPredicate = MatcherIndex;
2697 (void)MatcherIndexOfPredicate; // silence warning.
2699 // If we can't evaluate this predicate without pushing a scope (e.g. if
2700 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2701 // push the scope and evaluate the full predicate chain.
2703 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2704 Result, *this, RecordedNodes);
2708 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2709 << "index " << MatcherIndexOfPredicate
2710 << ", continuing at " << FailIndex << "\n");
2711 ++NumDAGIselRetries;
2713 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2714 // move to the next case.
2715 MatcherIndex = FailIndex;
2718 // If the whole scope failed to match, bail.
2719 if (FailIndex == 0) break;
2721 // Push a MatchScope which indicates where to go if the first child fails
2723 MatchScope NewEntry;
2724 NewEntry.FailIndex = FailIndex;
2725 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2726 NewEntry.NumRecordedNodes = RecordedNodes.size();
2727 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2728 NewEntry.InputChain = InputChain;
2729 NewEntry.InputGlue = InputGlue;
2730 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2731 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2732 MatchScopes.push_back(NewEntry);
2735 case OPC_RecordNode: {
2736 // Remember this node, it may end up being an operand in the pattern.
2737 SDNode *Parent = nullptr;
2738 if (NodeStack.size() > 1)
2739 Parent = NodeStack[NodeStack.size()-2].getNode();
2740 RecordedNodes.push_back(std::make_pair(N, Parent));
2744 case OPC_RecordChild0: case OPC_RecordChild1:
2745 case OPC_RecordChild2: case OPC_RecordChild3:
2746 case OPC_RecordChild4: case OPC_RecordChild5:
2747 case OPC_RecordChild6: case OPC_RecordChild7: {
2748 unsigned ChildNo = Opcode-OPC_RecordChild0;
2749 if (ChildNo >= N.getNumOperands())
2750 break; // Match fails if out of range child #.
2752 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2756 case OPC_RecordMemRef:
2757 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2760 case OPC_CaptureGlueInput:
2761 // If the current node has an input glue, capture it in InputGlue.
2762 if (N->getNumOperands() != 0 &&
2763 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2764 InputGlue = N->getOperand(N->getNumOperands()-1);
2767 case OPC_MoveChild: {
2768 unsigned ChildNo = MatcherTable[MatcherIndex++];
2769 if (ChildNo >= N.getNumOperands())
2770 break; // Match fails if out of range child #.
2771 N = N.getOperand(ChildNo);
2772 NodeStack.push_back(N);
2776 case OPC_MoveParent:
2777 // Pop the current node off the NodeStack.
2778 NodeStack.pop_back();
2779 assert(!NodeStack.empty() && "Node stack imbalance!");
2780 N = NodeStack.back();
2784 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2787 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2788 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2789 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2790 Opcode-OPC_CheckChild0Same))
2794 case OPC_CheckPatternPredicate:
2795 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2797 case OPC_CheckPredicate:
2798 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2802 case OPC_CheckComplexPat: {
2803 unsigned CPNum = MatcherTable[MatcherIndex++];
2804 unsigned RecNo = MatcherTable[MatcherIndex++];
2805 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2807 // If target can modify DAG during matching, keep the matching state
2809 std::unique_ptr<MatchStateUpdater> MSU;
2810 if (ComplexPatternFuncMutatesDAG())
2811 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2814 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2815 RecordedNodes[RecNo].first, CPNum,
2820 case OPC_CheckOpcode:
2821 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2825 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI,
2826 CurDAG->getDataLayout()))
2830 case OPC_SwitchOpcode: {
2831 unsigned CurNodeOpcode = N.getOpcode();
2832 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2835 // Get the size of this case.
2836 CaseSize = MatcherTable[MatcherIndex++];
2838 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2839 if (CaseSize == 0) break;
2841 uint16_t Opc = MatcherTable[MatcherIndex++];
2842 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2844 // If the opcode matches, then we will execute this case.
2845 if (CurNodeOpcode == Opc)
2848 // Otherwise, skip over this case.
2849 MatcherIndex += CaseSize;
2852 // If no cases matched, bail out.
2853 if (CaseSize == 0) break;
2855 // Otherwise, execute the case we found.
2856 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2857 << " to " << MatcherIndex << "\n");
2861 case OPC_SwitchType: {
2862 MVT CurNodeVT = N.getSimpleValueType();
2863 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2866 // Get the size of this case.
2867 CaseSize = MatcherTable[MatcherIndex++];
2869 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2870 if (CaseSize == 0) break;
2872 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2873 if (CaseVT == MVT::iPTR)
2874 CaseVT = TLI->getPointerTy(CurDAG->getDataLayout());
2876 // If the VT matches, then we will execute this case.
2877 if (CurNodeVT == CaseVT)
2880 // Otherwise, skip over this case.
2881 MatcherIndex += CaseSize;
2884 // If no cases matched, bail out.
2885 if (CaseSize == 0) break;
2887 // Otherwise, execute the case we found.
2888 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2889 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2892 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2893 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2894 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2895 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2896 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2897 CurDAG->getDataLayout(),
2898 Opcode - OPC_CheckChild0Type))
2901 case OPC_CheckCondCode:
2902 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2904 case OPC_CheckValueType:
2905 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI,
2906 CurDAG->getDataLayout()))
2909 case OPC_CheckInteger:
2910 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2912 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2913 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2914 case OPC_CheckChild4Integer:
2915 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2916 Opcode-OPC_CheckChild0Integer)) break;
2918 case OPC_CheckAndImm:
2919 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2921 case OPC_CheckOrImm:
2922 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2925 case OPC_CheckFoldableChainNode: {
2926 assert(NodeStack.size() != 1 && "No parent node");
2927 // Verify that all intermediate nodes between the root and this one have
2929 bool HasMultipleUses = false;
2930 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2931 if (!NodeStack[i].hasOneUse()) {
2932 HasMultipleUses = true;
2935 if (HasMultipleUses) break;
2937 // Check to see that the target thinks this is profitable to fold and that
2938 // we can fold it without inducing cycles in the graph.
2939 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2941 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2942 NodeToMatch, OptLevel,
2943 true/*We validate our own chains*/))
2948 case OPC_EmitInteger: {
2949 MVT::SimpleValueType VT =
2950 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2951 int64_t Val = MatcherTable[MatcherIndex++];
2953 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2954 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2955 CurDAG->getTargetConstant(Val, SDLoc(NodeToMatch),
2959 case OPC_EmitRegister: {
2960 MVT::SimpleValueType VT =
2961 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2962 unsigned RegNo = MatcherTable[MatcherIndex++];
2963 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2964 CurDAG->getRegister(RegNo, VT), nullptr));
2967 case OPC_EmitRegister2: {
2968 // For targets w/ more than 256 register names, the register enum
2969 // values are stored in two bytes in the matcher table (just like
2971 MVT::SimpleValueType VT =
2972 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2973 unsigned RegNo = MatcherTable[MatcherIndex++];
2974 RegNo |= MatcherTable[MatcherIndex++] << 8;
2975 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2976 CurDAG->getRegister(RegNo, VT), nullptr));
2980 case OPC_EmitConvertToTarget: {
2981 // Convert from IMM/FPIMM to target version.
2982 unsigned RecNo = MatcherTable[MatcherIndex++];
2983 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2984 SDValue Imm = RecordedNodes[RecNo].first;
2986 if (Imm->getOpcode() == ISD::Constant) {
2987 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2988 Imm = CurDAG->getConstant(*Val, SDLoc(NodeToMatch), Imm.getValueType(),
2990 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2991 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2992 Imm = CurDAG->getConstantFP(*Val, SDLoc(NodeToMatch),
2993 Imm.getValueType(), true);
2996 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
3000 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
3001 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
3002 // These are space-optimized forms of OPC_EmitMergeInputChains.
3003 assert(!InputChain.getNode() &&
3004 "EmitMergeInputChains should be the first chain producing node");
3005 assert(ChainNodesMatched.empty() &&
3006 "Should only have one EmitMergeInputChains per match");
3008 // Read all of the chained nodes.
3009 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
3010 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3011 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3013 // FIXME: What if other value results of the node have uses not matched
3015 if (ChainNodesMatched.back() != NodeToMatch &&
3016 !RecordedNodes[RecNo].first.hasOneUse()) {
3017 ChainNodesMatched.clear();
3021 // Merge the input chains if they are not intra-pattern references.
3022 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3024 if (!InputChain.getNode())
3025 break; // Failed to merge.
3029 case OPC_EmitMergeInputChains: {
3030 assert(!InputChain.getNode() &&
3031 "EmitMergeInputChains should be the first chain producing node");
3032 // This node gets a list of nodes we matched in the input that have
3033 // chains. We want to token factor all of the input chains to these nodes
3034 // together. However, if any of the input chains is actually one of the
3035 // nodes matched in this pattern, then we have an intra-match reference.
3036 // Ignore these because the newly token factored chain should not refer to
3038 unsigned NumChains = MatcherTable[MatcherIndex++];
3039 assert(NumChains != 0 && "Can't TF zero chains");
3041 assert(ChainNodesMatched.empty() &&
3042 "Should only have one EmitMergeInputChains per match");
3044 // Read all of the chained nodes.
3045 for (unsigned i = 0; i != NumChains; ++i) {
3046 unsigned RecNo = MatcherTable[MatcherIndex++];
3047 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3048 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3050 // FIXME: What if other value results of the node have uses not matched
3052 if (ChainNodesMatched.back() != NodeToMatch &&
3053 !RecordedNodes[RecNo].first.hasOneUse()) {
3054 ChainNodesMatched.clear();
3059 // If the inner loop broke out, the match fails.
3060 if (ChainNodesMatched.empty())
3063 // Merge the input chains if they are not intra-pattern references.
3064 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3066 if (!InputChain.getNode())
3067 break; // Failed to merge.
3072 case OPC_EmitCopyToReg: {
3073 unsigned RecNo = MatcherTable[MatcherIndex++];
3074 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3075 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3077 if (!InputChain.getNode())
3078 InputChain = CurDAG->getEntryNode();
3080 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3081 DestPhysReg, RecordedNodes[RecNo].first,
3084 InputGlue = InputChain.getValue(1);
3088 case OPC_EmitNodeXForm: {
3089 unsigned XFormNo = MatcherTable[MatcherIndex++];
3090 unsigned RecNo = MatcherTable[MatcherIndex++];
3091 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3092 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3093 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3098 case OPC_MorphNodeTo: {
3099 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3100 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3101 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3102 // Get the result VT list.
3103 unsigned NumVTs = MatcherTable[MatcherIndex++];
3104 SmallVector<EVT, 4> VTs;
3105 for (unsigned i = 0; i != NumVTs; ++i) {
3106 MVT::SimpleValueType VT =
3107 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3108 if (VT == MVT::iPTR)
3109 VT = TLI->getPointerTy(CurDAG->getDataLayout()).SimpleTy;
3113 if (EmitNodeInfo & OPFL_Chain)
3114 VTs.push_back(MVT::Other);
3115 if (EmitNodeInfo & OPFL_GlueOutput)
3116 VTs.push_back(MVT::Glue);
3118 // This is hot code, so optimize the two most common cases of 1 and 2
3121 if (VTs.size() == 1)
3122 VTList = CurDAG->getVTList(VTs[0]);
3123 else if (VTs.size() == 2)
3124 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3126 VTList = CurDAG->getVTList(VTs);
3128 // Get the operand list.
3129 unsigned NumOps = MatcherTable[MatcherIndex++];
3130 SmallVector<SDValue, 8> Ops;
3131 for (unsigned i = 0; i != NumOps; ++i) {
3132 unsigned RecNo = MatcherTable[MatcherIndex++];
3134 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3136 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3137 Ops.push_back(RecordedNodes[RecNo].first);
3140 // If there are variadic operands to add, handle them now.
3141 if (EmitNodeInfo & OPFL_VariadicInfo) {
3142 // Determine the start index to copy from.
3143 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3144 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3145 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3146 "Invalid variadic node");
3147 // Copy all of the variadic operands, not including a potential glue
3149 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3151 SDValue V = NodeToMatch->getOperand(i);
3152 if (V.getValueType() == MVT::Glue) break;
3157 // If this has chain/glue inputs, add them.
3158 if (EmitNodeInfo & OPFL_Chain)
3159 Ops.push_back(InputChain);
3160 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3161 Ops.push_back(InputGlue);
3164 SDNode *Res = nullptr;
3165 if (Opcode != OPC_MorphNodeTo) {
3166 // If this is a normal EmitNode command, just create the new node and
3167 // add the results to the RecordedNodes list.
3168 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3171 // Add all the non-glue/non-chain results to the RecordedNodes list.
3172 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3173 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3174 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3178 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3179 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3181 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3182 // We will visit the equivalent node later.
3183 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3187 // If the node had chain/glue results, update our notion of the current
3189 if (EmitNodeInfo & OPFL_GlueOutput) {
3190 InputGlue = SDValue(Res, VTs.size()-1);
3191 if (EmitNodeInfo & OPFL_Chain)
3192 InputChain = SDValue(Res, VTs.size()-2);
3193 } else if (EmitNodeInfo & OPFL_Chain)
3194 InputChain = SDValue(Res, VTs.size()-1);
3196 // If the OPFL_MemRefs glue is set on this node, slap all of the
3197 // accumulated memrefs onto it.
3199 // FIXME: This is vastly incorrect for patterns with multiple outputs
3200 // instructions that access memory and for ComplexPatterns that match
3202 if (EmitNodeInfo & OPFL_MemRefs) {
3203 // Only attach load or store memory operands if the generated
3204 // instruction may load or store.
3205 const MCInstrDesc &MCID = TII->get(TargetOpc);
3206 bool mayLoad = MCID.mayLoad();
3207 bool mayStore = MCID.mayStore();
3209 unsigned NumMemRefs = 0;
3210 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3211 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3212 if ((*I)->isLoad()) {
3215 } else if ((*I)->isStore()) {
3223 MachineSDNode::mmo_iterator MemRefs =
3224 MF->allocateMemRefsArray(NumMemRefs);
3226 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3227 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3228 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3229 if ((*I)->isLoad()) {
3232 } else if ((*I)->isStore()) {
3240 cast<MachineSDNode>(Res)
3241 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3245 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3246 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3248 // If this was a MorphNodeTo then we're completely done!
3249 if (Opcode == OPC_MorphNodeTo) {
3250 // Update chain and glue uses.
3251 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3252 InputGlue, GlueResultNodesMatched, true);
3259 case OPC_MarkGlueResults: {
3260 unsigned NumNodes = MatcherTable[MatcherIndex++];
3262 // Read and remember all the glue-result nodes.
3263 for (unsigned i = 0; i != NumNodes; ++i) {
3264 unsigned RecNo = MatcherTable[MatcherIndex++];
3266 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3268 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3269 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3274 case OPC_CompleteMatch: {
3275 // The match has been completed, and any new nodes (if any) have been
3276 // created. Patch up references to the matched dag to use the newly
3278 unsigned NumResults = MatcherTable[MatcherIndex++];
3280 for (unsigned i = 0; i != NumResults; ++i) {
3281 unsigned ResSlot = MatcherTable[MatcherIndex++];
3283 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3285 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3286 SDValue Res = RecordedNodes[ResSlot].first;
3288 assert(i < NodeToMatch->getNumValues() &&
3289 NodeToMatch->getValueType(i) != MVT::Other &&
3290 NodeToMatch->getValueType(i) != MVT::Glue &&
3291 "Invalid number of results to complete!");
3292 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3293 NodeToMatch->getValueType(i) == MVT::iPTR ||
3294 Res.getValueType() == MVT::iPTR ||
3295 NodeToMatch->getValueType(i).getSizeInBits() ==
3296 Res.getValueType().getSizeInBits()) &&
3297 "invalid replacement");
3298 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3301 // If the root node defines glue, add it to the glue nodes to update list.
3302 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3303 GlueResultNodesMatched.push_back(NodeToMatch);
3305 // Update chain and glue uses.
3306 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3307 InputGlue, GlueResultNodesMatched, false);
3309 assert(NodeToMatch->use_empty() &&
3310 "Didn't replace all uses of the node?");
3312 // FIXME: We just return here, which interacts correctly with SelectRoot
3313 // above. We should fix this to not return an SDNode* anymore.
3318 // If the code reached this point, then the match failed. See if there is
3319 // another child to try in the current 'Scope', otherwise pop it until we
3320 // find a case to check.
3321 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3322 ++NumDAGIselRetries;
3324 if (MatchScopes.empty()) {
3325 CannotYetSelect(NodeToMatch);
3329 // Restore the interpreter state back to the point where the scope was
3331 MatchScope &LastScope = MatchScopes.back();
3332 RecordedNodes.resize(LastScope.NumRecordedNodes);
3334 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3335 N = NodeStack.back();
3337 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3338 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3339 MatcherIndex = LastScope.FailIndex;
3341 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3343 InputChain = LastScope.InputChain;
3344 InputGlue = LastScope.InputGlue;
3345 if (!LastScope.HasChainNodesMatched)
3346 ChainNodesMatched.clear();
3347 if (!LastScope.HasGlueResultNodesMatched)
3348 GlueResultNodesMatched.clear();
3350 // Check to see what the offset is at the new MatcherIndex. If it is zero
3351 // we have reached the end of this scope, otherwise we have another child
3352 // in the current scope to try.
3353 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3354 if (NumToSkip & 128)
3355 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3357 // If we have another child in this scope to match, update FailIndex and
3359 if (NumToSkip != 0) {
3360 LastScope.FailIndex = MatcherIndex+NumToSkip;
3364 // End of this scope, pop it and try the next child in the containing
3366 MatchScopes.pop_back();
3373 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3375 raw_string_ostream Msg(msg);
3376 Msg << "Cannot select: ";
3378 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3379 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3380 N->getOpcode() != ISD::INTRINSIC_VOID) {
3381 N->printrFull(Msg, CurDAG);
3382 Msg << "\nIn function: " << MF->getName();
3384 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3386 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3387 if (iid < Intrinsic::num_intrinsics)
3388 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3389 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3390 Msg << "target intrinsic %" << TII->getName(iid);
3392 Msg << "unknown intrinsic #" << iid;
3394 report_fatal_error(Msg.str());
3397 char SelectionDAGISel::ID = 0;