1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
47 #include "llvm/Support/Compiler.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/Timer.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/ADT/Statistic.h"
56 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
57 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
58 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
59 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
62 STATISTIC(NumBBWithOutOfOrderLineInfo,
63 "Number of blocks with out of order line number info");
64 STATISTIC(NumMBBWithOutOfOrderLineInfo,
65 "Number of machine blocks with out of order line number info");
69 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
70 cl::desc("Enable verbose messages in the \"fast\" "
71 "instruction selector"));
73 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
74 cl::desc("Enable abort calls when \"fast\" instruction fails"));
78 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the first "
82 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
83 cl::desc("Pop up a window to show dags before legalize types"));
85 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
86 cl::desc("Pop up a window to show dags before legalize"));
88 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
89 cl::desc("Pop up a window to show dags before the second "
92 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
93 cl::desc("Pop up a window to show dags before the post legalize types"
94 " dag combine pass"));
96 ViewISelDAGs("view-isel-dags", cl::Hidden,
97 cl::desc("Pop up a window to show isel dags as they are selected"));
99 ViewSchedDAGs("view-sched-dags", cl::Hidden,
100 cl::desc("Pop up a window to show sched dags as they are processed"));
102 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
103 cl::desc("Pop up a window to show SUnit dags after they are processed"));
105 static const bool ViewDAGCombine1 = false,
106 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
107 ViewDAGCombine2 = false,
108 ViewDAGCombineLT = false,
109 ViewISelDAGs = false, ViewSchedDAGs = false,
110 ViewSUnitDAGs = false;
113 //===---------------------------------------------------------------------===//
115 /// RegisterScheduler class - Track the registration of instruction schedulers.
117 //===---------------------------------------------------------------------===//
118 MachinePassRegistry RegisterScheduler::Registry;
120 //===---------------------------------------------------------------------===//
122 /// ISHeuristic command line option for instruction schedulers.
124 //===---------------------------------------------------------------------===//
125 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
126 RegisterPassParser<RegisterScheduler> >
127 ISHeuristic("pre-RA-sched",
128 cl::init(&createDefaultScheduler),
129 cl::desc("Instruction schedulers available (before register"
132 static RegisterScheduler
133 defaultListDAGScheduler("default", "Best scheduler for the target",
134 createDefaultScheduler);
137 //===--------------------------------------------------------------------===//
138 /// createDefaultScheduler - This creates an instruction scheduler appropriate
140 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
141 CodeGenOpt::Level OptLevel) {
142 const TargetLowering &TLI = IS->getTargetLowering();
144 if (OptLevel == CodeGenOpt::None)
145 return createSourceListDAGScheduler(IS, OptLevel);
146 if (TLI.getSchedulingPreference() == Sched::Latency)
147 return createTDListDAGScheduler(IS, OptLevel);
148 if (TLI.getSchedulingPreference() == Sched::RegPressure)
149 return createBURRListDAGScheduler(IS, OptLevel);
150 if (TLI.getSchedulingPreference() == Sched::Hybrid)
151 return createHybridListDAGScheduler(IS, OptLevel);
152 assert(TLI.getSchedulingPreference() == Sched::ILP &&
153 "Unknown sched type!");
154 return createILPListDAGScheduler(IS, OptLevel);
158 // EmitInstrWithCustomInserter - This method should be implemented by targets
159 // that mark instructions with the 'usesCustomInserter' flag. These
160 // instructions are special in various ways, which require special support to
161 // insert. The specified MachineInstr is created but not inserted into any
162 // basic blocks, and this method is called to expand it into a sequence of
163 // instructions, potentially also creating new basic blocks and control flow.
164 // When new basic blocks are inserted and the edges from MBB to its successors
165 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
168 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
169 MachineBasicBlock *MBB) const {
171 dbgs() << "If a target marks an instruction with "
172 "'usesCustomInserter', it must implement "
173 "TargetLowering::EmitInstrWithCustomInserter!";
179 //===----------------------------------------------------------------------===//
180 // SelectionDAGISel code
181 //===----------------------------------------------------------------------===//
183 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
184 CodeGenOpt::Level OL) :
185 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
186 FuncInfo(new FunctionLoweringInfo(TLI)),
187 CurDAG(new SelectionDAG(tm)),
188 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
192 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
193 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
196 SelectionDAGISel::~SelectionDAGISel() {
202 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
203 AU.addRequired<AliasAnalysis>();
204 AU.addPreserved<AliasAnalysis>();
205 AU.addRequired<GCModuleInfo>();
206 AU.addPreserved<GCModuleInfo>();
207 MachineFunctionPass::getAnalysisUsage(AU);
210 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
211 /// other function that gcc recognizes as "returning twice". This is used to
212 /// limit code-gen optimizations on the machine function.
214 /// FIXME: Remove after <rdar://problem/8031714> is fixed.
215 static bool FunctionCallsSetJmp(const Function *F) {
216 const Module *M = F->getParent();
217 static const char *ReturnsTwiceFns[] = {
227 #define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *)
229 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I)
230 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) {
231 if (!Callee->use_empty())
232 for (Value::const_use_iterator
233 I = Callee->use_begin(), E = Callee->use_end();
235 if (const CallInst *CI = dyn_cast<CallInst>(*I))
236 if (CI->getParent()->getParent() == F)
241 #undef NUM_RETURNS_TWICE_FNS
244 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
245 /// may trap on it. In this case we have to split the edge so that the path
246 /// through the predecessor block that doesn't go to the phi block doesn't
247 /// execute the possibly trapping instruction.
249 /// This is required for correctness, so it must be done at -O0.
251 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
252 // Loop for blocks with phi nodes.
253 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
254 PHINode *PN = dyn_cast<PHINode>(BB->begin());
255 if (PN == 0) continue;
258 // For each block with a PHI node, check to see if any of the input values
259 // are potentially trapping constant expressions. Constant expressions are
260 // the only potentially trapping value that can occur as the argument to a
262 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
263 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
264 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
265 if (CE == 0 || !CE->canTrap()) continue;
267 // The only case we have to worry about is when the edge is critical.
268 // Since this block has a PHI Node, we assume it has multiple input
269 // edges: check to see if the pred has multiple successors.
270 BasicBlock *Pred = PN->getIncomingBlock(i);
271 if (Pred->getTerminator()->getNumSuccessors() == 1)
274 // Okay, we have to split this edge.
275 SplitCriticalEdge(Pred->getTerminator(),
276 GetSuccessorNumber(Pred, BB), SDISel, true);
282 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
283 // Do some sanity-checking on the command-line options.
284 assert((!EnableFastISelVerbose || EnableFastISel) &&
285 "-fast-isel-verbose requires -fast-isel");
286 assert((!EnableFastISelAbort || EnableFastISel) &&
287 "-fast-isel-abort requires -fast-isel");
289 const Function &Fn = *mf.getFunction();
290 const TargetInstrInfo &TII = *TM.getInstrInfo();
291 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
294 RegInfo = &MF->getRegInfo();
295 AA = &getAnalysis<AliasAnalysis>();
296 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
298 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
300 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
303 FuncInfo->set(Fn, *MF);
306 SelectAllBasicBlocks(Fn);
308 // If the first basic block in the function has live ins that need to be
309 // copied into vregs, emit the copies into the top of the block before
310 // emitting the code for the block.
311 MachineBasicBlock *EntryMBB = MF->begin();
312 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
314 DenseMap<unsigned, unsigned> LiveInMap;
315 if (!FuncInfo->ArgDbgValues.empty())
316 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
317 E = RegInfo->livein_end(); LI != E; ++LI)
319 LiveInMap.insert(std::make_pair(LI->first, LI->second));
321 // Insert DBG_VALUE instructions for function arguments to the entry block.
322 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
323 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
324 unsigned Reg = MI->getOperand(0).getReg();
325 if (TargetRegisterInfo::isPhysicalRegister(Reg))
326 EntryMBB->insert(EntryMBB->begin(), MI);
328 MachineInstr *Def = RegInfo->getVRegDef(Reg);
329 MachineBasicBlock::iterator InsertPos = Def;
330 // FIXME: VR def may not be in entry block.
331 Def->getParent()->insert(llvm::next(InsertPos), MI);
334 // If Reg is live-in then update debug info to track its copy in a vreg.
335 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
336 if (LDI != LiveInMap.end()) {
337 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
338 MachineBasicBlock::iterator InsertPos = Def;
339 const MDNode *Variable =
340 MI->getOperand(MI->getNumOperands()-1).getMetadata();
341 unsigned Offset = MI->getOperand(1).getImm();
342 // Def is never a terminator here, so it is ok to increment InsertPos.
343 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
344 TII.get(TargetOpcode::DBG_VALUE))
345 .addReg(LDI->second, RegState::Debug)
346 .addImm(Offset).addMetadata(Variable);
348 // If this vreg is directly copied into an exported register then
349 // that COPY instructions also need DBG_VALUE, if it is the only
350 // user of LDI->second.
351 MachineInstr *CopyUseMI = NULL;
352 for (MachineRegisterInfo::use_iterator
353 UI = RegInfo->use_begin(LDI->second);
354 MachineInstr *UseMI = UI.skipInstruction();) {
355 if (UseMI->isDebugValue()) continue;
356 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
357 CopyUseMI = UseMI; continue;
359 // Otherwise this is another use or second copy use.
360 CopyUseMI = NULL; break;
363 MachineInstr *NewMI =
364 BuildMI(*MF, CopyUseMI->getDebugLoc(),
365 TII.get(TargetOpcode::DBG_VALUE))
366 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
367 .addImm(Offset).addMetadata(Variable);
368 EntryMBB->insertAfter(CopyUseMI, NewMI);
373 // Determine if there are any calls in this machine function.
374 MachineFrameInfo *MFI = MF->getFrameInfo();
375 if (!MFI->hasCalls()) {
376 for (MachineFunction::const_iterator
377 I = MF->begin(), E = MF->end(); I != E; ++I) {
378 const MachineBasicBlock *MBB = I;
379 for (MachineBasicBlock::const_iterator
380 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
381 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
383 if ((TID.isCall() && !TID.isReturn()) ||
384 II->isStackAligningInlineAsm()) {
385 MFI->setHasCalls(true);
393 // Determine if there is a call to setjmp in the machine function.
394 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
396 // Replace forward-declared registers with the registers containing
397 // the desired value.
398 MachineRegisterInfo &MRI = MF->getRegInfo();
399 for (DenseMap<unsigned, unsigned>::iterator
400 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
402 unsigned From = I->first;
403 unsigned To = I->second;
404 // If To is also scheduled to be replaced, find what its ultimate
407 DenseMap<unsigned, unsigned>::iterator J =
408 FuncInfo->RegFixups.find(To);
413 MRI.replaceRegWith(From, To);
416 // Release function-specific state. SDB and CurDAG are already cleared
424 SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
425 BasicBlock::const_iterator End,
427 // Lower all of the non-terminator instructions. If a call is emitted
428 // as a tail call, cease emitting nodes for this block. Terminators
429 // are handled below.
430 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
433 // Make sure the root of the DAG is up-to-date.
434 CurDAG->setRoot(SDB->getControlRoot());
435 HadTailCall = SDB->HasTailCall;
438 // Final step, emit the lowered DAG as machine code.
443 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
444 SmallPtrSet<SDNode*, 128> VisitedNodes;
445 SmallVector<SDNode*, 128> Worklist;
447 Worklist.push_back(CurDAG->getRoot().getNode());
454 SDNode *N = Worklist.pop_back_val();
456 // If we've already seen this node, ignore it.
457 if (!VisitedNodes.insert(N))
460 // Otherwise, add all chain operands to the worklist.
461 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
462 if (N->getOperand(i).getValueType() == MVT::Other)
463 Worklist.push_back(N->getOperand(i).getNode());
465 // If this is a CopyToReg with a vreg dest, process it.
466 if (N->getOpcode() != ISD::CopyToReg)
469 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
470 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
473 // Ignore non-scalar or non-integer values.
474 SDValue Src = N->getOperand(2);
475 EVT SrcVT = Src.getValueType();
476 if (!SrcVT.isInteger() || SrcVT.isVector())
479 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
480 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
481 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
483 // Only install this information if it tells us something.
484 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
485 FuncInfo->LiveOutRegInfo.grow(DestReg);
486 FunctionLoweringInfo::LiveOutInfo &LOI =
487 FuncInfo->LiveOutRegInfo[DestReg];
488 LOI.NumSignBits = NumSignBits;
489 LOI.KnownOne = KnownOne;
490 LOI.KnownZero = KnownZero;
492 } while (!Worklist.empty());
495 void SelectionDAGISel::CodeGenAndEmitDAG() {
496 std::string GroupName;
497 if (TimePassesIsEnabled)
498 GroupName = "Instruction Selection and Scheduling";
499 std::string BlockName;
500 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
501 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
503 BlockName = MF->getFunction()->getNameStr() + ":" +
504 FuncInfo->MBB->getBasicBlock()->getNameStr();
506 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
508 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
510 // Run the DAG combiner in pre-legalize mode.
512 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
513 CurDAG->Combine(Unrestricted, *AA, OptLevel);
516 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump());
518 // Second step, hack on the DAG until it only uses operations and types that
519 // the target supports.
520 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
525 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
526 Changed = CurDAG->LegalizeTypes();
529 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump());
532 if (ViewDAGCombineLT)
533 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
535 // Run the DAG combiner in post-type-legalize mode.
537 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
538 TimePassesIsEnabled);
539 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
542 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n";
547 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
548 Changed = CurDAG->LegalizeVectors();
553 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
554 CurDAG->LegalizeTypes();
557 if (ViewDAGCombineLT)
558 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
560 // Run the DAG combiner in post-type-legalize mode.
562 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
563 TimePassesIsEnabled);
564 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
567 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n";
571 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
574 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
575 CurDAG->Legalize(OptLevel);
578 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump());
580 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
582 // Run the DAG combiner in post-legalize mode.
584 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
585 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
588 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump());
590 if (OptLevel != CodeGenOpt::None)
591 ComputeLiveOutVRegInfo();
593 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
595 // Third, instruction select all of the operations to machine code, adding the
596 // code to the MachineBasicBlock.
598 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
599 DoInstructionSelection();
602 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump());
604 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
606 // Schedule machine code.
607 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
609 NamedRegionTimer T("Instruction Scheduling", GroupName,
610 TimePassesIsEnabled);
611 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
614 if (ViewSUnitDAGs) Scheduler->viewGraph();
616 // Emit machine code to BB. This can change 'BB' to the last block being
618 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
620 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
622 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
623 FuncInfo->InsertPt = Scheduler->InsertPos;
626 // If the block was split, make sure we update any references that are used to
627 // update PHI nodes later on.
628 if (FirstMBB != LastMBB)
629 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
631 // Free the scheduler state.
633 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
634 TimePassesIsEnabled);
638 // Free the SelectionDAG state, now that we're finished with it.
642 void SelectionDAGISel::DoInstructionSelection() {
643 DEBUG(errs() << "===== Instruction selection begins:\n");
647 // Select target instructions for the DAG.
649 // Number all nodes with a topological order and set DAGSize.
650 DAGSize = CurDAG->AssignTopologicalOrder();
652 // Create a dummy node (which is not added to allnodes), that adds
653 // a reference to the root node, preventing it from being deleted,
654 // and tracking any changes of the root.
655 HandleSDNode Dummy(CurDAG->getRoot());
656 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
659 // The AllNodes list is now topological-sorted. Visit the
660 // nodes by starting at the end of the list (the root of the
661 // graph) and preceding back toward the beginning (the entry
663 while (ISelPosition != CurDAG->allnodes_begin()) {
664 SDNode *Node = --ISelPosition;
665 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
666 // but there are currently some corner cases that it misses. Also, this
667 // makes it theoretically possible to disable the DAGCombiner.
668 if (Node->use_empty())
671 SDNode *ResNode = Select(Node);
673 // FIXME: This is pretty gross. 'Select' should be changed to not return
674 // anything at all and this code should be nuked with a tactical strike.
676 // If node should not be replaced, continue with the next one.
677 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
681 ReplaceUses(Node, ResNode);
683 // If after the replacement this node is not used any more,
684 // remove this dead node.
685 if (Node->use_empty()) { // Don't delete EntryToken, etc.
686 ISelUpdater ISU(ISelPosition);
687 CurDAG->RemoveDeadNode(Node, &ISU);
691 CurDAG->setRoot(Dummy.getValue());
694 DEBUG(errs() << "===== Instruction selection ends:\n");
696 PostprocessISelDAG();
699 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
700 /// do other setup for EH landing-pad blocks.
701 void SelectionDAGISel::PrepareEHLandingPad() {
702 // Add a label to mark the beginning of the landing pad. Deletion of the
703 // landing pad can thus be detected via the MachineModuleInfo.
704 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
706 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
707 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
710 // Mark exception register as live in.
711 unsigned Reg = TLI.getExceptionAddressRegister();
712 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
714 // Mark exception selector register as live in.
715 Reg = TLI.getExceptionSelectorRegister();
716 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
718 // FIXME: Hack around an exception handling flaw (PR1508): the personality
719 // function and list of typeids logically belong to the invoke (or, if you
720 // like, the basic block containing the invoke), and need to be associated
721 // with it in the dwarf exception handling tables. Currently however the
722 // information is provided by an intrinsic (eh.selector) that can be moved
723 // to unexpected places by the optimizers: if the unwind edge is critical,
724 // then breaking it can result in the intrinsics being in the successor of
725 // the landing pad, not the landing pad itself. This results
726 // in exceptions not being caught because no typeids are associated with
727 // the invoke. This may not be the only way things can go wrong, but it
728 // is the only way we try to work around for the moment.
729 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
730 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
732 if (Br && Br->isUnconditional()) { // Critical edge?
733 BasicBlock::const_iterator I, E;
734 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
735 if (isa<EHSelectorInst>(I))
739 // No catch info found - try to extract some from the successor.
740 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
747 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
749 // Don't try to fold volatile loads. Target has to deal with alignment
751 if (LI->isVolatile()) return false;
753 // Figure out which vreg this is going into.
754 unsigned LoadReg = FastIS->getRegForValue(LI);
755 assert(LoadReg && "Load isn't already assigned a vreg? ");
757 // Check to see what the uses of this vreg are. If it has no uses, or more
758 // than one use (at the machine instr level) then we can't fold it.
759 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
760 if (RI == RegInfo->reg_end())
763 // See if there is exactly one use of the vreg. If there are multiple uses,
764 // then the instruction got lowered to multiple machine instructions or the
765 // use of the loaded value ended up being multiple operands of the result, in
766 // either case, we can't fold this.
767 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
768 if (PostRI != RegInfo->reg_end())
771 assert(RI.getOperand().isUse() &&
772 "The only use of the vreg must be a use, we haven't emitted the def!");
774 // Ask the target to try folding the load.
775 return FastIS->TryToFoldLoad(&*RI, RI.getOperandNo(), LI);
779 /// CheckLineNumbers - Check if basic block instructions follow source order
781 static void CheckLineNumbers(const BasicBlock *BB) {
784 for (BasicBlock::const_iterator BI = BB->begin(),
785 BE = BB->end(); BI != BE; ++BI) {
786 const DebugLoc DL = BI->getDebugLoc();
787 if (DL.isUnknown()) continue;
788 unsigned L = DL.getLine();
789 unsigned C = DL.getCol();
790 if (L < Line || (L == Line && C < Col)) {
791 ++NumBBWithOutOfOrderLineInfo;
799 /// CheckLineNumbers - Check if machine basic block instructions follow source
801 static void CheckLineNumbers(const MachineBasicBlock *MBB) {
804 for (MachineBasicBlock::const_iterator MBI = MBB->begin(),
805 MBE = MBB->end(); MBI != MBE; ++MBI) {
806 const DebugLoc DL = MBI->getDebugLoc();
807 if (DL.isUnknown()) continue;
808 unsigned L = DL.getLine();
809 unsigned C = DL.getCol();
810 if (L < Line || (L == Line && C < Col)) {
811 ++NumMBBWithOutOfOrderLineInfo;
820 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
821 // Initialize the Fast-ISel state, if needed.
822 FastISel *FastIS = 0;
824 FastIS = TLI.createFastISel(*FuncInfo);
826 // Iterate over all basic blocks in the function.
827 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
828 const BasicBlock *LLVMBB = &*I;
830 CheckLineNumbers(LLVMBB);
832 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
833 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
835 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
836 BasicBlock::const_iterator const End = LLVMBB->end();
837 BasicBlock::const_iterator BI = End;
839 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
841 // Setup an EH landing-pad block.
842 if (FuncInfo->MBB->isLandingPad())
843 PrepareEHLandingPad();
845 // Lower any arguments needed in this block if this is the entry block.
846 if (LLVMBB == &Fn.getEntryBlock())
847 LowerArguments(LLVMBB);
849 // Before doing SelectionDAG ISel, see if FastISel has been requested.
851 FastIS->startNewBlock();
853 // Emit code for any incoming arguments. This must happen before
854 // beginning FastISel on the entry block.
855 if (LLVMBB == &Fn.getEntryBlock()) {
856 CurDAG->setRoot(SDB->getControlRoot());
860 // If we inserted any instructions at the beginning, make a note of
861 // where they are, so we can be sure to emit subsequent instructions
863 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
864 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
866 FastIS->setLastLocalValue(0);
869 // Do FastISel on as many instructions as possible.
870 for (; BI != Begin; --BI) {
871 const Instruction *Inst = llvm::prior(BI);
873 // If we no longer require this instruction, skip it.
874 if (!Inst->mayWriteToMemory() &&
875 !isa<TerminatorInst>(Inst) &&
876 !isa<DbgInfoIntrinsic>(Inst) &&
877 !FuncInfo->isExportedInst(Inst))
880 // Bottom-up: reset the insert pos at the top, after any local-value
882 FastIS->recomputeInsertPt();
884 // Try to select the instruction with FastISel.
885 if (FastIS->SelectInstruction(Inst)) {
886 // If fast isel succeeded, check to see if there is a single-use
887 // non-volatile load right before the selected instruction, and see if
888 // the load is used by the instruction. If so, try to fold it.
889 const Instruction *BeforeInst = 0;
891 BeforeInst = llvm::prior(llvm::prior(BI));
892 if (BeforeInst && isa<LoadInst>(BeforeInst) &&
893 BeforeInst->hasOneUse() && *BeforeInst->use_begin() == Inst &&
894 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), FastIS)) {
895 // If we succeeded, don't re-select the load.
901 // Then handle certain instructions as single-LLVM-Instruction blocks.
902 if (isa<CallInst>(Inst)) {
903 ++NumFastIselFailures;
904 if (EnableFastISelVerbose || EnableFastISelAbort) {
905 dbgs() << "FastISel missed call: ";
909 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
910 unsigned &R = FuncInfo->ValueMap[Inst];
912 R = FuncInfo->CreateRegs(Inst->getType());
915 bool HadTailCall = false;
916 SelectBasicBlock(Inst, BI, HadTailCall);
918 // If the call was emitted as a tail call, we're done with the block.
927 // Otherwise, give up on FastISel for the rest of the block.
928 // For now, be a little lenient about non-branch terminators.
929 if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) {
930 ++NumFastIselFailures;
931 if (EnableFastISelVerbose || EnableFastISelAbort) {
932 dbgs() << "FastISel miss: ";
935 if (EnableFastISelAbort)
936 // The "fast" selector couldn't handle something and bailed.
937 // For the purpose of debugging, just abort.
938 llvm_unreachable("FastISel didn't select the entire block");
943 FastIS->recomputeInsertPt();
951 // Run SelectionDAG instruction selection on the remainder of the block
952 // not handled by FastISel. If FastISel is not run, this is the entire
955 SelectBasicBlock(Begin, BI, HadTailCall);
958 FuncInfo->PHINodesToUpdate.clear();
963 for (MachineFunction::const_iterator MBI = MF->begin(), MBE = MF->end();
965 CheckLineNumbers(MBI);
970 SelectionDAGISel::FinishBasicBlock() {
972 DEBUG(dbgs() << "Total amount of phi nodes to update: "
973 << FuncInfo->PHINodesToUpdate.size() << "\n";
974 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
975 dbgs() << "Node " << i << " : ("
976 << FuncInfo->PHINodesToUpdate[i].first
977 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
979 // Next, now that we know what the last MBB the LLVM BB expanded is, update
980 // PHI nodes in successors.
981 if (SDB->SwitchCases.empty() &&
982 SDB->JTCases.empty() &&
983 SDB->BitTestCases.empty()) {
984 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
985 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
986 assert(PHI->isPHI() &&
987 "This is not a machine PHI node that we are updating!");
988 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
991 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
992 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
997 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
998 // Lower header first, if it wasn't already lowered
999 if (!SDB->BitTestCases[i].Emitted) {
1000 // Set the current basic block to the mbb we wish to insert the code into
1001 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1002 FuncInfo->InsertPt = FuncInfo->MBB->end();
1004 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1005 CurDAG->setRoot(SDB->getRoot());
1007 CodeGenAndEmitDAG();
1010 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1011 // Set the current basic block to the mbb we wish to insert the code into
1012 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1013 FuncInfo->InsertPt = FuncInfo->MBB->end();
1016 SDB->visitBitTestCase(SDB->BitTestCases[i],
1017 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1018 SDB->BitTestCases[i].Reg,
1019 SDB->BitTestCases[i].Cases[j],
1022 SDB->visitBitTestCase(SDB->BitTestCases[i],
1023 SDB->BitTestCases[i].Default,
1024 SDB->BitTestCases[i].Reg,
1025 SDB->BitTestCases[i].Cases[j],
1029 CurDAG->setRoot(SDB->getRoot());
1031 CodeGenAndEmitDAG();
1035 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1037 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1038 MachineBasicBlock *PHIBB = PHI->getParent();
1039 assert(PHI->isPHI() &&
1040 "This is not a machine PHI node that we are updating!");
1041 // This is "default" BB. We have two jumps to it. From "header" BB and
1042 // from last "case" BB.
1043 if (PHIBB == SDB->BitTestCases[i].Default) {
1044 PHI->addOperand(MachineOperand::
1045 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1047 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1048 PHI->addOperand(MachineOperand::
1049 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1051 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1054 // One of "cases" BB.
1055 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1057 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1058 if (cBB->isSuccessor(PHIBB)) {
1059 PHI->addOperand(MachineOperand::
1060 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1062 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1067 SDB->BitTestCases.clear();
1069 // If the JumpTable record is filled in, then we need to emit a jump table.
1070 // Updating the PHI nodes is tricky in this case, since we need to determine
1071 // whether the PHI is a successor of the range check MBB or the jump table MBB
1072 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1073 // Lower header first, if it wasn't already lowered
1074 if (!SDB->JTCases[i].first.Emitted) {
1075 // Set the current basic block to the mbb we wish to insert the code into
1076 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1077 FuncInfo->InsertPt = FuncInfo->MBB->end();
1079 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1081 CurDAG->setRoot(SDB->getRoot());
1083 CodeGenAndEmitDAG();
1086 // Set the current basic block to the mbb we wish to insert the code into
1087 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1088 FuncInfo->InsertPt = FuncInfo->MBB->end();
1090 SDB->visitJumpTable(SDB->JTCases[i].second);
1091 CurDAG->setRoot(SDB->getRoot());
1093 CodeGenAndEmitDAG();
1096 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1098 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1099 MachineBasicBlock *PHIBB = PHI->getParent();
1100 assert(PHI->isPHI() &&
1101 "This is not a machine PHI node that we are updating!");
1102 // "default" BB. We can go there only from header BB.
1103 if (PHIBB == SDB->JTCases[i].second.Default) {
1105 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1108 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1110 // JT BB. Just iterate over successors here
1111 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1113 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1115 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1119 SDB->JTCases.clear();
1121 // If the switch block involved a branch to one of the actual successors, we
1122 // need to update PHI nodes in that block.
1123 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1124 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1125 assert(PHI->isPHI() &&
1126 "This is not a machine PHI node that we are updating!");
1127 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1129 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1130 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1134 // If we generated any switch lowering information, build and codegen any
1135 // additional DAGs necessary.
1136 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1137 // Set the current basic block to the mbb we wish to insert the code into
1138 MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1139 FuncInfo->InsertPt = FuncInfo->MBB->end();
1141 // Determine the unique successors.
1142 SmallVector<MachineBasicBlock *, 2> Succs;
1143 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1144 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1145 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1147 // Emit the code. Note that this could result in ThisBB being split, so
1148 // we need to check for updates.
1149 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1150 CurDAG->setRoot(SDB->getRoot());
1152 CodeGenAndEmitDAG();
1153 ThisBB = FuncInfo->MBB;
1155 // Handle any PHI nodes in successors of this chunk, as if we were coming
1156 // from the original BB before switch expansion. Note that PHI nodes can
1157 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1158 // handle them the right number of times.
1159 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1160 FuncInfo->MBB = Succs[i];
1161 FuncInfo->InsertPt = FuncInfo->MBB->end();
1162 // FuncInfo->MBB may have been removed from the CFG if a branch was
1164 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1165 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1166 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1168 // This value for this PHI node is recorded in PHINodesToUpdate.
1169 for (unsigned pn = 0; ; ++pn) {
1170 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1171 "Didn't find PHI entry!");
1172 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1173 Phi->addOperand(MachineOperand::
1174 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1176 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1184 SDB->SwitchCases.clear();
1188 /// Create the scheduler. If a specific scheduler was specified
1189 /// via the SchedulerRegistry, use it, otherwise select the
1190 /// one preferred by the target.
1192 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1193 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1197 RegisterScheduler::setDefault(Ctor);
1200 return Ctor(this, OptLevel);
1203 //===----------------------------------------------------------------------===//
1204 // Helper functions used by the generated instruction selector.
1205 //===----------------------------------------------------------------------===//
1206 // Calls to these methods are generated by tblgen.
1208 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1209 /// the dag combiner simplified the 255, we still want to match. RHS is the
1210 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1211 /// specified in the .td file (e.g. 255).
1212 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1213 int64_t DesiredMaskS) const {
1214 const APInt &ActualMask = RHS->getAPIntValue();
1215 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1217 // If the actual mask exactly matches, success!
1218 if (ActualMask == DesiredMask)
1221 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1222 if (ActualMask.intersects(~DesiredMask))
1225 // Otherwise, the DAG Combiner may have proven that the value coming in is
1226 // either already zero or is not demanded. Check for known zero input bits.
1227 APInt NeededMask = DesiredMask & ~ActualMask;
1228 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1231 // TODO: check to see if missing bits are just not demanded.
1233 // Otherwise, this pattern doesn't match.
1237 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1238 /// the dag combiner simplified the 255, we still want to match. RHS is the
1239 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1240 /// specified in the .td file (e.g. 255).
1241 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1242 int64_t DesiredMaskS) const {
1243 const APInt &ActualMask = RHS->getAPIntValue();
1244 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1246 // If the actual mask exactly matches, success!
1247 if (ActualMask == DesiredMask)
1250 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1251 if (ActualMask.intersects(~DesiredMask))
1254 // Otherwise, the DAG Combiner may have proven that the value coming in is
1255 // either already zero or is not demanded. Check for known zero input bits.
1256 APInt NeededMask = DesiredMask & ~ActualMask;
1258 APInt KnownZero, KnownOne;
1259 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1261 // If all the missing bits in the or are already known to be set, match!
1262 if ((NeededMask & KnownOne) == NeededMask)
1265 // TODO: check to see if missing bits are just not demanded.
1267 // Otherwise, this pattern doesn't match.
1272 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1273 /// by tblgen. Others should not call it.
1274 void SelectionDAGISel::
1275 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1276 std::vector<SDValue> InOps;
1277 std::swap(InOps, Ops);
1279 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1280 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1281 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1282 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1284 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1285 if (InOps[e-1].getValueType() == MVT::Glue)
1286 --e; // Don't process a glue operand if it is here.
1289 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1290 if (!InlineAsm::isMemKind(Flags)) {
1291 // Just skip over this operand, copying the operands verbatim.
1292 Ops.insert(Ops.end(), InOps.begin()+i,
1293 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1294 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1296 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1297 "Memory operand with multiple values?");
1298 // Otherwise, this is a memory operand. Ask the target to select it.
1299 std::vector<SDValue> SelOps;
1300 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1301 report_fatal_error("Could not match memory address. Inline asm"
1304 // Add this to the output node.
1306 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1307 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1308 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1313 // Add the glue input back if present.
1314 if (e != InOps.size())
1315 Ops.push_back(InOps.back());
1318 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1321 static SDNode *findGlueUse(SDNode *N) {
1322 unsigned FlagResNo = N->getNumValues()-1;
1323 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1324 SDUse &Use = I.getUse();
1325 if (Use.getResNo() == FlagResNo)
1326 return Use.getUser();
1331 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1332 /// This function recursively traverses up the operand chain, ignoring
1334 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1335 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1336 bool IgnoreChains) {
1337 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1338 // greater than all of its (recursive) operands. If we scan to a point where
1339 // 'use' is smaller than the node we're scanning for, then we know we will
1342 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1343 // happen because we scan down to newly selected nodes in the case of glue
1345 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1348 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1349 // won't fail if we scan it again.
1350 if (!Visited.insert(Use))
1353 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1354 // Ignore chain uses, they are validated by HandleMergeInputChains.
1355 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1358 SDNode *N = Use->getOperand(i).getNode();
1360 if (Use == ImmedUse || Use == Root)
1361 continue; // We are not looking for immediate use.
1366 // Traverse up the operand chain.
1367 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1373 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1374 /// operand node N of U during instruction selection that starts at Root.
1375 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1376 SDNode *Root) const {
1377 if (OptLevel == CodeGenOpt::None) return false;
1378 return N.hasOneUse();
1381 /// IsLegalToFold - Returns true if the specific operand node N of
1382 /// U can be folded during instruction selection that starts at Root.
1383 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1384 CodeGenOpt::Level OptLevel,
1385 bool IgnoreChains) {
1386 if (OptLevel == CodeGenOpt::None) return false;
1388 // If Root use can somehow reach N through a path that that doesn't contain
1389 // U then folding N would create a cycle. e.g. In the following
1390 // diagram, Root can reach N through X. If N is folded into into Root, then
1391 // X is both a predecessor and a successor of U.
1402 // * indicates nodes to be folded together.
1404 // If Root produces glue, then it gets (even more) interesting. Since it
1405 // will be "glued" together with its glue use in the scheduler, we need to
1406 // check if it might reach N.
1425 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1426 // (call it Fold), then X is a predecessor of GU and a successor of
1427 // Fold. But since Fold and GU are glued together, this will create
1428 // a cycle in the scheduling graph.
1430 // If the node has glue, walk down the graph to the "lowest" node in the
1432 EVT VT = Root->getValueType(Root->getNumValues()-1);
1433 while (VT == MVT::Glue) {
1434 SDNode *GU = findGlueUse(Root);
1438 VT = Root->getValueType(Root->getNumValues()-1);
1440 // If our query node has a glue result with a use, we've walked up it. If
1441 // the user (which has already been selected) has a chain or indirectly uses
1442 // the chain, our WalkChainUsers predicate will not consider it. Because of
1443 // this, we cannot ignore chains in this predicate.
1444 IgnoreChains = false;
1448 SmallPtrSet<SDNode*, 16> Visited;
1449 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1452 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1453 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1454 SelectInlineAsmMemoryOperands(Ops);
1456 std::vector<EVT> VTs;
1457 VTs.push_back(MVT::Other);
1458 VTs.push_back(MVT::Glue);
1459 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1460 VTs, &Ops[0], Ops.size());
1462 return New.getNode();
1465 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1466 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1469 /// GetVBR - decode a vbr encoding whose top bit is set.
1470 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1471 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1472 assert(Val >= 128 && "Not a VBR");
1473 Val &= 127; // Remove first vbr bit.
1478 NextBits = MatcherTable[Idx++];
1479 Val |= (NextBits&127) << Shift;
1481 } while (NextBits & 128);
1487 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1488 /// interior glue and chain results to use the new glue and chain results.
1489 void SelectionDAGISel::
1490 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1491 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1493 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1494 bool isMorphNodeTo) {
1495 SmallVector<SDNode*, 4> NowDeadNodes;
1497 ISelUpdater ISU(ISelPosition);
1499 // Now that all the normal results are replaced, we replace the chain and
1500 // glue results if present.
1501 if (!ChainNodesMatched.empty()) {
1502 assert(InputChain.getNode() != 0 &&
1503 "Matched input chains but didn't produce a chain");
1504 // Loop over all of the nodes we matched that produced a chain result.
1505 // Replace all the chain results with the final chain we ended up with.
1506 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1507 SDNode *ChainNode = ChainNodesMatched[i];
1509 // If this node was already deleted, don't look at it.
1510 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1513 // Don't replace the results of the root node if we're doing a
1515 if (ChainNode == NodeToMatch && isMorphNodeTo)
1518 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1519 if (ChainVal.getValueType() == MVT::Glue)
1520 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1521 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1522 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1524 // If the node became dead and we haven't already seen it, delete it.
1525 if (ChainNode->use_empty() &&
1526 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1527 NowDeadNodes.push_back(ChainNode);
1531 // If the result produces glue, update any glue results in the matched
1532 // pattern with the glue result.
1533 if (InputGlue.getNode() != 0) {
1534 // Handle any interior nodes explicitly marked.
1535 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1536 SDNode *FRN = GlueResultNodesMatched[i];
1538 // If this node was already deleted, don't look at it.
1539 if (FRN->getOpcode() == ISD::DELETED_NODE)
1542 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1543 "Doesn't have a glue result");
1544 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1547 // If the node became dead and we haven't already seen it, delete it.
1548 if (FRN->use_empty() &&
1549 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1550 NowDeadNodes.push_back(FRN);
1554 if (!NowDeadNodes.empty())
1555 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1557 DEBUG(errs() << "ISEL: Match complete!\n");
1563 CR_LeadsToInteriorNode
1566 /// WalkChainUsers - Walk down the users of the specified chained node that is
1567 /// part of the pattern we're matching, looking at all of the users we find.
1568 /// This determines whether something is an interior node, whether we have a
1569 /// non-pattern node in between two pattern nodes (which prevent folding because
1570 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1571 /// between pattern nodes (in which case the TF becomes part of the pattern).
1573 /// The walk we do here is guaranteed to be small because we quickly get down to
1574 /// already selected nodes "below" us.
1576 WalkChainUsers(SDNode *ChainedNode,
1577 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1578 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1579 ChainResult Result = CR_Simple;
1581 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1582 E = ChainedNode->use_end(); UI != E; ++UI) {
1583 // Make sure the use is of the chain, not some other value we produce.
1584 if (UI.getUse().getValueType() != MVT::Other) continue;
1588 // If we see an already-selected machine node, then we've gone beyond the
1589 // pattern that we're selecting down into the already selected chunk of the
1591 if (User->isMachineOpcode() ||
1592 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1595 if (User->getOpcode() == ISD::CopyToReg ||
1596 User->getOpcode() == ISD::CopyFromReg ||
1597 User->getOpcode() == ISD::INLINEASM ||
1598 User->getOpcode() == ISD::EH_LABEL) {
1599 // If their node ID got reset to -1 then they've already been selected.
1600 // Treat them like a MachineOpcode.
1601 if (User->getNodeId() == -1)
1605 // If we have a TokenFactor, we handle it specially.
1606 if (User->getOpcode() != ISD::TokenFactor) {
1607 // If the node isn't a token factor and isn't part of our pattern, then it
1608 // must be a random chained node in between two nodes we're selecting.
1609 // This happens when we have something like:
1614 // Because we structurally match the load/store as a read/modify/write,
1615 // but the call is chained between them. We cannot fold in this case
1616 // because it would induce a cycle in the graph.
1617 if (!std::count(ChainedNodesInPattern.begin(),
1618 ChainedNodesInPattern.end(), User))
1619 return CR_InducesCycle;
1621 // Otherwise we found a node that is part of our pattern. For example in:
1625 // This would happen when we're scanning down from the load and see the
1626 // store as a user. Record that there is a use of ChainedNode that is
1627 // part of the pattern and keep scanning uses.
1628 Result = CR_LeadsToInteriorNode;
1629 InteriorChainedNodes.push_back(User);
1633 // If we found a TokenFactor, there are two cases to consider: first if the
1634 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1635 // uses of the TF are in our pattern) we just want to ignore it. Second,
1636 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1642 // | \ DAG's like cheese
1645 // [TokenFactor] [Op]
1652 // In this case, the TokenFactor becomes part of our match and we rewrite it
1653 // as a new TokenFactor.
1655 // To distinguish these two cases, do a recursive walk down the uses.
1656 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1658 // If the uses of the TokenFactor are just already-selected nodes, ignore
1659 // it, it is "below" our pattern.
1661 case CR_InducesCycle:
1662 // If the uses of the TokenFactor lead to nodes that are not part of our
1663 // pattern that are not selected, folding would turn this into a cycle,
1665 return CR_InducesCycle;
1666 case CR_LeadsToInteriorNode:
1667 break; // Otherwise, keep processing.
1670 // Okay, we know we're in the interesting interior case. The TokenFactor
1671 // is now going to be considered part of the pattern so that we rewrite its
1672 // uses (it may have uses that are not part of the pattern) with the
1673 // ultimate chain result of the generated code. We will also add its chain
1674 // inputs as inputs to the ultimate TokenFactor we create.
1675 Result = CR_LeadsToInteriorNode;
1676 ChainedNodesInPattern.push_back(User);
1677 InteriorChainedNodes.push_back(User);
1684 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1685 /// operation for when the pattern matched at least one node with a chains. The
1686 /// input vector contains a list of all of the chained nodes that we match. We
1687 /// must determine if this is a valid thing to cover (i.e. matching it won't
1688 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1689 /// be used as the input node chain for the generated nodes.
1691 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1692 SelectionDAG *CurDAG) {
1693 // Walk all of the chained nodes we've matched, recursively scanning down the
1694 // users of the chain result. This adds any TokenFactor nodes that are caught
1695 // in between chained nodes to the chained and interior nodes list.
1696 SmallVector<SDNode*, 3> InteriorChainedNodes;
1697 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1698 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1699 InteriorChainedNodes) == CR_InducesCycle)
1700 return SDValue(); // Would induce a cycle.
1703 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1704 // that we are interested in. Form our input TokenFactor node.
1705 SmallVector<SDValue, 3> InputChains;
1706 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1707 // Add the input chain of this node to the InputChains list (which will be
1708 // the operands of the generated TokenFactor) if it's not an interior node.
1709 SDNode *N = ChainNodesMatched[i];
1710 if (N->getOpcode() != ISD::TokenFactor) {
1711 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1714 // Otherwise, add the input chain.
1715 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1716 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1717 InputChains.push_back(InChain);
1721 // If we have a token factor, we want to add all inputs of the token factor
1722 // that are not part of the pattern we're matching.
1723 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1724 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1725 N->getOperand(op).getNode()))
1726 InputChains.push_back(N->getOperand(op));
1731 if (InputChains.size() == 1)
1732 return InputChains[0];
1733 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1734 MVT::Other, &InputChains[0], InputChains.size());
1737 /// MorphNode - Handle morphing a node in place for the selector.
1738 SDNode *SelectionDAGISel::
1739 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1740 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1741 // It is possible we're using MorphNodeTo to replace a node with no
1742 // normal results with one that has a normal result (or we could be
1743 // adding a chain) and the input could have glue and chains as well.
1744 // In this case we need to shift the operands down.
1745 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1746 // than the old isel though.
1747 int OldGlueResultNo = -1, OldChainResultNo = -1;
1749 unsigned NTMNumResults = Node->getNumValues();
1750 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1751 OldGlueResultNo = NTMNumResults-1;
1752 if (NTMNumResults != 1 &&
1753 Node->getValueType(NTMNumResults-2) == MVT::Other)
1754 OldChainResultNo = NTMNumResults-2;
1755 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1756 OldChainResultNo = NTMNumResults-1;
1758 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1759 // that this deletes operands of the old node that become dead.
1760 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1762 // MorphNodeTo can operate in two ways: if an existing node with the
1763 // specified operands exists, it can just return it. Otherwise, it
1764 // updates the node in place to have the requested operands.
1766 // If we updated the node in place, reset the node ID. To the isel,
1767 // this should be just like a newly allocated machine node.
1771 unsigned ResNumResults = Res->getNumValues();
1772 // Move the glue if needed.
1773 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1774 (unsigned)OldGlueResultNo != ResNumResults-1)
1775 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1776 SDValue(Res, ResNumResults-1));
1778 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1781 // Move the chain reference if needed.
1782 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1783 (unsigned)OldChainResultNo != ResNumResults-1)
1784 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1785 SDValue(Res, ResNumResults-1));
1787 // Otherwise, no replacement happened because the node already exists. Replace
1788 // Uses of the old node with the new one.
1790 CurDAG->ReplaceAllUsesWith(Node, Res);
1795 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1796 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1797 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1799 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1800 // Accept if it is exactly the same as a previously recorded node.
1801 unsigned RecNo = MatcherTable[MatcherIndex++];
1802 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1803 return N == RecordedNodes[RecNo].first;
1806 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1807 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1808 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1809 SelectionDAGISel &SDISel) {
1810 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1813 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1814 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1815 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1816 SelectionDAGISel &SDISel, SDNode *N) {
1817 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1820 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1821 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1823 uint16_t Opc = MatcherTable[MatcherIndex++];
1824 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1825 return N->getOpcode() == Opc;
1828 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1829 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1830 SDValue N, const TargetLowering &TLI) {
1831 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1832 if (N.getValueType() == VT) return true;
1834 // Handle the case when VT is iPTR.
1835 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1838 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1839 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1840 SDValue N, const TargetLowering &TLI,
1842 if (ChildNo >= N.getNumOperands())
1843 return false; // Match fails if out of range child #.
1844 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1848 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1849 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1851 return cast<CondCodeSDNode>(N)->get() ==
1852 (ISD::CondCode)MatcherTable[MatcherIndex++];
1855 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1856 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1857 SDValue N, const TargetLowering &TLI) {
1858 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1859 if (cast<VTSDNode>(N)->getVT() == VT)
1862 // Handle the case when VT is iPTR.
1863 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1866 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1867 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1869 int64_t Val = MatcherTable[MatcherIndex++];
1871 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1873 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1874 return C != 0 && C->getSExtValue() == Val;
1877 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1878 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1879 SDValue N, SelectionDAGISel &SDISel) {
1880 int64_t Val = MatcherTable[MatcherIndex++];
1882 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1884 if (N->getOpcode() != ISD::AND) return false;
1886 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1887 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1890 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1891 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1892 SDValue N, SelectionDAGISel &SDISel) {
1893 int64_t Val = MatcherTable[MatcherIndex++];
1895 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1897 if (N->getOpcode() != ISD::OR) return false;
1899 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1900 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1903 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1904 /// scope, evaluate the current node. If the current predicate is known to
1905 /// fail, set Result=true and return anything. If the current predicate is
1906 /// known to pass, set Result=false and return the MatcherIndex to continue
1907 /// with. If the current predicate is unknown, set Result=false and return the
1908 /// MatcherIndex to continue with.
1909 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1910 unsigned Index, SDValue N,
1911 bool &Result, SelectionDAGISel &SDISel,
1912 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1913 switch (Table[Index++]) {
1916 return Index-1; // Could not evaluate this predicate.
1917 case SelectionDAGISel::OPC_CheckSame:
1918 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1920 case SelectionDAGISel::OPC_CheckPatternPredicate:
1921 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1923 case SelectionDAGISel::OPC_CheckPredicate:
1924 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1926 case SelectionDAGISel::OPC_CheckOpcode:
1927 Result = !::CheckOpcode(Table, Index, N.getNode());
1929 case SelectionDAGISel::OPC_CheckType:
1930 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1932 case SelectionDAGISel::OPC_CheckChild0Type:
1933 case SelectionDAGISel::OPC_CheckChild1Type:
1934 case SelectionDAGISel::OPC_CheckChild2Type:
1935 case SelectionDAGISel::OPC_CheckChild3Type:
1936 case SelectionDAGISel::OPC_CheckChild4Type:
1937 case SelectionDAGISel::OPC_CheckChild5Type:
1938 case SelectionDAGISel::OPC_CheckChild6Type:
1939 case SelectionDAGISel::OPC_CheckChild7Type:
1940 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1941 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1943 case SelectionDAGISel::OPC_CheckCondCode:
1944 Result = !::CheckCondCode(Table, Index, N);
1946 case SelectionDAGISel::OPC_CheckValueType:
1947 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1949 case SelectionDAGISel::OPC_CheckInteger:
1950 Result = !::CheckInteger(Table, Index, N);
1952 case SelectionDAGISel::OPC_CheckAndImm:
1953 Result = !::CheckAndImm(Table, Index, N, SDISel);
1955 case SelectionDAGISel::OPC_CheckOrImm:
1956 Result = !::CheckOrImm(Table, Index, N, SDISel);
1964 /// FailIndex - If this match fails, this is the index to continue with.
1967 /// NodeStack - The node stack when the scope was formed.
1968 SmallVector<SDValue, 4> NodeStack;
1970 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1971 unsigned NumRecordedNodes;
1973 /// NumMatchedMemRefs - The number of matched memref entries.
1974 unsigned NumMatchedMemRefs;
1976 /// InputChain/InputGlue - The current chain/glue
1977 SDValue InputChain, InputGlue;
1979 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1980 bool HasChainNodesMatched, HasGlueResultNodesMatched;
1985 SDNode *SelectionDAGISel::
1986 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1987 unsigned TableSize) {
1988 // FIXME: Should these even be selected? Handle these cases in the caller?
1989 switch (NodeToMatch->getOpcode()) {
1992 case ISD::EntryToken: // These nodes remain the same.
1993 case ISD::BasicBlock:
1995 //case ISD::VALUETYPE:
1996 //case ISD::CONDCODE:
1997 case ISD::HANDLENODE:
1998 case ISD::MDNODE_SDNODE:
1999 case ISD::TargetConstant:
2000 case ISD::TargetConstantFP:
2001 case ISD::TargetConstantPool:
2002 case ISD::TargetFrameIndex:
2003 case ISD::TargetExternalSymbol:
2004 case ISD::TargetBlockAddress:
2005 case ISD::TargetJumpTable:
2006 case ISD::TargetGlobalTLSAddress:
2007 case ISD::TargetGlobalAddress:
2008 case ISD::TokenFactor:
2009 case ISD::CopyFromReg:
2010 case ISD::CopyToReg:
2012 NodeToMatch->setNodeId(-1); // Mark selected.
2014 case ISD::AssertSext:
2015 case ISD::AssertZext:
2016 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2017 NodeToMatch->getOperand(0));
2019 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2020 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2023 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2025 // Set up the node stack with NodeToMatch as the only node on the stack.
2026 SmallVector<SDValue, 8> NodeStack;
2027 SDValue N = SDValue(NodeToMatch, 0);
2028 NodeStack.push_back(N);
2030 // MatchScopes - Scopes used when matching, if a match failure happens, this
2031 // indicates where to continue checking.
2032 SmallVector<MatchScope, 8> MatchScopes;
2034 // RecordedNodes - This is the set of nodes that have been recorded by the
2035 // state machine. The second value is the parent of the node, or null if the
2036 // root is recorded.
2037 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2039 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2041 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2043 // These are the current input chain and glue for use when generating nodes.
2044 // Various Emit operations change these. For example, emitting a copytoreg
2045 // uses and updates these.
2046 SDValue InputChain, InputGlue;
2048 // ChainNodesMatched - If a pattern matches nodes that have input/output
2049 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2050 // which ones they are. The result is captured into this list so that we can
2051 // update the chain results when the pattern is complete.
2052 SmallVector<SDNode*, 3> ChainNodesMatched;
2053 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2055 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2056 NodeToMatch->dump(CurDAG);
2059 // Determine where to start the interpreter. Normally we start at opcode #0,
2060 // but if the state machine starts with an OPC_SwitchOpcode, then we
2061 // accelerate the first lookup (which is guaranteed to be hot) with the
2062 // OpcodeOffset table.
2063 unsigned MatcherIndex = 0;
2065 if (!OpcodeOffset.empty()) {
2066 // Already computed the OpcodeOffset table, just index into it.
2067 if (N.getOpcode() < OpcodeOffset.size())
2068 MatcherIndex = OpcodeOffset[N.getOpcode()];
2069 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2071 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2072 // Otherwise, the table isn't computed, but the state machine does start
2073 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2074 // is the first time we're selecting an instruction.
2077 // Get the size of this case.
2078 unsigned CaseSize = MatcherTable[Idx++];
2080 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2081 if (CaseSize == 0) break;
2083 // Get the opcode, add the index to the table.
2084 uint16_t Opc = MatcherTable[Idx++];
2085 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2086 if (Opc >= OpcodeOffset.size())
2087 OpcodeOffset.resize((Opc+1)*2);
2088 OpcodeOffset[Opc] = Idx;
2092 // Okay, do the lookup for the first opcode.
2093 if (N.getOpcode() < OpcodeOffset.size())
2094 MatcherIndex = OpcodeOffset[N.getOpcode()];
2098 assert(MatcherIndex < TableSize && "Invalid index");
2100 unsigned CurrentOpcodeIndex = MatcherIndex;
2102 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2105 // Okay, the semantics of this operation are that we should push a scope
2106 // then evaluate the first child. However, pushing a scope only to have
2107 // the first check fail (which then pops it) is inefficient. If we can
2108 // determine immediately that the first check (or first several) will
2109 // immediately fail, don't even bother pushing a scope for them.
2113 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2114 if (NumToSkip & 128)
2115 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2116 // Found the end of the scope with no match.
2117 if (NumToSkip == 0) {
2122 FailIndex = MatcherIndex+NumToSkip;
2124 unsigned MatcherIndexOfPredicate = MatcherIndex;
2125 (void)MatcherIndexOfPredicate; // silence warning.
2127 // If we can't evaluate this predicate without pushing a scope (e.g. if
2128 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2129 // push the scope and evaluate the full predicate chain.
2131 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2132 Result, *this, RecordedNodes);
2136 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2137 << "index " << MatcherIndexOfPredicate
2138 << ", continuing at " << FailIndex << "\n");
2139 ++NumDAGIselRetries;
2141 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2142 // move to the next case.
2143 MatcherIndex = FailIndex;
2146 // If the whole scope failed to match, bail.
2147 if (FailIndex == 0) break;
2149 // Push a MatchScope which indicates where to go if the first child fails
2151 MatchScope NewEntry;
2152 NewEntry.FailIndex = FailIndex;
2153 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2154 NewEntry.NumRecordedNodes = RecordedNodes.size();
2155 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2156 NewEntry.InputChain = InputChain;
2157 NewEntry.InputGlue = InputGlue;
2158 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2159 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2160 MatchScopes.push_back(NewEntry);
2163 case OPC_RecordNode: {
2164 // Remember this node, it may end up being an operand in the pattern.
2166 if (NodeStack.size() > 1)
2167 Parent = NodeStack[NodeStack.size()-2].getNode();
2168 RecordedNodes.push_back(std::make_pair(N, Parent));
2172 case OPC_RecordChild0: case OPC_RecordChild1:
2173 case OPC_RecordChild2: case OPC_RecordChild3:
2174 case OPC_RecordChild4: case OPC_RecordChild5:
2175 case OPC_RecordChild6: case OPC_RecordChild7: {
2176 unsigned ChildNo = Opcode-OPC_RecordChild0;
2177 if (ChildNo >= N.getNumOperands())
2178 break; // Match fails if out of range child #.
2180 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2184 case OPC_RecordMemRef:
2185 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2188 case OPC_CaptureGlueInput:
2189 // If the current node has an input glue, capture it in InputGlue.
2190 if (N->getNumOperands() != 0 &&
2191 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2192 InputGlue = N->getOperand(N->getNumOperands()-1);
2195 case OPC_MoveChild: {
2196 unsigned ChildNo = MatcherTable[MatcherIndex++];
2197 if (ChildNo >= N.getNumOperands())
2198 break; // Match fails if out of range child #.
2199 N = N.getOperand(ChildNo);
2200 NodeStack.push_back(N);
2204 case OPC_MoveParent:
2205 // Pop the current node off the NodeStack.
2206 NodeStack.pop_back();
2207 assert(!NodeStack.empty() && "Node stack imbalance!");
2208 N = NodeStack.back();
2212 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2214 case OPC_CheckPatternPredicate:
2215 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2217 case OPC_CheckPredicate:
2218 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2222 case OPC_CheckComplexPat: {
2223 unsigned CPNum = MatcherTable[MatcherIndex++];
2224 unsigned RecNo = MatcherTable[MatcherIndex++];
2225 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2226 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2227 RecordedNodes[RecNo].first, CPNum,
2232 case OPC_CheckOpcode:
2233 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2237 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2240 case OPC_SwitchOpcode: {
2241 unsigned CurNodeOpcode = N.getOpcode();
2242 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2245 // Get the size of this case.
2246 CaseSize = MatcherTable[MatcherIndex++];
2248 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2249 if (CaseSize == 0) break;
2251 uint16_t Opc = MatcherTable[MatcherIndex++];
2252 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2254 // If the opcode matches, then we will execute this case.
2255 if (CurNodeOpcode == Opc)
2258 // Otherwise, skip over this case.
2259 MatcherIndex += CaseSize;
2262 // If no cases matched, bail out.
2263 if (CaseSize == 0) break;
2265 // Otherwise, execute the case we found.
2266 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2267 << " to " << MatcherIndex << "\n");
2271 case OPC_SwitchType: {
2272 MVT CurNodeVT = N.getValueType().getSimpleVT();
2273 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2276 // Get the size of this case.
2277 CaseSize = MatcherTable[MatcherIndex++];
2279 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2280 if (CaseSize == 0) break;
2282 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2283 if (CaseVT == MVT::iPTR)
2284 CaseVT = TLI.getPointerTy();
2286 // If the VT matches, then we will execute this case.
2287 if (CurNodeVT == CaseVT)
2290 // Otherwise, skip over this case.
2291 MatcherIndex += CaseSize;
2294 // If no cases matched, bail out.
2295 if (CaseSize == 0) break;
2297 // Otherwise, execute the case we found.
2298 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2299 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2302 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2303 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2304 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2305 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2306 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2307 Opcode-OPC_CheckChild0Type))
2310 case OPC_CheckCondCode:
2311 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2313 case OPC_CheckValueType:
2314 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2316 case OPC_CheckInteger:
2317 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2319 case OPC_CheckAndImm:
2320 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2322 case OPC_CheckOrImm:
2323 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2326 case OPC_CheckFoldableChainNode: {
2327 assert(NodeStack.size() != 1 && "No parent node");
2328 // Verify that all intermediate nodes between the root and this one have
2330 bool HasMultipleUses = false;
2331 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2332 if (!NodeStack[i].hasOneUse()) {
2333 HasMultipleUses = true;
2336 if (HasMultipleUses) break;
2338 // Check to see that the target thinks this is profitable to fold and that
2339 // we can fold it without inducing cycles in the graph.
2340 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2342 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2343 NodeToMatch, OptLevel,
2344 true/*We validate our own chains*/))
2349 case OPC_EmitInteger: {
2350 MVT::SimpleValueType VT =
2351 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2352 int64_t Val = MatcherTable[MatcherIndex++];
2354 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2355 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2356 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2359 case OPC_EmitRegister: {
2360 MVT::SimpleValueType VT =
2361 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2362 unsigned RegNo = MatcherTable[MatcherIndex++];
2363 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2364 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2368 case OPC_EmitConvertToTarget: {
2369 // Convert from IMM/FPIMM to target version.
2370 unsigned RecNo = MatcherTable[MatcherIndex++];
2371 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2372 SDValue Imm = RecordedNodes[RecNo].first;
2374 if (Imm->getOpcode() == ISD::Constant) {
2375 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2376 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2377 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2378 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2379 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2382 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2386 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2387 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2388 // These are space-optimized forms of OPC_EmitMergeInputChains.
2389 assert(InputChain.getNode() == 0 &&
2390 "EmitMergeInputChains should be the first chain producing node");
2391 assert(ChainNodesMatched.empty() &&
2392 "Should only have one EmitMergeInputChains per match");
2394 // Read all of the chained nodes.
2395 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2396 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2397 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2399 // FIXME: What if other value results of the node have uses not matched
2401 if (ChainNodesMatched.back() != NodeToMatch &&
2402 !RecordedNodes[RecNo].first.hasOneUse()) {
2403 ChainNodesMatched.clear();
2407 // Merge the input chains if they are not intra-pattern references.
2408 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2410 if (InputChain.getNode() == 0)
2411 break; // Failed to merge.
2415 case OPC_EmitMergeInputChains: {
2416 assert(InputChain.getNode() == 0 &&
2417 "EmitMergeInputChains should be the first chain producing node");
2418 // This node gets a list of nodes we matched in the input that have
2419 // chains. We want to token factor all of the input chains to these nodes
2420 // together. However, if any of the input chains is actually one of the
2421 // nodes matched in this pattern, then we have an intra-match reference.
2422 // Ignore these because the newly token factored chain should not refer to
2424 unsigned NumChains = MatcherTable[MatcherIndex++];
2425 assert(NumChains != 0 && "Can't TF zero chains");
2427 assert(ChainNodesMatched.empty() &&
2428 "Should only have one EmitMergeInputChains per match");
2430 // Read all of the chained nodes.
2431 for (unsigned i = 0; i != NumChains; ++i) {
2432 unsigned RecNo = MatcherTable[MatcherIndex++];
2433 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2434 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2436 // FIXME: What if other value results of the node have uses not matched
2438 if (ChainNodesMatched.back() != NodeToMatch &&
2439 !RecordedNodes[RecNo].first.hasOneUse()) {
2440 ChainNodesMatched.clear();
2445 // If the inner loop broke out, the match fails.
2446 if (ChainNodesMatched.empty())
2449 // Merge the input chains if they are not intra-pattern references.
2450 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2452 if (InputChain.getNode() == 0)
2453 break; // Failed to merge.
2458 case OPC_EmitCopyToReg: {
2459 unsigned RecNo = MatcherTable[MatcherIndex++];
2460 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2461 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2463 if (InputChain.getNode() == 0)
2464 InputChain = CurDAG->getEntryNode();
2466 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2467 DestPhysReg, RecordedNodes[RecNo].first,
2470 InputGlue = InputChain.getValue(1);
2474 case OPC_EmitNodeXForm: {
2475 unsigned XFormNo = MatcherTable[MatcherIndex++];
2476 unsigned RecNo = MatcherTable[MatcherIndex++];
2477 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2478 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2479 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2484 case OPC_MorphNodeTo: {
2485 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2486 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2487 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2488 // Get the result VT list.
2489 unsigned NumVTs = MatcherTable[MatcherIndex++];
2490 SmallVector<EVT, 4> VTs;
2491 for (unsigned i = 0; i != NumVTs; ++i) {
2492 MVT::SimpleValueType VT =
2493 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2494 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2498 if (EmitNodeInfo & OPFL_Chain)
2499 VTs.push_back(MVT::Other);
2500 if (EmitNodeInfo & OPFL_GlueOutput)
2501 VTs.push_back(MVT::Glue);
2503 // This is hot code, so optimize the two most common cases of 1 and 2
2506 if (VTs.size() == 1)
2507 VTList = CurDAG->getVTList(VTs[0]);
2508 else if (VTs.size() == 2)
2509 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2511 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2513 // Get the operand list.
2514 unsigned NumOps = MatcherTable[MatcherIndex++];
2515 SmallVector<SDValue, 8> Ops;
2516 for (unsigned i = 0; i != NumOps; ++i) {
2517 unsigned RecNo = MatcherTable[MatcherIndex++];
2519 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2521 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2522 Ops.push_back(RecordedNodes[RecNo].first);
2525 // If there are variadic operands to add, handle them now.
2526 if (EmitNodeInfo & OPFL_VariadicInfo) {
2527 // Determine the start index to copy from.
2528 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2529 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2530 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2531 "Invalid variadic node");
2532 // Copy all of the variadic operands, not including a potential glue
2534 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2536 SDValue V = NodeToMatch->getOperand(i);
2537 if (V.getValueType() == MVT::Glue) break;
2542 // If this has chain/glue inputs, add them.
2543 if (EmitNodeInfo & OPFL_Chain)
2544 Ops.push_back(InputChain);
2545 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2546 Ops.push_back(InputGlue);
2550 if (Opcode != OPC_MorphNodeTo) {
2551 // If this is a normal EmitNode command, just create the new node and
2552 // add the results to the RecordedNodes list.
2553 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2554 VTList, Ops.data(), Ops.size());
2556 // Add all the non-glue/non-chain results to the RecordedNodes list.
2557 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2558 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2559 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2564 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2568 // If the node had chain/glue results, update our notion of the current
2570 if (EmitNodeInfo & OPFL_GlueOutput) {
2571 InputGlue = SDValue(Res, VTs.size()-1);
2572 if (EmitNodeInfo & OPFL_Chain)
2573 InputChain = SDValue(Res, VTs.size()-2);
2574 } else if (EmitNodeInfo & OPFL_Chain)
2575 InputChain = SDValue(Res, VTs.size()-1);
2577 // If the OPFL_MemRefs glue is set on this node, slap all of the
2578 // accumulated memrefs onto it.
2580 // FIXME: This is vastly incorrect for patterns with multiple outputs
2581 // instructions that access memory and for ComplexPatterns that match
2583 if (EmitNodeInfo & OPFL_MemRefs) {
2584 MachineSDNode::mmo_iterator MemRefs =
2585 MF->allocateMemRefsArray(MatchedMemRefs.size());
2586 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2587 cast<MachineSDNode>(Res)
2588 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2592 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2593 << " node: "; Res->dump(CurDAG); errs() << "\n");
2595 // If this was a MorphNodeTo then we're completely done!
2596 if (Opcode == OPC_MorphNodeTo) {
2597 // Update chain and glue uses.
2598 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2599 InputGlue, GlueResultNodesMatched, true);
2606 case OPC_MarkGlueResults: {
2607 unsigned NumNodes = MatcherTable[MatcherIndex++];
2609 // Read and remember all the glue-result nodes.
2610 for (unsigned i = 0; i != NumNodes; ++i) {
2611 unsigned RecNo = MatcherTable[MatcherIndex++];
2613 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2615 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2616 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2621 case OPC_CompleteMatch: {
2622 // The match has been completed, and any new nodes (if any) have been
2623 // created. Patch up references to the matched dag to use the newly
2625 unsigned NumResults = MatcherTable[MatcherIndex++];
2627 for (unsigned i = 0; i != NumResults; ++i) {
2628 unsigned ResSlot = MatcherTable[MatcherIndex++];
2630 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2632 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2633 SDValue Res = RecordedNodes[ResSlot].first;
2635 assert(i < NodeToMatch->getNumValues() &&
2636 NodeToMatch->getValueType(i) != MVT::Other &&
2637 NodeToMatch->getValueType(i) != MVT::Glue &&
2638 "Invalid number of results to complete!");
2639 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2640 NodeToMatch->getValueType(i) == MVT::iPTR ||
2641 Res.getValueType() == MVT::iPTR ||
2642 NodeToMatch->getValueType(i).getSizeInBits() ==
2643 Res.getValueType().getSizeInBits()) &&
2644 "invalid replacement");
2645 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2648 // If the root node defines glue, add it to the glue nodes to update list.
2649 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2650 GlueResultNodesMatched.push_back(NodeToMatch);
2652 // Update chain and glue uses.
2653 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2654 InputGlue, GlueResultNodesMatched, false);
2656 assert(NodeToMatch->use_empty() &&
2657 "Didn't replace all uses of the node?");
2659 // FIXME: We just return here, which interacts correctly with SelectRoot
2660 // above. We should fix this to not return an SDNode* anymore.
2665 // If the code reached this point, then the match failed. See if there is
2666 // another child to try in the current 'Scope', otherwise pop it until we
2667 // find a case to check.
2668 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2669 ++NumDAGIselRetries;
2671 if (MatchScopes.empty()) {
2672 CannotYetSelect(NodeToMatch);
2676 // Restore the interpreter state back to the point where the scope was
2678 MatchScope &LastScope = MatchScopes.back();
2679 RecordedNodes.resize(LastScope.NumRecordedNodes);
2681 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2682 N = NodeStack.back();
2684 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2685 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2686 MatcherIndex = LastScope.FailIndex;
2688 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2690 InputChain = LastScope.InputChain;
2691 InputGlue = LastScope.InputGlue;
2692 if (!LastScope.HasChainNodesMatched)
2693 ChainNodesMatched.clear();
2694 if (!LastScope.HasGlueResultNodesMatched)
2695 GlueResultNodesMatched.clear();
2697 // Check to see what the offset is at the new MatcherIndex. If it is zero
2698 // we have reached the end of this scope, otherwise we have another child
2699 // in the current scope to try.
2700 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2701 if (NumToSkip & 128)
2702 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2704 // If we have another child in this scope to match, update FailIndex and
2706 if (NumToSkip != 0) {
2707 LastScope.FailIndex = MatcherIndex+NumToSkip;
2711 // End of this scope, pop it and try the next child in the containing
2713 MatchScopes.pop_back();
2720 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2722 raw_string_ostream Msg(msg);
2723 Msg << "Cannot select: ";
2725 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2726 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2727 N->getOpcode() != ISD::INTRINSIC_VOID) {
2728 N->printrFull(Msg, CurDAG);
2730 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2732 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2733 if (iid < Intrinsic::num_intrinsics)
2734 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2735 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2736 Msg << "target intrinsic %" << TII->getName(iid);
2738 Msg << "unknown intrinsic #" << iid;
2740 report_fatal_error(Msg.str());
2743 char SelectionDAGISel::ID = 0;