1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/GCStrategy.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/LibCallSemantics.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SelectionDAGISel.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DebugInfo.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/InlineAsm.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/IntrinsicInst.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/IR/LLVMContext.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/MC/MCAsmInfo.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/Timer.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetIntrinsicInfo.h"
55 #include "llvm/Target/TargetLowering.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include "llvm/Target/TargetOptions.h"
58 #include "llvm/Target/TargetRegisterInfo.h"
59 #include "llvm/Target/TargetSubtargetInfo.h"
60 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
64 #define DEBUG_TYPE "isel"
66 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
67 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
68 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
69 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
70 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
71 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
72 STATISTIC(NumFastIselFailLowerArguments,
73 "Number of entry blocks where fast isel failed to lower arguments");
77 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
78 cl::desc("Enable extra verbose messages in the \"fast\" "
79 "instruction selector"));
82 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
83 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
84 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
85 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
86 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
87 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
88 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
90 // Standard binary operators...
91 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
92 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
93 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
94 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
95 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
96 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
97 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
98 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
99 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
100 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
101 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
102 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
104 // Logical operators...
105 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
106 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
107 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
109 // Memory instructions...
110 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
111 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
112 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
113 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
114 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
115 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
116 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
118 // Convert instructions...
119 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
120 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
121 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
122 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
123 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
124 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
125 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
126 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
127 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
128 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
129 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
130 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
132 // Other instructions...
133 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
134 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
135 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
136 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
137 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
138 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
139 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
140 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
141 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
142 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
143 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
144 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
145 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
146 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
147 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
149 // Intrinsic instructions...
150 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
151 STATISTIC(NumFastIselFailSAddWithOverflow,
152 "Fast isel fails on sadd.with.overflow");
153 STATISTIC(NumFastIselFailUAddWithOverflow,
154 "Fast isel fails on uadd.with.overflow");
155 STATISTIC(NumFastIselFailSSubWithOverflow,
156 "Fast isel fails on ssub.with.overflow");
157 STATISTIC(NumFastIselFailUSubWithOverflow,
158 "Fast isel fails on usub.with.overflow");
159 STATISTIC(NumFastIselFailSMulWithOverflow,
160 "Fast isel fails on smul.with.overflow");
161 STATISTIC(NumFastIselFailUMulWithOverflow,
162 "Fast isel fails on umul.with.overflow");
163 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
164 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
165 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
166 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
170 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
171 cl::desc("Enable verbose messages in the \"fast\" "
172 "instruction selector"));
173 static cl::opt<int> EnableFastISelAbort(
174 "fast-isel-abort", cl::Hidden,
175 cl::desc("Enable abort calls when \"fast\" instruction selection "
176 "fails to lower an instruction: 0 disable the abort, 1 will "
177 "abort but for args, calls and terminators, 2 will also "
178 "abort for argument lowering, and 3 will never fallback "
179 "to SelectionDAG."));
183 cl::desc("use Machine Branch Probability Info"),
184 cl::init(true), cl::Hidden);
187 static cl::opt<std::string>
188 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
189 cl::desc("Only display the basic block whose name "
190 "matches this for all view-*-dags options"));
192 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
193 cl::desc("Pop up a window to show dags before the first "
194 "dag combine pass"));
196 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
197 cl::desc("Pop up a window to show dags before legalize types"));
199 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
200 cl::desc("Pop up a window to show dags before legalize"));
202 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
203 cl::desc("Pop up a window to show dags before the second "
204 "dag combine pass"));
206 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
207 cl::desc("Pop up a window to show dags before the post legalize types"
208 " dag combine pass"));
210 ViewISelDAGs("view-isel-dags", cl::Hidden,
211 cl::desc("Pop up a window to show isel dags as they are selected"));
213 ViewSchedDAGs("view-sched-dags", cl::Hidden,
214 cl::desc("Pop up a window to show sched dags as they are processed"));
216 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
217 cl::desc("Pop up a window to show SUnit dags after they are processed"));
219 static const bool ViewDAGCombine1 = false,
220 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
221 ViewDAGCombine2 = false,
222 ViewDAGCombineLT = false,
223 ViewISelDAGs = false, ViewSchedDAGs = false,
224 ViewSUnitDAGs = false;
227 //===---------------------------------------------------------------------===//
229 /// RegisterScheduler class - Track the registration of instruction schedulers.
231 //===---------------------------------------------------------------------===//
232 MachinePassRegistry RegisterScheduler::Registry;
234 //===---------------------------------------------------------------------===//
236 /// ISHeuristic command line option for instruction schedulers.
238 //===---------------------------------------------------------------------===//
239 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
240 RegisterPassParser<RegisterScheduler> >
241 ISHeuristic("pre-RA-sched",
242 cl::init(&createDefaultScheduler), cl::Hidden,
243 cl::desc("Instruction schedulers available (before register"
246 static RegisterScheduler
247 defaultListDAGScheduler("default", "Best scheduler for the target",
248 createDefaultScheduler);
251 //===--------------------------------------------------------------------===//
252 /// \brief This class is used by SelectionDAGISel to temporarily override
253 /// the optimization level on a per-function basis.
254 class OptLevelChanger {
255 SelectionDAGISel &IS;
256 CodeGenOpt::Level SavedOptLevel;
260 OptLevelChanger(SelectionDAGISel &ISel,
261 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
262 SavedOptLevel = IS.OptLevel;
263 if (NewOptLevel == SavedOptLevel)
265 IS.OptLevel = NewOptLevel;
266 IS.TM.setOptLevel(NewOptLevel);
267 SavedFastISel = IS.TM.Options.EnableFastISel;
268 if (NewOptLevel == CodeGenOpt::None)
269 IS.TM.setFastISel(true);
270 DEBUG(dbgs() << "\nChanging optimization level for Function "
271 << IS.MF->getFunction()->getName() << "\n");
272 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
273 << " ; After: -O" << NewOptLevel << "\n");
277 if (IS.OptLevel == SavedOptLevel)
279 DEBUG(dbgs() << "\nRestoring optimization level for Function "
280 << IS.MF->getFunction()->getName() << "\n");
281 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
282 << " ; After: -O" << SavedOptLevel << "\n");
283 IS.OptLevel = SavedOptLevel;
284 IS.TM.setOptLevel(SavedOptLevel);
285 IS.TM.setFastISel(SavedFastISel);
289 //===--------------------------------------------------------------------===//
290 /// createDefaultScheduler - This creates an instruction scheduler appropriate
292 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
293 CodeGenOpt::Level OptLevel) {
294 const TargetLowering *TLI = IS->TLI;
295 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
297 // Try first to see if the Target has its own way of selecting a scheduler
298 if (auto *SchedulerCtor = ST.getDAGScheduler(OptLevel)) {
299 return SchedulerCtor(IS, OptLevel);
302 if (OptLevel == CodeGenOpt::None ||
303 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
304 TLI->getSchedulingPreference() == Sched::Source)
305 return createSourceListDAGScheduler(IS, OptLevel);
306 if (TLI->getSchedulingPreference() == Sched::RegPressure)
307 return createBURRListDAGScheduler(IS, OptLevel);
308 if (TLI->getSchedulingPreference() == Sched::Hybrid)
309 return createHybridListDAGScheduler(IS, OptLevel);
310 if (TLI->getSchedulingPreference() == Sched::VLIW)
311 return createVLIWDAGScheduler(IS, OptLevel);
312 assert(TLI->getSchedulingPreference() == Sched::ILP &&
313 "Unknown sched type!");
314 return createILPListDAGScheduler(IS, OptLevel);
318 // EmitInstrWithCustomInserter - This method should be implemented by targets
319 // that mark instructions with the 'usesCustomInserter' flag. These
320 // instructions are special in various ways, which require special support to
321 // insert. The specified MachineInstr is created but not inserted into any
322 // basic blocks, and this method is called to expand it into a sequence of
323 // instructions, potentially also creating new basic blocks and control flow.
324 // When new basic blocks are inserted and the edges from MBB to its successors
325 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
328 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
329 MachineBasicBlock *MBB) const {
331 dbgs() << "If a target marks an instruction with "
332 "'usesCustomInserter', it must implement "
333 "TargetLowering::EmitInstrWithCustomInserter!";
335 llvm_unreachable(nullptr);
338 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
339 SDNode *Node) const {
340 assert(!MI->hasPostISelHook() &&
341 "If a target marks an instruction with 'hasPostISelHook', "
342 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
345 //===----------------------------------------------------------------------===//
346 // SelectionDAGISel code
347 //===----------------------------------------------------------------------===//
349 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
350 CodeGenOpt::Level OL) :
351 MachineFunctionPass(ID), TM(tm),
352 FuncInfo(new FunctionLoweringInfo()),
353 CurDAG(new SelectionDAG(tm, OL)),
354 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
358 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
359 initializeBranchProbabilityInfoWrapperPassPass(
360 *PassRegistry::getPassRegistry());
361 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
362 initializeTargetLibraryInfoWrapperPassPass(
363 *PassRegistry::getPassRegistry());
366 SelectionDAGISel::~SelectionDAGISel() {
372 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
373 AU.addRequired<AAResultsWrapperPass>();
374 AU.addRequired<GCModuleInfo>();
375 AU.addPreserved<GCModuleInfo>();
376 AU.addRequired<TargetLibraryInfoWrapperPass>();
377 if (UseMBPI && OptLevel != CodeGenOpt::None)
378 AU.addRequired<BranchProbabilityInfoWrapperPass>();
379 MachineFunctionPass::getAnalysisUsage(AU);
382 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
383 /// may trap on it. In this case we have to split the edge so that the path
384 /// through the predecessor block that doesn't go to the phi block doesn't
385 /// execute the possibly trapping instruction.
387 /// This is required for correctness, so it must be done at -O0.
389 static void SplitCriticalSideEffectEdges(Function &Fn) {
390 // Loop for blocks with phi nodes.
391 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
392 PHINode *PN = dyn_cast<PHINode>(BB->begin());
396 // For each block with a PHI node, check to see if any of the input values
397 // are potentially trapping constant expressions. Constant expressions are
398 // the only potentially trapping value that can occur as the argument to a
400 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
401 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
402 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
403 if (!CE || !CE->canTrap()) continue;
405 // The only case we have to worry about is when the edge is critical.
406 // Since this block has a PHI Node, we assume it has multiple input
407 // edges: check to see if the pred has multiple successors.
408 BasicBlock *Pred = PN->getIncomingBlock(i);
409 if (Pred->getTerminator()->getNumSuccessors() == 1)
412 // Okay, we have to split this edge.
414 Pred->getTerminator(), GetSuccessorNumber(Pred, BB),
415 CriticalEdgeSplittingOptions().setMergeIdenticalEdges());
421 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
422 // Do some sanity-checking on the command-line options.
423 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
424 "-fast-isel-verbose requires -fast-isel");
425 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
426 "-fast-isel-abort > 0 requires -fast-isel");
428 const Function &Fn = *mf.getFunction();
431 // Reset the target options before resetting the optimization
433 // FIXME: This is a horrible hack and should be processed via
434 // codegen looking at the optimization level explicitly when
435 // it wants to look at it.
436 TM.resetTargetOptions(Fn);
437 // Reset OptLevel to None for optnone functions.
438 CodeGenOpt::Level NewOptLevel = OptLevel;
439 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
440 NewOptLevel = CodeGenOpt::None;
441 OptLevelChanger OLC(*this, NewOptLevel);
443 TII = MF->getSubtarget().getInstrInfo();
444 TLI = MF->getSubtarget().getTargetLowering();
445 RegInfo = &MF->getRegInfo();
446 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
447 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
448 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
450 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
452 SplitCriticalSideEffectEdges(const_cast<Function &>(Fn));
455 FuncInfo->set(Fn, *MF, CurDAG);
457 if (UseMBPI && OptLevel != CodeGenOpt::None)
458 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
460 FuncInfo->BPI = nullptr;
462 SDB->init(GFI, *AA, LibInfo);
464 MF->setHasInlineAsm(false);
466 SelectAllBasicBlocks(Fn);
468 // If the first basic block in the function has live ins that need to be
469 // copied into vregs, emit the copies into the top of the block before
470 // emitting the code for the block.
471 MachineBasicBlock *EntryMBB = MF->begin();
472 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
473 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
475 DenseMap<unsigned, unsigned> LiveInMap;
476 if (!FuncInfo->ArgDbgValues.empty())
477 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
478 E = RegInfo->livein_end(); LI != E; ++LI)
480 LiveInMap.insert(std::make_pair(LI->first, LI->second));
482 // Insert DBG_VALUE instructions for function arguments to the entry block.
483 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
484 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
485 bool hasFI = MI->getOperand(0).isFI();
487 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
488 if (TargetRegisterInfo::isPhysicalRegister(Reg))
489 EntryMBB->insert(EntryMBB->begin(), MI);
491 MachineInstr *Def = RegInfo->getVRegDef(Reg);
493 MachineBasicBlock::iterator InsertPos = Def;
494 // FIXME: VR def may not be in entry block.
495 Def->getParent()->insert(std::next(InsertPos), MI);
497 DEBUG(dbgs() << "Dropping debug info for dead vreg"
498 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
501 // If Reg is live-in then update debug info to track its copy in a vreg.
502 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
503 if (LDI != LiveInMap.end()) {
504 assert(!hasFI && "There's no handling of frame pointer updating here yet "
506 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
507 MachineBasicBlock::iterator InsertPos = Def;
508 const MDNode *Variable = MI->getDebugVariable();
509 const MDNode *Expr = MI->getDebugExpression();
510 DebugLoc DL = MI->getDebugLoc();
511 bool IsIndirect = MI->isIndirectDebugValue();
512 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
513 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
514 "Expected inlined-at fields to agree");
515 // Def is never a terminator here, so it is ok to increment InsertPos.
516 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
517 IsIndirect, LDI->second, Offset, Variable, Expr);
519 // If this vreg is directly copied into an exported register then
520 // that COPY instructions also need DBG_VALUE, if it is the only
521 // user of LDI->second.
522 MachineInstr *CopyUseMI = nullptr;
523 for (MachineRegisterInfo::use_instr_iterator
524 UI = RegInfo->use_instr_begin(LDI->second),
525 E = RegInfo->use_instr_end(); UI != E; ) {
526 MachineInstr *UseMI = &*(UI++);
527 if (UseMI->isDebugValue()) continue;
528 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
529 CopyUseMI = UseMI; continue;
531 // Otherwise this is another use or second copy use.
532 CopyUseMI = nullptr; break;
535 // Use MI's debug location, which describes where Variable was
536 // declared, rather than whatever is attached to CopyUseMI.
537 MachineInstr *NewMI =
538 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
539 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
540 MachineBasicBlock::iterator Pos = CopyUseMI;
541 EntryMBB->insertAfter(Pos, NewMI);
546 // Determine if there are any calls in this machine function.
547 MachineFrameInfo *MFI = MF->getFrameInfo();
548 for (const auto &MBB : *MF) {
549 if (MFI->hasCalls() && MF->hasInlineAsm())
552 for (const auto &MI : MBB) {
553 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
554 if ((MCID.isCall() && !MCID.isReturn()) ||
555 MI.isStackAligningInlineAsm()) {
556 MFI->setHasCalls(true);
558 if (MI.isInlineAsm()) {
559 MF->setHasInlineAsm(true);
564 // Determine if there is a call to setjmp in the machine function.
565 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
567 // Replace forward-declared registers with the registers containing
568 // the desired value.
569 MachineRegisterInfo &MRI = MF->getRegInfo();
570 for (DenseMap<unsigned, unsigned>::iterator
571 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
573 unsigned From = I->first;
574 unsigned To = I->second;
575 // If To is also scheduled to be replaced, find what its ultimate
578 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
582 // Make sure the new register has a sufficiently constrained register class.
583 if (TargetRegisterInfo::isVirtualRegister(From) &&
584 TargetRegisterInfo::isVirtualRegister(To))
585 MRI.constrainRegClass(To, MRI.getRegClass(From));
589 // Replacing one register with another won't touch the kill flags.
590 // We need to conservatively clear the kill flags as a kill on the old
591 // register might dominate existing uses of the new register.
592 if (!MRI.use_empty(To))
593 MRI.clearKillFlags(From);
594 MRI.replaceRegWith(From, To);
597 // Freeze the set of reserved registers now that MachineFrameInfo has been
598 // set up. All the information required by getReservedRegs() should be
600 MRI.freezeReservedRegs(*MF);
602 // Release function-specific state. SDB and CurDAG are already cleared
606 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
607 DEBUG(MF->print(dbgs()));
612 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
613 BasicBlock::const_iterator End,
615 // Lower the instructions. If a call is emitted as a tail call, cease emitting
616 // nodes for this block.
617 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
620 // Make sure the root of the DAG is up-to-date.
621 CurDAG->setRoot(SDB->getControlRoot());
622 HadTailCall = SDB->HasTailCall;
625 // Final step, emit the lowered DAG as machine code.
629 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
630 SmallPtrSet<SDNode*, 128> VisitedNodes;
631 SmallVector<SDNode*, 128> Worklist;
633 Worklist.push_back(CurDAG->getRoot().getNode());
639 SDNode *N = Worklist.pop_back_val();
641 // If we've already seen this node, ignore it.
642 if (!VisitedNodes.insert(N).second)
645 // Otherwise, add all chain operands to the worklist.
646 for (const SDValue &Op : N->op_values())
647 if (Op.getValueType() == MVT::Other)
648 Worklist.push_back(Op.getNode());
650 // If this is a CopyToReg with a vreg dest, process it.
651 if (N->getOpcode() != ISD::CopyToReg)
654 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
655 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
658 // Ignore non-scalar or non-integer values.
659 SDValue Src = N->getOperand(2);
660 EVT SrcVT = Src.getValueType();
661 if (!SrcVT.isInteger() || SrcVT.isVector())
664 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
665 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
666 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
667 } while (!Worklist.empty());
670 void SelectionDAGISel::CodeGenAndEmitDAG() {
671 std::string GroupName;
672 if (TimePassesIsEnabled)
673 GroupName = "Instruction Selection and Scheduling";
674 std::string BlockName;
675 int BlockNumber = -1;
677 bool MatchFilterBB = false; (void)MatchFilterBB;
679 MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
680 FilterDAGBasicBlockName ==
681 FuncInfo->MBB->getBasicBlock()->getName().str());
684 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
685 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
689 BlockNumber = FuncInfo->MBB->getNumber();
691 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
693 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
694 << " '" << BlockName << "'\n"; CurDAG->dump());
696 if (ViewDAGCombine1 && MatchFilterBB)
697 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
699 // Run the DAG combiner in pre-legalize mode.
701 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
702 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
705 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
706 << " '" << BlockName << "'\n"; CurDAG->dump());
708 // Second step, hack on the DAG until it only uses operations and types that
709 // the target supports.
710 if (ViewLegalizeTypesDAGs && MatchFilterBB)
711 CurDAG->viewGraph("legalize-types input for " + BlockName);
715 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
716 Changed = CurDAG->LegalizeTypes();
719 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
720 << " '" << BlockName << "'\n"; CurDAG->dump());
722 CurDAG->NewNodesMustHaveLegalTypes = true;
725 if (ViewDAGCombineLT && MatchFilterBB)
726 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
728 // Run the DAG combiner in post-type-legalize mode.
730 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
731 TimePassesIsEnabled);
732 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
735 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
736 << " '" << BlockName << "'\n"; CurDAG->dump());
741 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
742 Changed = CurDAG->LegalizeVectors();
747 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
748 CurDAG->LegalizeTypes();
751 if (ViewDAGCombineLT && MatchFilterBB)
752 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
754 // Run the DAG combiner in post-type-legalize mode.
756 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
757 TimePassesIsEnabled);
758 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
761 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
762 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
765 if (ViewLegalizeDAGs && MatchFilterBB)
766 CurDAG->viewGraph("legalize input for " + BlockName);
769 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
773 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
774 << " '" << BlockName << "'\n"; CurDAG->dump());
776 if (ViewDAGCombine2 && MatchFilterBB)
777 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
779 // Run the DAG combiner in post-legalize mode.
781 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
782 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
785 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
786 << " '" << BlockName << "'\n"; CurDAG->dump());
788 if (OptLevel != CodeGenOpt::None)
789 ComputeLiveOutVRegInfo();
791 if (ViewISelDAGs && MatchFilterBB)
792 CurDAG->viewGraph("isel input for " + BlockName);
794 // Third, instruction select all of the operations to machine code, adding the
795 // code to the MachineBasicBlock.
797 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
798 DoInstructionSelection();
801 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
802 << " '" << BlockName << "'\n"; CurDAG->dump());
804 if (ViewSchedDAGs && MatchFilterBB)
805 CurDAG->viewGraph("scheduler input for " + BlockName);
807 // Schedule machine code.
808 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
810 NamedRegionTimer T("Instruction Scheduling", GroupName,
811 TimePassesIsEnabled);
812 Scheduler->Run(CurDAG, FuncInfo->MBB);
815 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
817 // Emit machine code to BB. This can change 'BB' to the last block being
819 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
821 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
823 // FuncInfo->InsertPt is passed by reference and set to the end of the
824 // scheduled instructions.
825 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
828 // If the block was split, make sure we update any references that are used to
829 // update PHI nodes later on.
830 if (FirstMBB != LastMBB)
831 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
833 // Free the scheduler state.
835 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
836 TimePassesIsEnabled);
840 // Free the SelectionDAG state, now that we're finished with it.
845 /// ISelUpdater - helper class to handle updates of the instruction selection
847 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
848 SelectionDAG::allnodes_iterator &ISelPosition;
850 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
851 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
853 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
854 /// deleted is the current ISelPosition node, update ISelPosition.
856 void NodeDeleted(SDNode *N, SDNode *E) override {
857 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
861 } // end anonymous namespace
863 void SelectionDAGISel::DoInstructionSelection() {
864 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
865 << FuncInfo->MBB->getNumber()
866 << " '" << FuncInfo->MBB->getName() << "'\n");
870 // Select target instructions for the DAG.
872 // Number all nodes with a topological order and set DAGSize.
873 DAGSize = CurDAG->AssignTopologicalOrder();
875 // Create a dummy node (which is not added to allnodes), that adds
876 // a reference to the root node, preventing it from being deleted,
877 // and tracking any changes of the root.
878 HandleSDNode Dummy(CurDAG->getRoot());
879 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
882 // Make sure that ISelPosition gets properly updated when nodes are deleted
883 // in calls made from this function.
884 ISelUpdater ISU(*CurDAG, ISelPosition);
886 // The AllNodes list is now topological-sorted. Visit the
887 // nodes by starting at the end of the list (the root of the
888 // graph) and preceding back toward the beginning (the entry
890 while (ISelPosition != CurDAG->allnodes_begin()) {
891 SDNode *Node = --ISelPosition;
892 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
893 // but there are currently some corner cases that it misses. Also, this
894 // makes it theoretically possible to disable the DAGCombiner.
895 if (Node->use_empty())
898 SDNode *ResNode = Select(Node);
900 // FIXME: This is pretty gross. 'Select' should be changed to not return
901 // anything at all and this code should be nuked with a tactical strike.
903 // If node should not be replaced, continue with the next one.
904 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
908 ReplaceUses(Node, ResNode);
911 // If after the replacement this node is not used any more,
912 // remove this dead node.
913 if (Node->use_empty()) // Don't delete EntryToken, etc.
914 CurDAG->RemoveDeadNode(Node);
917 CurDAG->setRoot(Dummy.getValue());
920 DEBUG(dbgs() << "===== Instruction selection ends:\n");
922 PostprocessISelDAG();
925 static bool hasExceptionPointerOrCodeUser(const CatchPadInst *CPI) {
926 for (const User *U : CPI->users()) {
927 if (const IntrinsicInst *EHPtrCall = dyn_cast<IntrinsicInst>(U)) {
928 Intrinsic::ID IID = EHPtrCall->getIntrinsicID();
929 if (IID == Intrinsic::eh_exceptionpointer ||
930 IID == Intrinsic::eh_exceptioncode)
937 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
938 /// do other setup for EH landing-pad blocks.
939 bool SelectionDAGISel::PrepareEHLandingPad() {
940 MachineBasicBlock *MBB = FuncInfo->MBB;
941 const BasicBlock *LLVMBB = MBB->getBasicBlock();
942 const TargetRegisterClass *PtrRC =
943 TLI->getRegClassFor(TLI->getPointerTy(CurDAG->getDataLayout()));
945 // Catchpads have one live-in register, which typically holds the exception
947 if (const auto *CPI = dyn_cast<CatchPadInst>(LLVMBB->getFirstNonPHI())) {
948 if (hasExceptionPointerOrCodeUser(CPI)) {
949 // Get or create the virtual register to hold the pointer or code. Mark
950 // the live in physreg and copy into the vreg.
951 MCPhysReg EHPhysReg = TLI->getExceptionPointerRegister();
952 assert(EHPhysReg && "target lacks exception pointer register");
953 MBB->addLiveIn(EHPhysReg);
954 unsigned VReg = FuncInfo->getCatchPadExceptionPointerVReg(CPI, PtrRC);
955 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(),
956 TII->get(TargetOpcode::COPY), VReg)
957 .addReg(EHPhysReg, RegState::Kill);
962 if (!LLVMBB->isLandingPad())
965 // Add a label to mark the beginning of the landing pad. Deletion of the
966 // landing pad can thus be detected via the MachineModuleInfo.
967 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
969 // Assign the call site to the landing pad's begin label.
970 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
972 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
973 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
976 // Mark exception register as live in.
977 if (unsigned Reg = TLI->getExceptionPointerRegister())
978 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
980 // Mark exception selector register as live in.
981 if (unsigned Reg = TLI->getExceptionSelectorRegister())
982 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
987 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
988 /// side-effect free and is either dead or folded into a generated instruction.
989 /// Return false if it needs to be emitted.
990 static bool isFoldedOrDeadInstruction(const Instruction *I,
991 FunctionLoweringInfo *FuncInfo) {
992 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
993 !isa<TerminatorInst>(I) && // Terminators aren't folded.
994 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
995 !I->isEHPad() && // EH pad instructions aren't folded.
996 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1000 // Collect per Instruction statistics for fast-isel misses. Only those
1001 // instructions that cause the bail are accounted for. It does not account for
1002 // instructions higher in the block. Thus, summing the per instructions stats
1003 // will not add up to what is reported by NumFastIselFailures.
1004 static void collectFailStats(const Instruction *I) {
1005 switch (I->getOpcode()) {
1006 default: assert (0 && "<Invalid operator> ");
1009 case Instruction::Ret: NumFastIselFailRet++; return;
1010 case Instruction::Br: NumFastIselFailBr++; return;
1011 case Instruction::Switch: NumFastIselFailSwitch++; return;
1012 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1013 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1014 case Instruction::Resume: NumFastIselFailResume++; return;
1015 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1017 // Standard binary operators...
1018 case Instruction::Add: NumFastIselFailAdd++; return;
1019 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1020 case Instruction::Sub: NumFastIselFailSub++; return;
1021 case Instruction::FSub: NumFastIselFailFSub++; return;
1022 case Instruction::Mul: NumFastIselFailMul++; return;
1023 case Instruction::FMul: NumFastIselFailFMul++; return;
1024 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1025 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1026 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1027 case Instruction::URem: NumFastIselFailURem++; return;
1028 case Instruction::SRem: NumFastIselFailSRem++; return;
1029 case Instruction::FRem: NumFastIselFailFRem++; return;
1031 // Logical operators...
1032 case Instruction::And: NumFastIselFailAnd++; return;
1033 case Instruction::Or: NumFastIselFailOr++; return;
1034 case Instruction::Xor: NumFastIselFailXor++; return;
1036 // Memory instructions...
1037 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1038 case Instruction::Load: NumFastIselFailLoad++; return;
1039 case Instruction::Store: NumFastIselFailStore++; return;
1040 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1041 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1042 case Instruction::Fence: NumFastIselFailFence++; return;
1043 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1045 // Convert instructions...
1046 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1047 case Instruction::ZExt: NumFastIselFailZExt++; return;
1048 case Instruction::SExt: NumFastIselFailSExt++; return;
1049 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1050 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1051 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1052 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1053 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1054 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1055 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1056 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1057 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1059 // Other instructions...
1060 case Instruction::ICmp: NumFastIselFailICmp++; return;
1061 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1062 case Instruction::PHI: NumFastIselFailPHI++; return;
1063 case Instruction::Select: NumFastIselFailSelect++; return;
1064 case Instruction::Call: {
1065 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1066 switch (Intrinsic->getIntrinsicID()) {
1068 NumFastIselFailIntrinsicCall++; return;
1069 case Intrinsic::sadd_with_overflow:
1070 NumFastIselFailSAddWithOverflow++; return;
1071 case Intrinsic::uadd_with_overflow:
1072 NumFastIselFailUAddWithOverflow++; return;
1073 case Intrinsic::ssub_with_overflow:
1074 NumFastIselFailSSubWithOverflow++; return;
1075 case Intrinsic::usub_with_overflow:
1076 NumFastIselFailUSubWithOverflow++; return;
1077 case Intrinsic::smul_with_overflow:
1078 NumFastIselFailSMulWithOverflow++; return;
1079 case Intrinsic::umul_with_overflow:
1080 NumFastIselFailUMulWithOverflow++; return;
1081 case Intrinsic::frameaddress:
1082 NumFastIselFailFrameaddress++; return;
1083 case Intrinsic::sqrt:
1084 NumFastIselFailSqrt++; return;
1085 case Intrinsic::experimental_stackmap:
1086 NumFastIselFailStackMap++; return;
1087 case Intrinsic::experimental_patchpoint_void: // fall-through
1088 case Intrinsic::experimental_patchpoint_i64:
1089 NumFastIselFailPatchPoint++; return;
1092 NumFastIselFailCall++;
1095 case Instruction::Shl: NumFastIselFailShl++; return;
1096 case Instruction::LShr: NumFastIselFailLShr++; return;
1097 case Instruction::AShr: NumFastIselFailAShr++; return;
1098 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1099 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1100 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1101 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1102 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1103 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1104 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1109 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1110 // Initialize the Fast-ISel state, if needed.
1111 FastISel *FastIS = nullptr;
1112 if (TM.Options.EnableFastISel)
1113 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1115 // Iterate over all basic blocks in the function.
1116 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1117 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1118 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1119 const BasicBlock *LLVMBB = *I;
1121 if (OptLevel != CodeGenOpt::None) {
1122 bool AllPredsVisited = true;
1123 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1125 if (!FuncInfo->VisitedBBs.count(*PI)) {
1126 AllPredsVisited = false;
1131 if (AllPredsVisited) {
1132 for (BasicBlock::const_iterator I = LLVMBB->begin();
1133 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1134 FuncInfo->ComputePHILiveOutRegInfo(PN);
1136 for (BasicBlock::const_iterator I = LLVMBB->begin();
1137 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1138 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1141 FuncInfo->VisitedBBs.insert(LLVMBB);
1144 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1145 BasicBlock::const_iterator const End = LLVMBB->end();
1146 BasicBlock::const_iterator BI = End;
1148 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1150 continue; // Some blocks like catchpads have no code or MBB.
1151 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1153 // Setup an EH landing-pad block.
1154 FuncInfo->ExceptionPointerVirtReg = 0;
1155 FuncInfo->ExceptionSelectorVirtReg = 0;
1156 if (!PrepareEHLandingPad())
1159 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1161 FastIS->startNewBlock();
1163 // Emit code for any incoming arguments. This must happen before
1164 // beginning FastISel on the entry block.
1165 if (LLVMBB == &Fn.getEntryBlock()) {
1168 // Lower any arguments needed in this block if this is the entry block.
1169 if (!FastIS->lowerArguments()) {
1170 // Fast isel failed to lower these arguments
1171 ++NumFastIselFailLowerArguments;
1172 if (EnableFastISelAbort > 1)
1173 report_fatal_error("FastISel didn't lower all arguments");
1175 // Use SelectionDAG argument lowering
1177 CurDAG->setRoot(SDB->getControlRoot());
1179 CodeGenAndEmitDAG();
1182 // If we inserted any instructions at the beginning, make a note of
1183 // where they are, so we can be sure to emit subsequent instructions
1185 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1186 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1188 FastIS->setLastLocalValue(nullptr);
1191 unsigned NumFastIselRemaining = std::distance(Begin, End);
1192 // Do FastISel on as many instructions as possible.
1193 for (; BI != Begin; --BI) {
1194 const Instruction *Inst = std::prev(BI);
1196 // If we no longer require this instruction, skip it.
1197 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1198 --NumFastIselRemaining;
1202 // Bottom-up: reset the insert pos at the top, after any local-value
1204 FastIS->recomputeInsertPt();
1206 // Try to select the instruction with FastISel.
1207 if (FastIS->selectInstruction(Inst)) {
1208 --NumFastIselRemaining;
1209 ++NumFastIselSuccess;
1210 // If fast isel succeeded, skip over all the folded instructions, and
1211 // then see if there is a load right before the selected instructions.
1212 // Try to fold the load if so.
1213 const Instruction *BeforeInst = Inst;
1214 while (BeforeInst != Begin) {
1215 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1216 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1219 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1220 BeforeInst->hasOneUse() &&
1221 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1222 // If we succeeded, don't re-select the load.
1223 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1224 --NumFastIselRemaining;
1225 ++NumFastIselSuccess;
1231 if (EnableFastISelVerbose2)
1232 collectFailStats(Inst);
1235 // Then handle certain instructions as single-LLVM-Instruction blocks.
1236 if (isa<CallInst>(Inst)) {
1238 if (EnableFastISelVerbose || EnableFastISelAbort) {
1239 dbgs() << "FastISel missed call: ";
1242 if (EnableFastISelAbort > 2)
1243 // FastISel selector couldn't handle something and bailed.
1244 // For the purpose of debugging, just abort.
1245 report_fatal_error("FastISel didn't select the entire block");
1247 if (!Inst->getType()->isVoidTy() && !Inst->getType()->isTokenTy() &&
1248 !Inst->use_empty()) {
1249 unsigned &R = FuncInfo->ValueMap[Inst];
1251 R = FuncInfo->CreateRegs(Inst->getType());
1254 bool HadTailCall = false;
1255 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1256 SelectBasicBlock(Inst, BI, HadTailCall);
1258 // If the call was emitted as a tail call, we're done with the block.
1259 // We also need to delete any previously emitted instructions.
1261 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1266 // Recompute NumFastIselRemaining as Selection DAG instruction
1267 // selection may have handled the call, input args, etc.
1268 unsigned RemainingNow = std::distance(Begin, BI);
1269 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1270 NumFastIselRemaining = RemainingNow;
1274 bool ShouldAbort = EnableFastISelAbort;
1275 if (EnableFastISelVerbose || EnableFastISelAbort) {
1276 if (isa<TerminatorInst>(Inst)) {
1277 // Use a different message for terminator misses.
1278 dbgs() << "FastISel missed terminator: ";
1279 // Don't abort unless for terminator unless the level is really high
1280 ShouldAbort = (EnableFastISelAbort > 2);
1282 dbgs() << "FastISel miss: ";
1287 // FastISel selector couldn't handle something and bailed.
1288 // For the purpose of debugging, just abort.
1289 report_fatal_error("FastISel didn't select the entire block");
1291 NumFastIselFailures += NumFastIselRemaining;
1295 FastIS->recomputeInsertPt();
1297 // Lower any arguments needed in this block if this is the entry block.
1298 if (LLVMBB == &Fn.getEntryBlock()) {
1307 ++NumFastIselBlocks;
1310 // Run SelectionDAG instruction selection on the remainder of the block
1311 // not handled by FastISel. If FastISel is not run, this is the entire
1314 SelectBasicBlock(Begin, BI, HadTailCall);
1318 FuncInfo->PHINodesToUpdate.clear();
1322 SDB->clearDanglingDebugInfo();
1323 SDB->SPDescriptor.resetPerFunctionState();
1326 /// Given that the input MI is before a partial terminator sequence TSeq, return
1327 /// true if M + TSeq also a partial terminator sequence.
1329 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1330 /// lowering copy vregs into physical registers, which are then passed into
1331 /// terminator instructors so we can satisfy ABI constraints. A partial
1332 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1333 /// may be the whole terminator sequence).
1334 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1335 // If we do not have a copy or an implicit def, we return true if and only if
1336 // MI is a debug value.
1337 if (!MI->isCopy() && !MI->isImplicitDef())
1338 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1339 // physical registers if there is debug info associated with the terminator
1340 // of our mbb. We want to include said debug info in our terminator
1341 // sequence, so we return true in that case.
1342 return MI->isDebugValue();
1344 // We have left the terminator sequence if we are not doing one of the
1347 // 1. Copying a vreg into a physical register.
1348 // 2. Copying a vreg into a vreg.
1349 // 3. Defining a register via an implicit def.
1351 // OPI should always be a register definition...
1352 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1353 if (!OPI->isReg() || !OPI->isDef())
1356 // Defining any register via an implicit def is always ok.
1357 if (MI->isImplicitDef())
1360 // Grab the copy source...
1361 MachineInstr::const_mop_iterator OPI2 = OPI;
1363 assert(OPI2 != MI->operands_end()
1364 && "Should have a copy implying we should have 2 arguments.");
1366 // Make sure that the copy dest is not a vreg when the copy source is a
1367 // physical register.
1368 if (!OPI2->isReg() ||
1369 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1370 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1376 /// Find the split point at which to splice the end of BB into its success stack
1377 /// protector check machine basic block.
1379 /// On many platforms, due to ABI constraints, terminators, even before register
1380 /// allocation, use physical registers. This creates an issue for us since
1381 /// physical registers at this point can not travel across basic
1382 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1383 /// when they enter functions and moves them through a sequence of copies back
1384 /// into the physical registers right before the terminator creating a
1385 /// ``Terminator Sequence''. This function is searching for the beginning of the
1386 /// terminator sequence so that we can ensure that we splice off not just the
1387 /// terminator, but additionally the copies that move the vregs into the
1388 /// physical registers.
1389 static MachineBasicBlock::iterator
1390 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1391 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1393 if (SplitPoint == BB->begin())
1396 MachineBasicBlock::iterator Start = BB->begin();
1397 MachineBasicBlock::iterator Previous = SplitPoint;
1400 while (MIIsInTerminatorSequence(Previous)) {
1401 SplitPoint = Previous;
1402 if (Previous == Start)
1411 SelectionDAGISel::FinishBasicBlock() {
1413 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1414 << FuncInfo->PHINodesToUpdate.size() << "\n";
1415 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1416 dbgs() << "Node " << i << " : ("
1417 << FuncInfo->PHINodesToUpdate[i].first
1418 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1420 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1421 // PHI nodes in successors.
1422 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1423 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1424 assert(PHI->isPHI() &&
1425 "This is not a machine PHI node that we are updating!");
1426 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1428 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1431 // Handle stack protector.
1432 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1433 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1434 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1436 // Find the split point to split the parent mbb. At the same time copy all
1437 // physical registers used in the tail of parent mbb into virtual registers
1438 // before the split point and back into physical registers after the split
1439 // point. This prevents us needing to deal with Live-ins and many other
1440 // register allocation issues caused by us splitting the parent mbb. The
1441 // register allocator will clean up said virtual copies later on.
1442 MachineBasicBlock::iterator SplitPoint =
1443 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1445 // Splice the terminator of ParentMBB into SuccessMBB.
1446 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1450 // Add compare/jump on neq/jump to the parent BB.
1451 FuncInfo->MBB = ParentMBB;
1452 FuncInfo->InsertPt = ParentMBB->end();
1453 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1454 CurDAG->setRoot(SDB->getRoot());
1456 CodeGenAndEmitDAG();
1458 // CodeGen Failure MBB if we have not codegened it yet.
1459 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1460 if (!FailureMBB->size()) {
1461 FuncInfo->MBB = FailureMBB;
1462 FuncInfo->InsertPt = FailureMBB->end();
1463 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1464 CurDAG->setRoot(SDB->getRoot());
1466 CodeGenAndEmitDAG();
1469 // Clear the Per-BB State.
1470 SDB->SPDescriptor.resetPerBBState();
1473 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1474 // Lower header first, if it wasn't already lowered
1475 if (!SDB->BitTestCases[i].Emitted) {
1476 // Set the current basic block to the mbb we wish to insert the code into
1477 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1478 FuncInfo->InsertPt = FuncInfo->MBB->end();
1480 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1481 CurDAG->setRoot(SDB->getRoot());
1483 CodeGenAndEmitDAG();
1486 uint32_t UnhandledWeight = SDB->BitTestCases[i].Weight;
1488 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1489 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1490 // Set the current basic block to the mbb we wish to insert the code into
1491 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1492 FuncInfo->InsertPt = FuncInfo->MBB->end();
1495 // If all cases cover a contiguous range, it is not necessary to jump to
1496 // the default block after the last bit test fails. This is because the
1497 // range check during bit test header creation has guaranteed that every
1498 // case here doesn't go outside the range.
1499 MachineBasicBlock *NextMBB;
1500 if (SDB->BitTestCases[i].ContiguousRange && j + 2 == ej)
1501 NextMBB = SDB->BitTestCases[i].Cases[j + 1].TargetBB;
1502 else if (j + 1 != ej)
1503 NextMBB = SDB->BitTestCases[i].Cases[j + 1].ThisBB;
1505 NextMBB = SDB->BitTestCases[i].Default;
1507 SDB->visitBitTestCase(SDB->BitTestCases[i],
1510 SDB->BitTestCases[i].Reg,
1511 SDB->BitTestCases[i].Cases[j],
1514 CurDAG->setRoot(SDB->getRoot());
1516 CodeGenAndEmitDAG();
1518 if (SDB->BitTestCases[i].ContiguousRange && j + 2 == ej)
1523 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1525 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1526 MachineBasicBlock *PHIBB = PHI->getParent();
1527 assert(PHI->isPHI() &&
1528 "This is not a machine PHI node that we are updating!");
1529 // This is "default" BB. We have two jumps to it. From "header" BB and
1530 // from last "case" BB.
1531 if (PHIBB == SDB->BitTestCases[i].Default)
1532 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1533 .addMBB(SDB->BitTestCases[i].Parent)
1534 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1535 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1536 // One of "cases" BB.
1537 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1539 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1540 if (cBB->isSuccessor(PHIBB))
1541 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1545 SDB->BitTestCases.clear();
1547 // If the JumpTable record is filled in, then we need to emit a jump table.
1548 // Updating the PHI nodes is tricky in this case, since we need to determine
1549 // whether the PHI is a successor of the range check MBB or the jump table MBB
1550 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1551 // Lower header first, if it wasn't already lowered
1552 if (!SDB->JTCases[i].first.Emitted) {
1553 // Set the current basic block to the mbb we wish to insert the code into
1554 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1555 FuncInfo->InsertPt = FuncInfo->MBB->end();
1557 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1559 CurDAG->setRoot(SDB->getRoot());
1561 CodeGenAndEmitDAG();
1564 // Set the current basic block to the mbb we wish to insert the code into
1565 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1566 FuncInfo->InsertPt = FuncInfo->MBB->end();
1568 SDB->visitJumpTable(SDB->JTCases[i].second);
1569 CurDAG->setRoot(SDB->getRoot());
1571 CodeGenAndEmitDAG();
1574 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1576 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1577 MachineBasicBlock *PHIBB = PHI->getParent();
1578 assert(PHI->isPHI() &&
1579 "This is not a machine PHI node that we are updating!");
1580 // "default" BB. We can go there only from header BB.
1581 if (PHIBB == SDB->JTCases[i].second.Default)
1582 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1583 .addMBB(SDB->JTCases[i].first.HeaderBB);
1584 // JT BB. Just iterate over successors here
1585 if (FuncInfo->MBB->isSuccessor(PHIBB))
1586 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1589 SDB->JTCases.clear();
1591 // If we generated any switch lowering information, build and codegen any
1592 // additional DAGs necessary.
1593 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1594 // Set the current basic block to the mbb we wish to insert the code into
1595 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1596 FuncInfo->InsertPt = FuncInfo->MBB->end();
1598 // Determine the unique successors.
1599 SmallVector<MachineBasicBlock *, 2> Succs;
1600 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1601 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1602 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1604 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1605 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1606 CurDAG->setRoot(SDB->getRoot());
1608 CodeGenAndEmitDAG();
1610 // Remember the last block, now that any splitting is done, for use in
1611 // populating PHI nodes in successors.
1612 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1614 // Handle any PHI nodes in successors of this chunk, as if we were coming
1615 // from the original BB before switch expansion. Note that PHI nodes can
1616 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1617 // handle them the right number of times.
1618 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1619 FuncInfo->MBB = Succs[i];
1620 FuncInfo->InsertPt = FuncInfo->MBB->end();
1621 // FuncInfo->MBB may have been removed from the CFG if a branch was
1623 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1624 for (MachineBasicBlock::iterator
1625 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1626 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1627 MachineInstrBuilder PHI(*MF, MBBI);
1628 // This value for this PHI node is recorded in PHINodesToUpdate.
1629 for (unsigned pn = 0; ; ++pn) {
1630 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1631 "Didn't find PHI entry!");
1632 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1633 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1641 SDB->SwitchCases.clear();
1645 /// Create the scheduler. If a specific scheduler was specified
1646 /// via the SchedulerRegistry, use it, otherwise select the
1647 /// one preferred by the target.
1649 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1650 return ISHeuristic(this, OptLevel);
1653 //===----------------------------------------------------------------------===//
1654 // Helper functions used by the generated instruction selector.
1655 //===----------------------------------------------------------------------===//
1656 // Calls to these methods are generated by tblgen.
1658 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1659 /// the dag combiner simplified the 255, we still want to match. RHS is the
1660 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1661 /// specified in the .td file (e.g. 255).
1662 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1663 int64_t DesiredMaskS) const {
1664 const APInt &ActualMask = RHS->getAPIntValue();
1665 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1667 // If the actual mask exactly matches, success!
1668 if (ActualMask == DesiredMask)
1671 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1672 if (ActualMask.intersects(~DesiredMask))
1675 // Otherwise, the DAG Combiner may have proven that the value coming in is
1676 // either already zero or is not demanded. Check for known zero input bits.
1677 APInt NeededMask = DesiredMask & ~ActualMask;
1678 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1681 // TODO: check to see if missing bits are just not demanded.
1683 // Otherwise, this pattern doesn't match.
1687 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1688 /// the dag combiner simplified the 255, we still want to match. RHS is the
1689 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1690 /// specified in the .td file (e.g. 255).
1691 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1692 int64_t DesiredMaskS) const {
1693 const APInt &ActualMask = RHS->getAPIntValue();
1694 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1696 // If the actual mask exactly matches, success!
1697 if (ActualMask == DesiredMask)
1700 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1701 if (ActualMask.intersects(~DesiredMask))
1704 // Otherwise, the DAG Combiner may have proven that the value coming in is
1705 // either already zero or is not demanded. Check for known zero input bits.
1706 APInt NeededMask = DesiredMask & ~ActualMask;
1708 APInt KnownZero, KnownOne;
1709 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1711 // If all the missing bits in the or are already known to be set, match!
1712 if ((NeededMask & KnownOne) == NeededMask)
1715 // TODO: check to see if missing bits are just not demanded.
1717 // Otherwise, this pattern doesn't match.
1721 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1722 /// by tblgen. Others should not call it.
1723 void SelectionDAGISel::
1724 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SDLoc DL) {
1725 std::vector<SDValue> InOps;
1726 std::swap(InOps, Ops);
1728 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1729 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1730 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1731 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1733 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1734 if (InOps[e-1].getValueType() == MVT::Glue)
1735 --e; // Don't process a glue operand if it is here.
1738 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1739 if (!InlineAsm::isMemKind(Flags)) {
1740 // Just skip over this operand, copying the operands verbatim.
1741 Ops.insert(Ops.end(), InOps.begin()+i,
1742 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1743 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1745 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1746 "Memory operand with multiple values?");
1748 unsigned TiedToOperand;
1749 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) {
1750 // We need the constraint ID from the operand this is tied to.
1751 unsigned CurOp = InlineAsm::Op_FirstOperand;
1752 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1753 for (; TiedToOperand; --TiedToOperand) {
1754 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
1755 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1759 // Otherwise, this is a memory operand. Ask the target to select it.
1760 std::vector<SDValue> SelOps;
1761 if (SelectInlineAsmMemoryOperand(InOps[i+1],
1762 InlineAsm::getMemoryConstraintID(Flags),
1764 report_fatal_error("Could not match memory address. Inline asm"
1767 // Add this to the output node.
1769 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1770 Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32));
1771 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1776 // Add the glue input back if present.
1777 if (e != InOps.size())
1778 Ops.push_back(InOps.back());
1781 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1784 static SDNode *findGlueUse(SDNode *N) {
1785 unsigned FlagResNo = N->getNumValues()-1;
1786 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1787 SDUse &Use = I.getUse();
1788 if (Use.getResNo() == FlagResNo)
1789 return Use.getUser();
1794 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1795 /// This function recursively traverses up the operand chain, ignoring
1797 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1798 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1799 bool IgnoreChains) {
1800 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1801 // greater than all of its (recursive) operands. If we scan to a point where
1802 // 'use' is smaller than the node we're scanning for, then we know we will
1805 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1806 // happen because we scan down to newly selected nodes in the case of glue
1808 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1811 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1812 // won't fail if we scan it again.
1813 if (!Visited.insert(Use).second)
1816 for (const SDValue &Op : Use->op_values()) {
1817 // Ignore chain uses, they are validated by HandleMergeInputChains.
1818 if (Op.getValueType() == MVT::Other && IgnoreChains)
1821 SDNode *N = Op.getNode();
1823 if (Use == ImmedUse || Use == Root)
1824 continue; // We are not looking for immediate use.
1829 // Traverse up the operand chain.
1830 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1836 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1837 /// operand node N of U during instruction selection that starts at Root.
1838 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1839 SDNode *Root) const {
1840 if (OptLevel == CodeGenOpt::None) return false;
1841 return N.hasOneUse();
1844 /// IsLegalToFold - Returns true if the specific operand node N of
1845 /// U can be folded during instruction selection that starts at Root.
1846 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1847 CodeGenOpt::Level OptLevel,
1848 bool IgnoreChains) {
1849 if (OptLevel == CodeGenOpt::None) return false;
1851 // If Root use can somehow reach N through a path that that doesn't contain
1852 // U then folding N would create a cycle. e.g. In the following
1853 // diagram, Root can reach N through X. If N is folded into into Root, then
1854 // X is both a predecessor and a successor of U.
1865 // * indicates nodes to be folded together.
1867 // If Root produces glue, then it gets (even more) interesting. Since it
1868 // will be "glued" together with its glue use in the scheduler, we need to
1869 // check if it might reach N.
1888 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1889 // (call it Fold), then X is a predecessor of GU and a successor of
1890 // Fold. But since Fold and GU are glued together, this will create
1891 // a cycle in the scheduling graph.
1893 // If the node has glue, walk down the graph to the "lowest" node in the
1895 EVT VT = Root->getValueType(Root->getNumValues()-1);
1896 while (VT == MVT::Glue) {
1897 SDNode *GU = findGlueUse(Root);
1901 VT = Root->getValueType(Root->getNumValues()-1);
1903 // If our query node has a glue result with a use, we've walked up it. If
1904 // the user (which has already been selected) has a chain or indirectly uses
1905 // the chain, our WalkChainUsers predicate will not consider it. Because of
1906 // this, we cannot ignore chains in this predicate.
1907 IgnoreChains = false;
1911 SmallPtrSet<SDNode*, 16> Visited;
1912 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1915 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1918 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1919 SelectInlineAsmMemoryOperands(Ops, DL);
1921 const EVT VTs[] = {MVT::Other, MVT::Glue};
1922 SDValue New = CurDAG->getNode(ISD::INLINEASM, DL, VTs, Ops);
1924 return New.getNode();
1928 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1930 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1931 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1933 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0),
1935 SDValue New = CurDAG->getCopyFromReg(
1936 Op->getOperand(0), dl, Reg, Op->getValueType(0));
1938 return New.getNode();
1942 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1944 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1945 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1946 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1947 Op->getOperand(2).getValueType(),
1949 SDValue New = CurDAG->getCopyToReg(
1950 Op->getOperand(0), dl, Reg, Op->getOperand(2));
1952 return New.getNode();
1957 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1958 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1961 /// GetVBR - decode a vbr encoding whose top bit is set.
1962 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline uint64_t
1963 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1964 assert(Val >= 128 && "Not a VBR");
1965 Val &= 127; // Remove first vbr bit.
1970 NextBits = MatcherTable[Idx++];
1971 Val |= (NextBits&127) << Shift;
1973 } while (NextBits & 128);
1979 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1980 /// interior glue and chain results to use the new glue and chain results.
1981 void SelectionDAGISel::
1982 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1983 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1985 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1986 bool isMorphNodeTo) {
1987 SmallVector<SDNode*, 4> NowDeadNodes;
1989 // Now that all the normal results are replaced, we replace the chain and
1990 // glue results if present.
1991 if (!ChainNodesMatched.empty()) {
1992 assert(InputChain.getNode() &&
1993 "Matched input chains but didn't produce a chain");
1994 // Loop over all of the nodes we matched that produced a chain result.
1995 // Replace all the chain results with the final chain we ended up with.
1996 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1997 SDNode *ChainNode = ChainNodesMatched[i];
1999 // If this node was already deleted, don't look at it.
2000 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2003 // Don't replace the results of the root node if we're doing a
2005 if (ChainNode == NodeToMatch && isMorphNodeTo)
2008 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2009 if (ChainVal.getValueType() == MVT::Glue)
2010 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2011 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2012 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2014 // If the node became dead and we haven't already seen it, delete it.
2015 if (ChainNode->use_empty() &&
2016 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2017 NowDeadNodes.push_back(ChainNode);
2021 // If the result produces glue, update any glue results in the matched
2022 // pattern with the glue result.
2023 if (InputGlue.getNode()) {
2024 // Handle any interior nodes explicitly marked.
2025 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2026 SDNode *FRN = GlueResultNodesMatched[i];
2028 // If this node was already deleted, don't look at it.
2029 if (FRN->getOpcode() == ISD::DELETED_NODE)
2032 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2033 "Doesn't have a glue result");
2034 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2037 // If the node became dead and we haven't already seen it, delete it.
2038 if (FRN->use_empty() &&
2039 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2040 NowDeadNodes.push_back(FRN);
2044 if (!NowDeadNodes.empty())
2045 CurDAG->RemoveDeadNodes(NowDeadNodes);
2047 DEBUG(dbgs() << "ISEL: Match complete!\n");
2053 CR_LeadsToInteriorNode
2056 /// WalkChainUsers - Walk down the users of the specified chained node that is
2057 /// part of the pattern we're matching, looking at all of the users we find.
2058 /// This determines whether something is an interior node, whether we have a
2059 /// non-pattern node in between two pattern nodes (which prevent folding because
2060 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2061 /// between pattern nodes (in which case the TF becomes part of the pattern).
2063 /// The walk we do here is guaranteed to be small because we quickly get down to
2064 /// already selected nodes "below" us.
2066 WalkChainUsers(const SDNode *ChainedNode,
2067 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2068 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2069 ChainResult Result = CR_Simple;
2071 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2072 E = ChainedNode->use_end(); UI != E; ++UI) {
2073 // Make sure the use is of the chain, not some other value we produce.
2074 if (UI.getUse().getValueType() != MVT::Other) continue;
2078 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2081 // If we see an already-selected machine node, then we've gone beyond the
2082 // pattern that we're selecting down into the already selected chunk of the
2084 unsigned UserOpcode = User->getOpcode();
2085 if (User->isMachineOpcode() ||
2086 UserOpcode == ISD::CopyToReg ||
2087 UserOpcode == ISD::CopyFromReg ||
2088 UserOpcode == ISD::INLINEASM ||
2089 UserOpcode == ISD::EH_LABEL ||
2090 UserOpcode == ISD::LIFETIME_START ||
2091 UserOpcode == ISD::LIFETIME_END) {
2092 // If their node ID got reset to -1 then they've already been selected.
2093 // Treat them like a MachineOpcode.
2094 if (User->getNodeId() == -1)
2098 // If we have a TokenFactor, we handle it specially.
2099 if (User->getOpcode() != ISD::TokenFactor) {
2100 // If the node isn't a token factor and isn't part of our pattern, then it
2101 // must be a random chained node in between two nodes we're selecting.
2102 // This happens when we have something like:
2107 // Because we structurally match the load/store as a read/modify/write,
2108 // but the call is chained between them. We cannot fold in this case
2109 // because it would induce a cycle in the graph.
2110 if (!std::count(ChainedNodesInPattern.begin(),
2111 ChainedNodesInPattern.end(), User))
2112 return CR_InducesCycle;
2114 // Otherwise we found a node that is part of our pattern. For example in:
2118 // This would happen when we're scanning down from the load and see the
2119 // store as a user. Record that there is a use of ChainedNode that is
2120 // part of the pattern and keep scanning uses.
2121 Result = CR_LeadsToInteriorNode;
2122 InteriorChainedNodes.push_back(User);
2126 // If we found a TokenFactor, there are two cases to consider: first if the
2127 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2128 // uses of the TF are in our pattern) we just want to ignore it. Second,
2129 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2135 // | \ DAG's like cheese
2138 // [TokenFactor] [Op]
2145 // In this case, the TokenFactor becomes part of our match and we rewrite it
2146 // as a new TokenFactor.
2148 // To distinguish these two cases, do a recursive walk down the uses.
2149 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2151 // If the uses of the TokenFactor are just already-selected nodes, ignore
2152 // it, it is "below" our pattern.
2154 case CR_InducesCycle:
2155 // If the uses of the TokenFactor lead to nodes that are not part of our
2156 // pattern that are not selected, folding would turn this into a cycle,
2158 return CR_InducesCycle;
2159 case CR_LeadsToInteriorNode:
2160 break; // Otherwise, keep processing.
2163 // Okay, we know we're in the interesting interior case. The TokenFactor
2164 // is now going to be considered part of the pattern so that we rewrite its
2165 // uses (it may have uses that are not part of the pattern) with the
2166 // ultimate chain result of the generated code. We will also add its chain
2167 // inputs as inputs to the ultimate TokenFactor we create.
2168 Result = CR_LeadsToInteriorNode;
2169 ChainedNodesInPattern.push_back(User);
2170 InteriorChainedNodes.push_back(User);
2177 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2178 /// operation for when the pattern matched at least one node with a chains. The
2179 /// input vector contains a list of all of the chained nodes that we match. We
2180 /// must determine if this is a valid thing to cover (i.e. matching it won't
2181 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2182 /// be used as the input node chain for the generated nodes.
2184 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2185 SelectionDAG *CurDAG) {
2186 // Walk all of the chained nodes we've matched, recursively scanning down the
2187 // users of the chain result. This adds any TokenFactor nodes that are caught
2188 // in between chained nodes to the chained and interior nodes list.
2189 SmallVector<SDNode*, 3> InteriorChainedNodes;
2190 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2191 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2192 InteriorChainedNodes) == CR_InducesCycle)
2193 return SDValue(); // Would induce a cycle.
2196 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2197 // that we are interested in. Form our input TokenFactor node.
2198 SmallVector<SDValue, 3> InputChains;
2199 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2200 // Add the input chain of this node to the InputChains list (which will be
2201 // the operands of the generated TokenFactor) if it's not an interior node.
2202 SDNode *N = ChainNodesMatched[i];
2203 if (N->getOpcode() != ISD::TokenFactor) {
2204 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2207 // Otherwise, add the input chain.
2208 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2209 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2210 InputChains.push_back(InChain);
2214 // If we have a token factor, we want to add all inputs of the token factor
2215 // that are not part of the pattern we're matching.
2216 for (const SDValue &Op : N->op_values()) {
2217 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2219 InputChains.push_back(Op);
2223 if (InputChains.size() == 1)
2224 return InputChains[0];
2225 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2226 MVT::Other, InputChains);
2229 /// MorphNode - Handle morphing a node in place for the selector.
2230 SDNode *SelectionDAGISel::
2231 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2232 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2233 // It is possible we're using MorphNodeTo to replace a node with no
2234 // normal results with one that has a normal result (or we could be
2235 // adding a chain) and the input could have glue and chains as well.
2236 // In this case we need to shift the operands down.
2237 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2238 // than the old isel though.
2239 int OldGlueResultNo = -1, OldChainResultNo = -1;
2241 unsigned NTMNumResults = Node->getNumValues();
2242 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2243 OldGlueResultNo = NTMNumResults-1;
2244 if (NTMNumResults != 1 &&
2245 Node->getValueType(NTMNumResults-2) == MVT::Other)
2246 OldChainResultNo = NTMNumResults-2;
2247 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2248 OldChainResultNo = NTMNumResults-1;
2250 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2251 // that this deletes operands of the old node that become dead.
2252 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2254 // MorphNodeTo can operate in two ways: if an existing node with the
2255 // specified operands exists, it can just return it. Otherwise, it
2256 // updates the node in place to have the requested operands.
2258 // If we updated the node in place, reset the node ID. To the isel,
2259 // this should be just like a newly allocated machine node.
2263 unsigned ResNumResults = Res->getNumValues();
2264 // Move the glue if needed.
2265 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2266 (unsigned)OldGlueResultNo != ResNumResults-1)
2267 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2268 SDValue(Res, ResNumResults-1));
2270 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2273 // Move the chain reference if needed.
2274 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2275 (unsigned)OldChainResultNo != ResNumResults-1)
2276 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2277 SDValue(Res, ResNumResults-1));
2279 // Otherwise, no replacement happened because the node already exists. Replace
2280 // Uses of the old node with the new one.
2282 CurDAG->ReplaceAllUsesWith(Node, Res);
2287 /// CheckSame - Implements OP_CheckSame.
2288 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2289 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2291 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2292 // Accept if it is exactly the same as a previously recorded node.
2293 unsigned RecNo = MatcherTable[MatcherIndex++];
2294 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2295 return N == RecordedNodes[RecNo].first;
2298 /// CheckChildSame - Implements OP_CheckChildXSame.
2299 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2300 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2302 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2304 if (ChildNo >= N.getNumOperands())
2305 return false; // Match fails if out of range child #.
2306 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2310 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2311 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2312 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2313 const SelectionDAGISel &SDISel) {
2314 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2317 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2318 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2319 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2320 const SelectionDAGISel &SDISel, SDNode *N) {
2321 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2324 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2325 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2327 uint16_t Opc = MatcherTable[MatcherIndex++];
2328 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2329 return N->getOpcode() == Opc;
2332 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2333 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N,
2334 const TargetLowering *TLI, const DataLayout &DL) {
2335 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2336 if (N.getValueType() == VT) return true;
2338 // Handle the case when VT is iPTR.
2339 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(DL);
2342 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2343 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2344 SDValue N, const TargetLowering *TLI, const DataLayout &DL,
2346 if (ChildNo >= N.getNumOperands())
2347 return false; // Match fails if out of range child #.
2348 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI,
2352 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2353 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2355 return cast<CondCodeSDNode>(N)->get() ==
2356 (ISD::CondCode)MatcherTable[MatcherIndex++];
2359 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2360 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2361 SDValue N, const TargetLowering *TLI, const DataLayout &DL) {
2362 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2363 if (cast<VTSDNode>(N)->getVT() == VT)
2366 // Handle the case when VT is iPTR.
2367 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL);
2370 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2371 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2373 int64_t Val = MatcherTable[MatcherIndex++];
2375 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2377 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2378 return C && C->getSExtValue() == Val;
2381 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2382 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2383 SDValue N, unsigned ChildNo) {
2384 if (ChildNo >= N.getNumOperands())
2385 return false; // Match fails if out of range child #.
2386 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2389 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2390 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2391 SDValue N, const SelectionDAGISel &SDISel) {
2392 int64_t Val = MatcherTable[MatcherIndex++];
2394 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2396 if (N->getOpcode() != ISD::AND) return false;
2398 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2399 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2402 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2403 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2404 SDValue N, const SelectionDAGISel &SDISel) {
2405 int64_t Val = MatcherTable[MatcherIndex++];
2407 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2409 if (N->getOpcode() != ISD::OR) return false;
2411 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2412 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2415 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2416 /// scope, evaluate the current node. If the current predicate is known to
2417 /// fail, set Result=true and return anything. If the current predicate is
2418 /// known to pass, set Result=false and return the MatcherIndex to continue
2419 /// with. If the current predicate is unknown, set Result=false and return the
2420 /// MatcherIndex to continue with.
2421 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2422 unsigned Index, SDValue N,
2424 const SelectionDAGISel &SDISel,
2425 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2426 switch (Table[Index++]) {
2429 return Index-1; // Could not evaluate this predicate.
2430 case SelectionDAGISel::OPC_CheckSame:
2431 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2433 case SelectionDAGISel::OPC_CheckChild0Same:
2434 case SelectionDAGISel::OPC_CheckChild1Same:
2435 case SelectionDAGISel::OPC_CheckChild2Same:
2436 case SelectionDAGISel::OPC_CheckChild3Same:
2437 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2438 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2440 case SelectionDAGISel::OPC_CheckPatternPredicate:
2441 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2443 case SelectionDAGISel::OPC_CheckPredicate:
2444 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2446 case SelectionDAGISel::OPC_CheckOpcode:
2447 Result = !::CheckOpcode(Table, Index, N.getNode());
2449 case SelectionDAGISel::OPC_CheckType:
2450 Result = !::CheckType(Table, Index, N, SDISel.TLI,
2451 SDISel.CurDAG->getDataLayout());
2453 case SelectionDAGISel::OPC_CheckChild0Type:
2454 case SelectionDAGISel::OPC_CheckChild1Type:
2455 case SelectionDAGISel::OPC_CheckChild2Type:
2456 case SelectionDAGISel::OPC_CheckChild3Type:
2457 case SelectionDAGISel::OPC_CheckChild4Type:
2458 case SelectionDAGISel::OPC_CheckChild5Type:
2459 case SelectionDAGISel::OPC_CheckChild6Type:
2460 case SelectionDAGISel::OPC_CheckChild7Type:
2461 Result = !::CheckChildType(
2462 Table, Index, N, SDISel.TLI, SDISel.CurDAG->getDataLayout(),
2463 Table[Index - 1] - SelectionDAGISel::OPC_CheckChild0Type);
2465 case SelectionDAGISel::OPC_CheckCondCode:
2466 Result = !::CheckCondCode(Table, Index, N);
2468 case SelectionDAGISel::OPC_CheckValueType:
2469 Result = !::CheckValueType(Table, Index, N, SDISel.TLI,
2470 SDISel.CurDAG->getDataLayout());
2472 case SelectionDAGISel::OPC_CheckInteger:
2473 Result = !::CheckInteger(Table, Index, N);
2475 case SelectionDAGISel::OPC_CheckChild0Integer:
2476 case SelectionDAGISel::OPC_CheckChild1Integer:
2477 case SelectionDAGISel::OPC_CheckChild2Integer:
2478 case SelectionDAGISel::OPC_CheckChild3Integer:
2479 case SelectionDAGISel::OPC_CheckChild4Integer:
2480 Result = !::CheckChildInteger(Table, Index, N,
2481 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2483 case SelectionDAGISel::OPC_CheckAndImm:
2484 Result = !::CheckAndImm(Table, Index, N, SDISel);
2486 case SelectionDAGISel::OPC_CheckOrImm:
2487 Result = !::CheckOrImm(Table, Index, N, SDISel);
2495 /// FailIndex - If this match fails, this is the index to continue with.
2498 /// NodeStack - The node stack when the scope was formed.
2499 SmallVector<SDValue, 4> NodeStack;
2501 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2502 unsigned NumRecordedNodes;
2504 /// NumMatchedMemRefs - The number of matched memref entries.
2505 unsigned NumMatchedMemRefs;
2507 /// InputChain/InputGlue - The current chain/glue
2508 SDValue InputChain, InputGlue;
2510 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2511 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2514 /// \\brief A DAG update listener to keep the matching state
2515 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2516 /// change the DAG while matching. X86 addressing mode matcher is an example
2518 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2520 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2521 SmallVectorImpl<MatchScope> &MatchScopes;
2523 MatchStateUpdater(SelectionDAG &DAG,
2524 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2525 SmallVectorImpl<MatchScope> &MS) :
2526 SelectionDAG::DAGUpdateListener(DAG),
2527 RecordedNodes(RN), MatchScopes(MS) { }
2529 void NodeDeleted(SDNode *N, SDNode *E) override {
2530 // Some early-returns here to avoid the search if we deleted the node or
2531 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2532 // do, so it's unnecessary to update matching state at that point).
2533 // Neither of these can occur currently because we only install this
2534 // update listener during matching a complex patterns.
2535 if (!E || E->isMachineOpcode())
2537 // Performing linear search here does not matter because we almost never
2538 // run this code. You'd have to have a CSE during complex pattern
2540 for (auto &I : RecordedNodes)
2541 if (I.first.getNode() == N)
2544 for (auto &I : MatchScopes)
2545 for (auto &J : I.NodeStack)
2546 if (J.getNode() == N)
2552 SDNode *SelectionDAGISel::
2553 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2554 unsigned TableSize) {
2555 // FIXME: Should these even be selected? Handle these cases in the caller?
2556 switch (NodeToMatch->getOpcode()) {
2559 case ISD::EntryToken: // These nodes remain the same.
2560 case ISD::BasicBlock:
2562 case ISD::RegisterMask:
2563 case ISD::HANDLENODE:
2564 case ISD::MDNODE_SDNODE:
2565 case ISD::TargetConstant:
2566 case ISD::TargetConstantFP:
2567 case ISD::TargetConstantPool:
2568 case ISD::TargetFrameIndex:
2569 case ISD::TargetExternalSymbol:
2571 case ISD::TargetBlockAddress:
2572 case ISD::TargetJumpTable:
2573 case ISD::TargetGlobalTLSAddress:
2574 case ISD::TargetGlobalAddress:
2575 case ISD::TokenFactor:
2576 case ISD::CopyFromReg:
2577 case ISD::CopyToReg:
2579 case ISD::LIFETIME_START:
2580 case ISD::LIFETIME_END:
2581 NodeToMatch->setNodeId(-1); // Mark selected.
2583 case ISD::AssertSext:
2584 case ISD::AssertZext:
2585 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2586 NodeToMatch->getOperand(0));
2588 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2589 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2590 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2591 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2594 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2596 // Set up the node stack with NodeToMatch as the only node on the stack.
2597 SmallVector<SDValue, 8> NodeStack;
2598 SDValue N = SDValue(NodeToMatch, 0);
2599 NodeStack.push_back(N);
2601 // MatchScopes - Scopes used when matching, if a match failure happens, this
2602 // indicates where to continue checking.
2603 SmallVector<MatchScope, 8> MatchScopes;
2605 // RecordedNodes - This is the set of nodes that have been recorded by the
2606 // state machine. The second value is the parent of the node, or null if the
2607 // root is recorded.
2608 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2610 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2612 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2614 // These are the current input chain and glue for use when generating nodes.
2615 // Various Emit operations change these. For example, emitting a copytoreg
2616 // uses and updates these.
2617 SDValue InputChain, InputGlue;
2619 // ChainNodesMatched - If a pattern matches nodes that have input/output
2620 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2621 // which ones they are. The result is captured into this list so that we can
2622 // update the chain results when the pattern is complete.
2623 SmallVector<SDNode*, 3> ChainNodesMatched;
2624 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2626 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2627 NodeToMatch->dump(CurDAG);
2630 // Determine where to start the interpreter. Normally we start at opcode #0,
2631 // but if the state machine starts with an OPC_SwitchOpcode, then we
2632 // accelerate the first lookup (which is guaranteed to be hot) with the
2633 // OpcodeOffset table.
2634 unsigned MatcherIndex = 0;
2636 if (!OpcodeOffset.empty()) {
2637 // Already computed the OpcodeOffset table, just index into it.
2638 if (N.getOpcode() < OpcodeOffset.size())
2639 MatcherIndex = OpcodeOffset[N.getOpcode()];
2640 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2642 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2643 // Otherwise, the table isn't computed, but the state machine does start
2644 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2645 // is the first time we're selecting an instruction.
2648 // Get the size of this case.
2649 unsigned CaseSize = MatcherTable[Idx++];
2651 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2652 if (CaseSize == 0) break;
2654 // Get the opcode, add the index to the table.
2655 uint16_t Opc = MatcherTable[Idx++];
2656 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2657 if (Opc >= OpcodeOffset.size())
2658 OpcodeOffset.resize((Opc+1)*2);
2659 OpcodeOffset[Opc] = Idx;
2663 // Okay, do the lookup for the first opcode.
2664 if (N.getOpcode() < OpcodeOffset.size())
2665 MatcherIndex = OpcodeOffset[N.getOpcode()];
2669 assert(MatcherIndex < TableSize && "Invalid index");
2671 unsigned CurrentOpcodeIndex = MatcherIndex;
2673 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2676 // Okay, the semantics of this operation are that we should push a scope
2677 // then evaluate the first child. However, pushing a scope only to have
2678 // the first check fail (which then pops it) is inefficient. If we can
2679 // determine immediately that the first check (or first several) will
2680 // immediately fail, don't even bother pushing a scope for them.
2684 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2685 if (NumToSkip & 128)
2686 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2687 // Found the end of the scope with no match.
2688 if (NumToSkip == 0) {
2693 FailIndex = MatcherIndex+NumToSkip;
2695 unsigned MatcherIndexOfPredicate = MatcherIndex;
2696 (void)MatcherIndexOfPredicate; // silence warning.
2698 // If we can't evaluate this predicate without pushing a scope (e.g. if
2699 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2700 // push the scope and evaluate the full predicate chain.
2702 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2703 Result, *this, RecordedNodes);
2707 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2708 << "index " << MatcherIndexOfPredicate
2709 << ", continuing at " << FailIndex << "\n");
2710 ++NumDAGIselRetries;
2712 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2713 // move to the next case.
2714 MatcherIndex = FailIndex;
2717 // If the whole scope failed to match, bail.
2718 if (FailIndex == 0) break;
2720 // Push a MatchScope which indicates where to go if the first child fails
2722 MatchScope NewEntry;
2723 NewEntry.FailIndex = FailIndex;
2724 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2725 NewEntry.NumRecordedNodes = RecordedNodes.size();
2726 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2727 NewEntry.InputChain = InputChain;
2728 NewEntry.InputGlue = InputGlue;
2729 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2730 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2731 MatchScopes.push_back(NewEntry);
2734 case OPC_RecordNode: {
2735 // Remember this node, it may end up being an operand in the pattern.
2736 SDNode *Parent = nullptr;
2737 if (NodeStack.size() > 1)
2738 Parent = NodeStack[NodeStack.size()-2].getNode();
2739 RecordedNodes.push_back(std::make_pair(N, Parent));
2743 case OPC_RecordChild0: case OPC_RecordChild1:
2744 case OPC_RecordChild2: case OPC_RecordChild3:
2745 case OPC_RecordChild4: case OPC_RecordChild5:
2746 case OPC_RecordChild6: case OPC_RecordChild7: {
2747 unsigned ChildNo = Opcode-OPC_RecordChild0;
2748 if (ChildNo >= N.getNumOperands())
2749 break; // Match fails if out of range child #.
2751 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2755 case OPC_RecordMemRef:
2756 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2759 case OPC_CaptureGlueInput:
2760 // If the current node has an input glue, capture it in InputGlue.
2761 if (N->getNumOperands() != 0 &&
2762 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2763 InputGlue = N->getOperand(N->getNumOperands()-1);
2766 case OPC_MoveChild: {
2767 unsigned ChildNo = MatcherTable[MatcherIndex++];
2768 if (ChildNo >= N.getNumOperands())
2769 break; // Match fails if out of range child #.
2770 N = N.getOperand(ChildNo);
2771 NodeStack.push_back(N);
2775 case OPC_MoveParent:
2776 // Pop the current node off the NodeStack.
2777 NodeStack.pop_back();
2778 assert(!NodeStack.empty() && "Node stack imbalance!");
2779 N = NodeStack.back();
2783 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2786 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2787 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2788 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2789 Opcode-OPC_CheckChild0Same))
2793 case OPC_CheckPatternPredicate:
2794 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2796 case OPC_CheckPredicate:
2797 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2801 case OPC_CheckComplexPat: {
2802 unsigned CPNum = MatcherTable[MatcherIndex++];
2803 unsigned RecNo = MatcherTable[MatcherIndex++];
2804 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2806 // If target can modify DAG during matching, keep the matching state
2808 std::unique_ptr<MatchStateUpdater> MSU;
2809 if (ComplexPatternFuncMutatesDAG())
2810 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2813 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2814 RecordedNodes[RecNo].first, CPNum,
2819 case OPC_CheckOpcode:
2820 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2824 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI,
2825 CurDAG->getDataLayout()))
2829 case OPC_SwitchOpcode: {
2830 unsigned CurNodeOpcode = N.getOpcode();
2831 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2834 // Get the size of this case.
2835 CaseSize = MatcherTable[MatcherIndex++];
2837 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2838 if (CaseSize == 0) break;
2840 uint16_t Opc = MatcherTable[MatcherIndex++];
2841 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2843 // If the opcode matches, then we will execute this case.
2844 if (CurNodeOpcode == Opc)
2847 // Otherwise, skip over this case.
2848 MatcherIndex += CaseSize;
2851 // If no cases matched, bail out.
2852 if (CaseSize == 0) break;
2854 // Otherwise, execute the case we found.
2855 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2856 << " to " << MatcherIndex << "\n");
2860 case OPC_SwitchType: {
2861 MVT CurNodeVT = N.getSimpleValueType();
2862 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2865 // Get the size of this case.
2866 CaseSize = MatcherTable[MatcherIndex++];
2868 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2869 if (CaseSize == 0) break;
2871 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2872 if (CaseVT == MVT::iPTR)
2873 CaseVT = TLI->getPointerTy(CurDAG->getDataLayout());
2875 // If the VT matches, then we will execute this case.
2876 if (CurNodeVT == CaseVT)
2879 // Otherwise, skip over this case.
2880 MatcherIndex += CaseSize;
2883 // If no cases matched, bail out.
2884 if (CaseSize == 0) break;
2886 // Otherwise, execute the case we found.
2887 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2888 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2891 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2892 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2893 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2894 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2895 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2896 CurDAG->getDataLayout(),
2897 Opcode - OPC_CheckChild0Type))
2900 case OPC_CheckCondCode:
2901 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2903 case OPC_CheckValueType:
2904 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI,
2905 CurDAG->getDataLayout()))
2908 case OPC_CheckInteger:
2909 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2911 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2912 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2913 case OPC_CheckChild4Integer:
2914 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2915 Opcode-OPC_CheckChild0Integer)) break;
2917 case OPC_CheckAndImm:
2918 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2920 case OPC_CheckOrImm:
2921 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2924 case OPC_CheckFoldableChainNode: {
2925 assert(NodeStack.size() != 1 && "No parent node");
2926 // Verify that all intermediate nodes between the root and this one have
2928 bool HasMultipleUses = false;
2929 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2930 if (!NodeStack[i].hasOneUse()) {
2931 HasMultipleUses = true;
2934 if (HasMultipleUses) break;
2936 // Check to see that the target thinks this is profitable to fold and that
2937 // we can fold it without inducing cycles in the graph.
2938 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2940 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2941 NodeToMatch, OptLevel,
2942 true/*We validate our own chains*/))
2947 case OPC_EmitInteger: {
2948 MVT::SimpleValueType VT =
2949 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2950 int64_t Val = MatcherTable[MatcherIndex++];
2952 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2953 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2954 CurDAG->getTargetConstant(Val, SDLoc(NodeToMatch),
2958 case OPC_EmitRegister: {
2959 MVT::SimpleValueType VT =
2960 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2961 unsigned RegNo = MatcherTable[MatcherIndex++];
2962 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2963 CurDAG->getRegister(RegNo, VT), nullptr));
2966 case OPC_EmitRegister2: {
2967 // For targets w/ more than 256 register names, the register enum
2968 // values are stored in two bytes in the matcher table (just like
2970 MVT::SimpleValueType VT =
2971 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2972 unsigned RegNo = MatcherTable[MatcherIndex++];
2973 RegNo |= MatcherTable[MatcherIndex++] << 8;
2974 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2975 CurDAG->getRegister(RegNo, VT), nullptr));
2979 case OPC_EmitConvertToTarget: {
2980 // Convert from IMM/FPIMM to target version.
2981 unsigned RecNo = MatcherTable[MatcherIndex++];
2982 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2983 SDValue Imm = RecordedNodes[RecNo].first;
2985 if (Imm->getOpcode() == ISD::Constant) {
2986 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2987 Imm = CurDAG->getConstant(*Val, SDLoc(NodeToMatch), Imm.getValueType(),
2989 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2990 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2991 Imm = CurDAG->getConstantFP(*Val, SDLoc(NodeToMatch),
2992 Imm.getValueType(), true);
2995 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2999 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
3000 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
3001 // These are space-optimized forms of OPC_EmitMergeInputChains.
3002 assert(!InputChain.getNode() &&
3003 "EmitMergeInputChains should be the first chain producing node");
3004 assert(ChainNodesMatched.empty() &&
3005 "Should only have one EmitMergeInputChains per match");
3007 // Read all of the chained nodes.
3008 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
3009 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3010 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3012 // FIXME: What if other value results of the node have uses not matched
3014 if (ChainNodesMatched.back() != NodeToMatch &&
3015 !RecordedNodes[RecNo].first.hasOneUse()) {
3016 ChainNodesMatched.clear();
3020 // Merge the input chains if they are not intra-pattern references.
3021 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3023 if (!InputChain.getNode())
3024 break; // Failed to merge.
3028 case OPC_EmitMergeInputChains: {
3029 assert(!InputChain.getNode() &&
3030 "EmitMergeInputChains should be the first chain producing node");
3031 // This node gets a list of nodes we matched in the input that have
3032 // chains. We want to token factor all of the input chains to these nodes
3033 // together. However, if any of the input chains is actually one of the
3034 // nodes matched in this pattern, then we have an intra-match reference.
3035 // Ignore these because the newly token factored chain should not refer to
3037 unsigned NumChains = MatcherTable[MatcherIndex++];
3038 assert(NumChains != 0 && "Can't TF zero chains");
3040 assert(ChainNodesMatched.empty() &&
3041 "Should only have one EmitMergeInputChains per match");
3043 // Read all of the chained nodes.
3044 for (unsigned i = 0; i != NumChains; ++i) {
3045 unsigned RecNo = MatcherTable[MatcherIndex++];
3046 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3047 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3049 // FIXME: What if other value results of the node have uses not matched
3051 if (ChainNodesMatched.back() != NodeToMatch &&
3052 !RecordedNodes[RecNo].first.hasOneUse()) {
3053 ChainNodesMatched.clear();
3058 // If the inner loop broke out, the match fails.
3059 if (ChainNodesMatched.empty())
3062 // Merge the input chains if they are not intra-pattern references.
3063 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3065 if (!InputChain.getNode())
3066 break; // Failed to merge.
3071 case OPC_EmitCopyToReg: {
3072 unsigned RecNo = MatcherTable[MatcherIndex++];
3073 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3074 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3076 if (!InputChain.getNode())
3077 InputChain = CurDAG->getEntryNode();
3079 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3080 DestPhysReg, RecordedNodes[RecNo].first,
3083 InputGlue = InputChain.getValue(1);
3087 case OPC_EmitNodeXForm: {
3088 unsigned XFormNo = MatcherTable[MatcherIndex++];
3089 unsigned RecNo = MatcherTable[MatcherIndex++];
3090 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3091 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3092 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3097 case OPC_MorphNodeTo: {
3098 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3099 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3100 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3101 // Get the result VT list.
3102 unsigned NumVTs = MatcherTable[MatcherIndex++];
3103 SmallVector<EVT, 4> VTs;
3104 for (unsigned i = 0; i != NumVTs; ++i) {
3105 MVT::SimpleValueType VT =
3106 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3107 if (VT == MVT::iPTR)
3108 VT = TLI->getPointerTy(CurDAG->getDataLayout()).SimpleTy;
3112 if (EmitNodeInfo & OPFL_Chain)
3113 VTs.push_back(MVT::Other);
3114 if (EmitNodeInfo & OPFL_GlueOutput)
3115 VTs.push_back(MVT::Glue);
3117 // This is hot code, so optimize the two most common cases of 1 and 2
3120 if (VTs.size() == 1)
3121 VTList = CurDAG->getVTList(VTs[0]);
3122 else if (VTs.size() == 2)
3123 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3125 VTList = CurDAG->getVTList(VTs);
3127 // Get the operand list.
3128 unsigned NumOps = MatcherTable[MatcherIndex++];
3129 SmallVector<SDValue, 8> Ops;
3130 for (unsigned i = 0; i != NumOps; ++i) {
3131 unsigned RecNo = MatcherTable[MatcherIndex++];
3133 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3135 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3136 Ops.push_back(RecordedNodes[RecNo].first);
3139 // If there are variadic operands to add, handle them now.
3140 if (EmitNodeInfo & OPFL_VariadicInfo) {
3141 // Determine the start index to copy from.
3142 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3143 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3144 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3145 "Invalid variadic node");
3146 // Copy all of the variadic operands, not including a potential glue
3148 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3150 SDValue V = NodeToMatch->getOperand(i);
3151 if (V.getValueType() == MVT::Glue) break;
3156 // If this has chain/glue inputs, add them.
3157 if (EmitNodeInfo & OPFL_Chain)
3158 Ops.push_back(InputChain);
3159 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3160 Ops.push_back(InputGlue);
3163 SDNode *Res = nullptr;
3164 if (Opcode != OPC_MorphNodeTo) {
3165 // If this is a normal EmitNode command, just create the new node and
3166 // add the results to the RecordedNodes list.
3167 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3170 // Add all the non-glue/non-chain results to the RecordedNodes list.
3171 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3172 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3173 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3177 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3178 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3180 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3181 // We will visit the equivalent node later.
3182 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3186 // If the node had chain/glue results, update our notion of the current
3188 if (EmitNodeInfo & OPFL_GlueOutput) {
3189 InputGlue = SDValue(Res, VTs.size()-1);
3190 if (EmitNodeInfo & OPFL_Chain)
3191 InputChain = SDValue(Res, VTs.size()-2);
3192 } else if (EmitNodeInfo & OPFL_Chain)
3193 InputChain = SDValue(Res, VTs.size()-1);
3195 // If the OPFL_MemRefs glue is set on this node, slap all of the
3196 // accumulated memrefs onto it.
3198 // FIXME: This is vastly incorrect for patterns with multiple outputs
3199 // instructions that access memory and for ComplexPatterns that match
3201 if (EmitNodeInfo & OPFL_MemRefs) {
3202 // Only attach load or store memory operands if the generated
3203 // instruction may load or store.
3204 const MCInstrDesc &MCID = TII->get(TargetOpc);
3205 bool mayLoad = MCID.mayLoad();
3206 bool mayStore = MCID.mayStore();
3208 unsigned NumMemRefs = 0;
3209 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3210 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3211 if ((*I)->isLoad()) {
3214 } else if ((*I)->isStore()) {
3222 MachineSDNode::mmo_iterator MemRefs =
3223 MF->allocateMemRefsArray(NumMemRefs);
3225 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3226 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3227 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3228 if ((*I)->isLoad()) {
3231 } else if ((*I)->isStore()) {
3239 cast<MachineSDNode>(Res)
3240 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3244 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3245 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3247 // If this was a MorphNodeTo then we're completely done!
3248 if (Opcode == OPC_MorphNodeTo) {
3249 // Update chain and glue uses.
3250 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3251 InputGlue, GlueResultNodesMatched, true);
3258 case OPC_MarkGlueResults: {
3259 unsigned NumNodes = MatcherTable[MatcherIndex++];
3261 // Read and remember all the glue-result nodes.
3262 for (unsigned i = 0; i != NumNodes; ++i) {
3263 unsigned RecNo = MatcherTable[MatcherIndex++];
3265 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3267 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3268 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3273 case OPC_CompleteMatch: {
3274 // The match has been completed, and any new nodes (if any) have been
3275 // created. Patch up references to the matched dag to use the newly
3277 unsigned NumResults = MatcherTable[MatcherIndex++];
3279 for (unsigned i = 0; i != NumResults; ++i) {
3280 unsigned ResSlot = MatcherTable[MatcherIndex++];
3282 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3284 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3285 SDValue Res = RecordedNodes[ResSlot].first;
3287 assert(i < NodeToMatch->getNumValues() &&
3288 NodeToMatch->getValueType(i) != MVT::Other &&
3289 NodeToMatch->getValueType(i) != MVT::Glue &&
3290 "Invalid number of results to complete!");
3291 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3292 NodeToMatch->getValueType(i) == MVT::iPTR ||
3293 Res.getValueType() == MVT::iPTR ||
3294 NodeToMatch->getValueType(i).getSizeInBits() ==
3295 Res.getValueType().getSizeInBits()) &&
3296 "invalid replacement");
3297 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3300 // If the root node defines glue, add it to the glue nodes to update list.
3301 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3302 GlueResultNodesMatched.push_back(NodeToMatch);
3304 // Update chain and glue uses.
3305 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3306 InputGlue, GlueResultNodesMatched, false);
3308 assert(NodeToMatch->use_empty() &&
3309 "Didn't replace all uses of the node?");
3311 // FIXME: We just return here, which interacts correctly with SelectRoot
3312 // above. We should fix this to not return an SDNode* anymore.
3317 // If the code reached this point, then the match failed. See if there is
3318 // another child to try in the current 'Scope', otherwise pop it until we
3319 // find a case to check.
3320 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3321 ++NumDAGIselRetries;
3323 if (MatchScopes.empty()) {
3324 CannotYetSelect(NodeToMatch);
3328 // Restore the interpreter state back to the point where the scope was
3330 MatchScope &LastScope = MatchScopes.back();
3331 RecordedNodes.resize(LastScope.NumRecordedNodes);
3333 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3334 N = NodeStack.back();
3336 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3337 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3338 MatcherIndex = LastScope.FailIndex;
3340 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3342 InputChain = LastScope.InputChain;
3343 InputGlue = LastScope.InputGlue;
3344 if (!LastScope.HasChainNodesMatched)
3345 ChainNodesMatched.clear();
3346 if (!LastScope.HasGlueResultNodesMatched)
3347 GlueResultNodesMatched.clear();
3349 // Check to see what the offset is at the new MatcherIndex. If it is zero
3350 // we have reached the end of this scope, otherwise we have another child
3351 // in the current scope to try.
3352 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3353 if (NumToSkip & 128)
3354 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3356 // If we have another child in this scope to match, update FailIndex and
3358 if (NumToSkip != 0) {
3359 LastScope.FailIndex = MatcherIndex+NumToSkip;
3363 // End of this scope, pop it and try the next child in the containing
3365 MatchScopes.pop_back();
3372 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3374 raw_string_ostream Msg(msg);
3375 Msg << "Cannot select: ";
3377 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3378 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3379 N->getOpcode() != ISD::INTRINSIC_VOID) {
3380 N->printrFull(Msg, CurDAG);
3381 Msg << "\nIn function: " << MF->getName();
3383 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3385 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3386 if (iid < Intrinsic::num_intrinsics)
3387 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3388 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3389 Msg << "target intrinsic %" << TII->getName(iid);
3391 Msg << "unknown intrinsic #" << iid;
3393 report_fatal_error(Msg.str());
3396 char SelectionDAGISel::ID = 0;