1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/Compiler.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
60 cl::desc("Pop up a window to show SUnit dags after they are processed"));
62 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
65 //===---------------------------------------------------------------------===//
67 /// RegisterScheduler class - Track the registration of instruction schedulers.
69 //===---------------------------------------------------------------------===//
70 MachinePassRegistry RegisterScheduler::Registry;
72 //===---------------------------------------------------------------------===//
74 /// ISHeuristic command line option for instruction schedulers.
76 //===---------------------------------------------------------------------===//
78 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
79 RegisterPassParser<RegisterScheduler> >
80 ISHeuristic("pre-RA-sched",
81 cl::init(&createDefaultScheduler),
82 cl::desc("Instruction schedulers available (before register"
85 static RegisterScheduler
86 defaultListDAGScheduler("default", " Best scheduler for the target",
87 createDefaultScheduler);
90 namespace { struct SDISelAsmOperandInfo; }
92 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
93 /// MVT::ValueTypes that represent all the individual underlying
94 /// non-aggregate types that comprise it.
95 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
96 SmallVectorImpl<MVT::ValueType> &ValueVTs) {
97 // Given a struct type, recursively traverse the elements.
98 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
99 for (StructType::element_iterator EI = STy->element_begin(),
100 EB = STy->element_end();
102 ComputeValueVTs(TLI, *EI, ValueVTs);
105 // Given an array type, recursively traverse the elements.
106 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
107 const Type *EltTy = ATy->getElementType();
108 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
109 ComputeValueVTs(TLI, EltTy, ValueVTs);
112 // Base case: we can get an MVT::ValueType for this LLVM IR type.
113 ValueVTs.push_back(TLI.getValueType(Ty));
117 /// RegsForValue - This struct represents the registers (physical or virtual)
118 /// that a particular set of values is assigned, and the type information about
119 /// the value. The most common situation is to represent one value at a time,
120 /// but struct or array values are handled element-wise as multiple values.
121 /// The splitting of aggregates is performed recursively, so that we never
122 /// have aggregate-typed registers. The values at this point do not necessarily
123 /// have legal types, so each value may require one or more registers of some
126 struct VISIBILITY_HIDDEN RegsForValue {
127 /// TLI - The TargetLowering object.
129 const TargetLowering *TLI;
131 /// ValueVTs - The value types of the values, which may not be legal, and
132 /// may need be promoted or synthesized from one or more registers.
134 SmallVector<MVT::ValueType, 4> ValueVTs;
136 /// RegVTs - The value types of the registers. This is the same size as
137 /// ValueVTs and it records, for each value, what the type of the assigned
138 /// register or registers are. (Individual values are never synthesized
139 /// from more than one type of register.)
141 /// With virtual registers, the contents of RegVTs is redundant with TLI's
142 /// getRegisterType member function, however when with physical registers
143 /// it is necessary to have a separate record of the types.
145 SmallVector<MVT::ValueType, 4> RegVTs;
147 /// Regs - This list holds the registers assigned to the values.
148 /// Each legal or promoted value requires one register, and each
149 /// expanded value requires multiple registers.
151 SmallVector<unsigned, 4> Regs;
153 RegsForValue() : TLI(0) {}
155 RegsForValue(const TargetLowering &tli,
156 const SmallVector<unsigned, 4> ®s,
157 MVT::ValueType regvt, MVT::ValueType valuevt)
158 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
159 RegsForValue(const TargetLowering &tli,
160 const SmallVector<unsigned, 4> ®s,
161 const SmallVector<MVT::ValueType, 4> ®vts,
162 const SmallVector<MVT::ValueType, 4> &valuevts)
163 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
164 RegsForValue(const TargetLowering &tli,
165 unsigned Reg, const Type *Ty) : TLI(&tli) {
166 ComputeValueVTs(tli, Ty, ValueVTs);
168 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
169 MVT::ValueType ValueVT = ValueVTs[Value];
170 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
171 MVT::ValueType RegisterVT = TLI->getRegisterType(ValueVT);
172 for (unsigned i = 0; i != NumRegs; ++i)
173 Regs.push_back(Reg + i);
174 RegVTs.push_back(RegisterVT);
179 /// append - Add the specified values to this one.
180 void append(const RegsForValue &RHS) {
182 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
183 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
184 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
188 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
189 /// this value and returns the result as a ValueVTs value. This uses
190 /// Chain/Flag as the input and updates them for the output Chain/Flag.
191 /// If the Flag pointer is NULL, no flag is used.
192 SDOperand getCopyFromRegs(SelectionDAG &DAG,
193 SDOperand &Chain, SDOperand *Flag) const;
195 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
196 /// specified value into the registers specified by this object. This uses
197 /// Chain/Flag as the input and updates them for the output Chain/Flag.
198 /// If the Flag pointer is NULL, no flag is used.
199 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
200 SDOperand &Chain, SDOperand *Flag) const;
202 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
203 /// operand list. This adds the code marker and includes the number of
204 /// values added into it.
205 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
206 std::vector<SDOperand> &Ops) const;
211 //===--------------------------------------------------------------------===//
212 /// createDefaultScheduler - This creates an instruction scheduler appropriate
214 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
216 MachineBasicBlock *BB) {
217 TargetLowering &TLI = IS->getTargetLowering();
219 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
220 return createTDListDAGScheduler(IS, DAG, BB);
222 assert(TLI.getSchedulingPreference() ==
223 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
224 return createBURRListDAGScheduler(IS, DAG, BB);
229 //===--------------------------------------------------------------------===//
230 /// FunctionLoweringInfo - This contains information that is global to a
231 /// function that is used when lowering a region of the function.
232 class FunctionLoweringInfo {
237 MachineRegisterInfo &RegInfo;
239 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
241 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
242 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
244 /// ValueMap - Since we emit code for the function a basic block at a time,
245 /// we must remember which virtual registers hold the values for
246 /// cross-basic-block values.
247 DenseMap<const Value*, unsigned> ValueMap;
249 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
250 /// the entry block. This allows the allocas to be efficiently referenced
251 /// anywhere in the function.
252 std::map<const AllocaInst*, int> StaticAllocaMap;
255 SmallSet<Instruction*, 8> CatchInfoLost;
256 SmallSet<Instruction*, 8> CatchInfoFound;
259 unsigned MakeReg(MVT::ValueType VT) {
260 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
263 /// isExportedInst - Return true if the specified value is an instruction
264 /// exported from its block.
265 bool isExportedInst(const Value *V) {
266 return ValueMap.count(V);
269 unsigned CreateRegForValue(const Value *V);
271 unsigned InitializeRegForValue(const Value *V) {
272 unsigned &R = ValueMap[V];
273 assert(R == 0 && "Already initialized this value register!");
274 return R = CreateRegForValue(V);
279 /// isSelector - Return true if this instruction is a call to the
280 /// eh.selector intrinsic.
281 static bool isSelector(Instruction *I) {
282 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
283 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
284 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
288 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
289 /// PHI nodes or outside of the basic block that defines it, or used by a
290 /// switch or atomic instruction, which may expand to multiple basic blocks.
291 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
292 if (isa<PHINode>(I)) return true;
293 BasicBlock *BB = I->getParent();
294 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
295 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
296 // FIXME: Remove switchinst special case.
297 isa<SwitchInst>(*UI))
302 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
303 /// entry block, return true. This includes arguments used by switches, since
304 /// the switch may expand into multiple basic blocks.
305 static bool isOnlyUsedInEntryBlock(Argument *A) {
306 BasicBlock *Entry = A->getParent()->begin();
307 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
308 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
309 return false; // Use not in entry block.
313 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
314 Function &fn, MachineFunction &mf)
315 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
317 // Create a vreg for each argument register that is not dead and is used
318 // outside of the entry block for the function.
319 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
321 if (!isOnlyUsedInEntryBlock(AI))
322 InitializeRegForValue(AI);
324 // Initialize the mapping of values to registers. This is only set up for
325 // instruction values that are used outside of the block that defines
327 Function::iterator BB = Fn.begin(), EB = Fn.end();
328 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
329 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
330 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
331 const Type *Ty = AI->getAllocatedType();
332 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
334 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
337 TySize *= CUI->getZExtValue(); // Get total allocated size.
338 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
339 StaticAllocaMap[AI] =
340 MF.getFrameInfo()->CreateStackObject(TySize, Align);
343 for (; BB != EB; ++BB)
344 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
345 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
346 if (!isa<AllocaInst>(I) ||
347 !StaticAllocaMap.count(cast<AllocaInst>(I)))
348 InitializeRegForValue(I);
350 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
351 // also creates the initial PHI MachineInstrs, though none of the input
352 // operands are populated.
353 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
354 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
356 MF.getBasicBlockList().push_back(MBB);
358 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
361 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
362 if (PN->use_empty()) continue;
364 MVT::ValueType VT = TLI.getValueType(PN->getType());
365 unsigned NumRegisters = TLI.getNumRegisters(VT);
366 unsigned PHIReg = ValueMap[PN];
367 assert(PHIReg && "PHI node does not have an assigned virtual register!");
368 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
369 for (unsigned i = 0; i != NumRegisters; ++i)
370 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
375 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
376 /// the correctly promoted or expanded types. Assign these registers
377 /// consecutive vreg numbers and return the first assigned number.
379 /// In the case that the given value has struct or array type, this function
380 /// will assign registers for each member or element.
382 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
383 SmallVector<MVT::ValueType, 4> ValueVTs;
384 ComputeValueVTs(TLI, V->getType(), ValueVTs);
386 unsigned FirstReg = 0;
387 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
388 MVT::ValueType ValueVT = ValueVTs[Value];
389 MVT::ValueType RegisterVT = TLI.getRegisterType(ValueVT);
391 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
392 for (unsigned i = 0; i != NumRegs; ++i) {
393 unsigned R = MakeReg(RegisterVT);
394 if (!FirstReg) FirstReg = R;
400 //===----------------------------------------------------------------------===//
401 /// SelectionDAGLowering - This is the common target-independent lowering
402 /// implementation that is parameterized by a TargetLowering object.
403 /// Also, targets can overload any lowering method.
406 class SelectionDAGLowering {
407 MachineBasicBlock *CurMBB;
409 DenseMap<const Value*, SDOperand> NodeMap;
411 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
412 /// them up and then emit token factor nodes when possible. This allows us to
413 /// get simple disambiguation between loads without worrying about alias
415 std::vector<SDOperand> PendingLoads;
417 /// PendingExports - CopyToReg nodes that copy values to virtual registers
418 /// for export to other blocks need to be emitted before any terminator
419 /// instruction, but they have no other ordering requirements. We bunch them
420 /// up and the emit a single tokenfactor for them just before terminator
422 std::vector<SDOperand> PendingExports;
424 /// Case - A struct to record the Value for a switch case, and the
425 /// case's target basic block.
429 MachineBasicBlock* BB;
431 Case() : Low(0), High(0), BB(0) { }
432 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
433 Low(low), High(high), BB(bb) { }
434 uint64_t size() const {
435 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
436 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
437 return (rHigh - rLow + 1ULL);
443 MachineBasicBlock* BB;
446 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
447 Mask(mask), BB(bb), Bits(bits) { }
450 typedef std::vector<Case> CaseVector;
451 typedef std::vector<CaseBits> CaseBitsVector;
452 typedef CaseVector::iterator CaseItr;
453 typedef std::pair<CaseItr, CaseItr> CaseRange;
455 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
456 /// of conditional branches.
458 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
459 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
461 /// CaseBB - The MBB in which to emit the compare and branch
462 MachineBasicBlock *CaseBB;
463 /// LT, GE - If nonzero, we know the current case value must be less-than or
464 /// greater-than-or-equal-to these Constants.
467 /// Range - A pair of iterators representing the range of case values to be
468 /// processed at this point in the binary search tree.
472 typedef std::vector<CaseRec> CaseRecVector;
474 /// The comparison function for sorting the switch case values in the vector.
475 /// WARNING: Case ranges should be disjoint!
477 bool operator () (const Case& C1, const Case& C2) {
478 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
479 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
480 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
481 return CI1->getValue().slt(CI2->getValue());
486 bool operator () (const CaseBits& C1, const CaseBits& C2) {
487 return C1.Bits > C2.Bits;
491 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
494 // TLI - This is information that describes the available target features we
495 // need for lowering. This indicates when operations are unavailable,
496 // implemented with a libcall, etc.
499 const TargetData *TD;
502 /// SwitchCases - Vector of CaseBlock structures used to communicate
503 /// SwitchInst code generation information.
504 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
505 /// JTCases - Vector of JumpTable structures used to communicate
506 /// SwitchInst code generation information.
507 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
508 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
510 /// FuncInfo - Information about the function as a whole.
512 FunctionLoweringInfo &FuncInfo;
514 /// GCI - Garbage collection metadata for the function.
515 CollectorMetadata *GCI;
517 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
519 FunctionLoweringInfo &funcinfo,
520 CollectorMetadata *gci)
521 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
522 FuncInfo(funcinfo), GCI(gci) {
525 /// getRoot - Return the current virtual root of the Selection DAG,
526 /// flushing any PendingLoad items. This must be done before emitting
527 /// a store or any other node that may need to be ordered after any
528 /// prior load instructions.
530 SDOperand getRoot() {
531 if (PendingLoads.empty())
532 return DAG.getRoot();
534 if (PendingLoads.size() == 1) {
535 SDOperand Root = PendingLoads[0];
537 PendingLoads.clear();
541 // Otherwise, we have to make a token factor node.
542 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
543 &PendingLoads[0], PendingLoads.size());
544 PendingLoads.clear();
549 /// getControlRoot - Similar to getRoot, but instead of flushing all the
550 /// PendingLoad items, flush all the PendingExports items. It is necessary
551 /// to do this before emitting a terminator instruction.
553 SDOperand getControlRoot() {
554 SDOperand Root = DAG.getRoot();
556 if (PendingExports.empty())
559 // Turn all of the CopyToReg chains into one factored node.
560 if (Root.getOpcode() != ISD::EntryToken) {
561 unsigned i = 0, e = PendingExports.size();
562 for (; i != e; ++i) {
563 assert(PendingExports[i].Val->getNumOperands() > 1);
564 if (PendingExports[i].Val->getOperand(0) == Root)
565 break; // Don't add the root if we already indirectly depend on it.
569 PendingExports.push_back(Root);
572 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
574 PendingExports.size());
575 PendingExports.clear();
580 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
582 void visit(Instruction &I) { visit(I.getOpcode(), I); }
584 void visit(unsigned Opcode, User &I) {
585 // Note: this doesn't use InstVisitor, because it has to work with
586 // ConstantExpr's in addition to instructions.
588 default: assert(0 && "Unknown instruction type encountered!");
590 // Build the switch statement using the Instruction.def file.
591 #define HANDLE_INST(NUM, OPCODE, CLASS) \
592 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
593 #include "llvm/Instruction.def"
597 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
599 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
600 const Value *SV, SDOperand Root,
601 bool isVolatile, unsigned Alignment);
603 SDOperand getValue(const Value *V);
605 void setValue(const Value *V, SDOperand NewN) {
606 SDOperand &N = NodeMap[V];
607 assert(N.Val == 0 && "Already set a value for this node!");
611 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
612 std::set<unsigned> &OutputRegs,
613 std::set<unsigned> &InputRegs);
615 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
616 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
618 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
619 void ExportFromCurrentBlock(Value *V);
620 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
621 MachineBasicBlock *LandingPad = NULL);
623 // Terminator instructions.
624 void visitRet(ReturnInst &I);
625 void visitBr(BranchInst &I);
626 void visitSwitch(SwitchInst &I);
627 void visitUnreachable(UnreachableInst &I) { /* noop */ }
629 // Helpers for visitSwitch
630 bool handleSmallSwitchRange(CaseRec& CR,
631 CaseRecVector& WorkList,
633 MachineBasicBlock* Default);
634 bool handleJTSwitchCase(CaseRec& CR,
635 CaseRecVector& WorkList,
637 MachineBasicBlock* Default);
638 bool handleBTSplitSwitchCase(CaseRec& CR,
639 CaseRecVector& WorkList,
641 MachineBasicBlock* Default);
642 bool handleBitTestsSwitchCase(CaseRec& CR,
643 CaseRecVector& WorkList,
645 MachineBasicBlock* Default);
646 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
647 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
648 void visitBitTestCase(MachineBasicBlock* NextMBB,
650 SelectionDAGISel::BitTestCase &B);
651 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
652 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
653 SelectionDAGISel::JumpTableHeader &JTH);
655 // These all get lowered before this pass.
656 void visitInvoke(InvokeInst &I);
657 void visitUnwind(UnwindInst &I);
659 void visitBinary(User &I, unsigned OpCode);
660 void visitShift(User &I, unsigned Opcode);
661 void visitAdd(User &I) {
662 if (I.getType()->isFPOrFPVector())
663 visitBinary(I, ISD::FADD);
665 visitBinary(I, ISD::ADD);
667 void visitSub(User &I);
668 void visitMul(User &I) {
669 if (I.getType()->isFPOrFPVector())
670 visitBinary(I, ISD::FMUL);
672 visitBinary(I, ISD::MUL);
674 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
675 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
676 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
677 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
678 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
679 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
680 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
681 void visitOr (User &I) { visitBinary(I, ISD::OR); }
682 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
683 void visitShl (User &I) { visitShift(I, ISD::SHL); }
684 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
685 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
686 void visitICmp(User &I);
687 void visitFCmp(User &I);
688 void visitVICmp(User &I);
689 void visitVFCmp(User &I);
690 // Visit the conversion instructions
691 void visitTrunc(User &I);
692 void visitZExt(User &I);
693 void visitSExt(User &I);
694 void visitFPTrunc(User &I);
695 void visitFPExt(User &I);
696 void visitFPToUI(User &I);
697 void visitFPToSI(User &I);
698 void visitUIToFP(User &I);
699 void visitSIToFP(User &I);
700 void visitPtrToInt(User &I);
701 void visitIntToPtr(User &I);
702 void visitBitCast(User &I);
704 void visitExtractElement(User &I);
705 void visitInsertElement(User &I);
706 void visitShuffleVector(User &I);
708 void visitGetElementPtr(User &I);
709 void visitSelect(User &I);
711 void visitMalloc(MallocInst &I);
712 void visitFree(FreeInst &I);
713 void visitAlloca(AllocaInst &I);
714 void visitLoad(LoadInst &I);
715 void visitStore(StoreInst &I);
716 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
717 void visitCall(CallInst &I);
718 void visitInlineAsm(CallSite CS);
719 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
720 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
722 void visitVAStart(CallInst &I);
723 void visitVAArg(VAArgInst &I);
724 void visitVAEnd(CallInst &I);
725 void visitVACopy(CallInst &I);
727 void visitGetResult(GetResultInst &I);
729 void visitUserOp1(Instruction &I) {
730 assert(0 && "UserOp1 should not exist at instruction selection time!");
733 void visitUserOp2(Instruction &I) {
734 assert(0 && "UserOp2 should not exist at instruction selection time!");
739 inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
742 } // end namespace llvm
745 /// getCopyFromParts - Create a value that contains the specified legal parts
746 /// combined into the value they represent. If the parts combine to a type
747 /// larger then ValueVT then AssertOp can be used to specify whether the extra
748 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
749 /// (ISD::AssertSext).
750 static SDOperand getCopyFromParts(SelectionDAG &DAG,
751 const SDOperand *Parts,
753 MVT::ValueType PartVT,
754 MVT::ValueType ValueVT,
755 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
756 assert(NumParts > 0 && "No parts to assemble!");
757 TargetLowering &TLI = DAG.getTargetLoweringInfo();
758 SDOperand Val = Parts[0];
761 // Assemble the value from multiple parts.
762 if (!MVT::isVector(ValueVT)) {
763 unsigned PartBits = MVT::getSizeInBits(PartVT);
764 unsigned ValueBits = MVT::getSizeInBits(ValueVT);
766 // Assemble the power of 2 part.
767 unsigned RoundParts = NumParts & (NumParts - 1) ?
768 1 << Log2_32(NumParts) : NumParts;
769 unsigned RoundBits = PartBits * RoundParts;
770 MVT::ValueType RoundVT = RoundBits == ValueBits ?
771 ValueVT : MVT::getIntegerType(RoundBits);
774 if (RoundParts > 2) {
775 MVT::ValueType HalfVT = MVT::getIntegerType(RoundBits/2);
776 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
777 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
783 if (TLI.isBigEndian())
785 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
787 if (RoundParts < NumParts) {
788 // Assemble the trailing non-power-of-2 part.
789 unsigned OddParts = NumParts - RoundParts;
790 MVT::ValueType OddVT = MVT::getIntegerType(OddParts * PartBits);
791 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
793 // Combine the round and odd parts.
795 if (TLI.isBigEndian())
797 MVT::ValueType TotalVT = MVT::getIntegerType(NumParts * PartBits);
798 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
799 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
800 DAG.getConstant(MVT::getSizeInBits(Lo.getValueType()),
801 TLI.getShiftAmountTy()));
802 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
803 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
806 // Handle a multi-element vector.
807 MVT::ValueType IntermediateVT, RegisterVT;
808 unsigned NumIntermediates;
810 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
813 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
814 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
815 assert(RegisterVT == Parts[0].getValueType() &&
816 "Part type doesn't match part!");
818 // Assemble the parts into intermediate operands.
819 SmallVector<SDOperand, 8> Ops(NumIntermediates);
820 if (NumIntermediates == NumParts) {
821 // If the register was not expanded, truncate or copy the value,
823 for (unsigned i = 0; i != NumParts; ++i)
824 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
825 PartVT, IntermediateVT);
826 } else if (NumParts > 0) {
827 // If the intermediate type was expanded, build the intermediate operands
829 assert(NumParts % NumIntermediates == 0 &&
830 "Must expand into a divisible number of parts!");
831 unsigned Factor = NumParts / NumIntermediates;
832 for (unsigned i = 0; i != NumIntermediates; ++i)
833 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
834 PartVT, IntermediateVT);
837 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
839 Val = DAG.getNode(MVT::isVector(IntermediateVT) ?
840 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
841 ValueVT, &Ops[0], NumIntermediates);
845 // There is now one part, held in Val. Correct it to match ValueVT.
846 PartVT = Val.getValueType();
848 if (PartVT == ValueVT)
851 if (MVT::isVector(PartVT)) {
852 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
853 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
856 if (MVT::isVector(ValueVT)) {
857 assert(MVT::getVectorElementType(ValueVT) == PartVT &&
858 MVT::getVectorNumElements(ValueVT) == 1 &&
859 "Only trivial scalar-to-vector conversions should get here!");
860 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
863 if (MVT::isInteger(PartVT) &&
864 MVT::isInteger(ValueVT)) {
865 if (MVT::getSizeInBits(ValueVT) < MVT::getSizeInBits(PartVT)) {
866 // For a truncate, see if we have any information to
867 // indicate whether the truncated bits will always be
868 // zero or sign-extension.
869 if (AssertOp != ISD::DELETED_NODE)
870 Val = DAG.getNode(AssertOp, PartVT, Val,
871 DAG.getValueType(ValueVT));
872 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
874 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
878 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) {
879 if (ValueVT < Val.getValueType())
880 // FP_ROUND's are always exact here.
881 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
882 DAG.getIntPtrConstant(1));
883 return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val);
886 if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
887 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
889 assert(0 && "Unknown mismatch!");
893 /// getCopyToParts - Create a series of nodes that contain the specified value
894 /// split into legal parts. If the parts contain more bits than Val, then, for
895 /// integers, ExtendKind can be used to specify how to generate the extra bits.
896 static void getCopyToParts(SelectionDAG &DAG,
900 MVT::ValueType PartVT,
901 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
902 TargetLowering &TLI = DAG.getTargetLoweringInfo();
903 MVT::ValueType PtrVT = TLI.getPointerTy();
904 MVT::ValueType ValueVT = Val.getValueType();
905 unsigned PartBits = MVT::getSizeInBits(PartVT);
906 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
911 if (!MVT::isVector(ValueVT)) {
912 if (PartVT == ValueVT) {
913 assert(NumParts == 1 && "No-op copy with multiple parts!");
918 if (NumParts * PartBits > MVT::getSizeInBits(ValueVT)) {
919 // If the parts cover more bits than the value has, promote the value.
920 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) {
921 assert(NumParts == 1 && "Do not know what to promote to!");
922 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
923 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
924 ValueVT = MVT::getIntegerType(NumParts * PartBits);
925 Val = DAG.getNode(ExtendKind, ValueVT, Val);
927 assert(0 && "Unknown mismatch!");
929 } else if (PartBits == MVT::getSizeInBits(ValueVT)) {
930 // Different types of the same size.
931 assert(NumParts == 1 && PartVT != ValueVT);
932 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
933 } else if (NumParts * PartBits < MVT::getSizeInBits(ValueVT)) {
934 // If the parts cover less bits than value has, truncate the value.
935 if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
936 ValueVT = MVT::getIntegerType(NumParts * PartBits);
937 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
939 assert(0 && "Unknown mismatch!");
943 // The value may have changed - recompute ValueVT.
944 ValueVT = Val.getValueType();
945 assert(NumParts * PartBits == MVT::getSizeInBits(ValueVT) &&
946 "Failed to tile the value with PartVT!");
949 assert(PartVT == ValueVT && "Type conversion failed!");
954 // Expand the value into multiple parts.
955 if (NumParts & (NumParts - 1)) {
956 // The number of parts is not a power of 2. Split off and copy the tail.
957 assert(MVT::isInteger(PartVT) && MVT::isInteger(ValueVT) &&
958 "Do not know what to expand to!");
959 unsigned RoundParts = 1 << Log2_32(NumParts);
960 unsigned RoundBits = RoundParts * PartBits;
961 unsigned OddParts = NumParts - RoundParts;
962 SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
963 DAG.getConstant(RoundBits,
964 TLI.getShiftAmountTy()));
965 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
966 if (TLI.isBigEndian())
967 // The odd parts were reversed by getCopyToParts - unreverse them.
968 std::reverse(Parts + RoundParts, Parts + NumParts);
969 NumParts = RoundParts;
970 ValueVT = MVT::getIntegerType(NumParts * PartBits);
971 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
974 // The number of parts is a power of 2. Repeatedly bisect the value using
976 Parts[0] = DAG.getNode(ISD::BIT_CONVERT,
977 MVT::getIntegerType(MVT::getSizeInBits(ValueVT)),
979 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
980 for (unsigned i = 0; i < NumParts; i += StepSize) {
981 unsigned ThisBits = StepSize * PartBits / 2;
982 MVT::ValueType ThisVT = MVT::getIntegerType (ThisBits);
983 SDOperand &Part0 = Parts[i];
984 SDOperand &Part1 = Parts[i+StepSize/2];
986 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
987 DAG.getConstant(1, PtrVT));
988 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0,
989 DAG.getConstant(0, PtrVT));
991 if (ThisBits == PartBits && ThisVT != PartVT) {
992 Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0);
993 Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1);
998 if (TLI.isBigEndian())
999 std::reverse(Parts, Parts + NumParts);
1005 if (NumParts == 1) {
1006 if (PartVT != ValueVT) {
1007 if (MVT::isVector(PartVT)) {
1008 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
1010 assert(MVT::getVectorElementType(ValueVT) == PartVT &&
1011 MVT::getVectorNumElements(ValueVT) == 1 &&
1012 "Only trivial vector-to-scalar conversions should get here!");
1013 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
1014 DAG.getConstant(0, PtrVT));
1022 // Handle a multi-element vector.
1023 MVT::ValueType IntermediateVT, RegisterVT;
1024 unsigned NumIntermediates;
1026 DAG.getTargetLoweringInfo()
1027 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
1029 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
1031 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
1032 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
1034 // Split the vector into intermediate operands.
1035 SmallVector<SDOperand, 8> Ops(NumIntermediates);
1036 for (unsigned i = 0; i != NumIntermediates; ++i)
1037 if (MVT::isVector(IntermediateVT))
1038 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
1039 IntermediateVT, Val,
1040 DAG.getConstant(i * (NumElements / NumIntermediates),
1043 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
1044 IntermediateVT, Val,
1045 DAG.getConstant(i, PtrVT));
1047 // Split the intermediate operands into legal parts.
1048 if (NumParts == NumIntermediates) {
1049 // If the register was not expanded, promote or copy the value,
1051 for (unsigned i = 0; i != NumParts; ++i)
1052 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
1053 } else if (NumParts > 0) {
1054 // If the intermediate type was expanded, split each the value into
1056 assert(NumParts % NumIntermediates == 0 &&
1057 "Must expand into a divisible number of parts!");
1058 unsigned Factor = NumParts / NumIntermediates;
1059 for (unsigned i = 0; i != NumIntermediates; ++i)
1060 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
1065 SDOperand SelectionDAGLowering::getValue(const Value *V) {
1066 SDOperand &N = NodeMap[V];
1067 if (N.Val) return N;
1069 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
1070 MVT::ValueType VT = TLI.getValueType(V->getType(), true);
1072 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
1073 return N = DAG.getConstant(CI->getValue(), VT);
1075 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
1076 return N = DAG.getGlobalAddress(GV, VT);
1078 if (isa<ConstantPointerNull>(C))
1079 return N = DAG.getConstant(0, TLI.getPointerTy());
1081 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1082 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
1084 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()))
1085 return N = DAG.getNode(ISD::UNDEF, VT);
1087 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1088 visit(CE->getOpcode(), *CE);
1089 SDOperand N1 = NodeMap[V];
1090 assert(N1.Val && "visit didn't populate the ValueMap!");
1094 const VectorType *VecTy = cast<VectorType>(V->getType());
1095 unsigned NumElements = VecTy->getNumElements();
1097 // Now that we know the number and type of the elements, get that number of
1098 // elements into the Ops array based on what kind of constant it is.
1099 SmallVector<SDOperand, 16> Ops;
1100 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1101 for (unsigned i = 0; i != NumElements; ++i)
1102 Ops.push_back(getValue(CP->getOperand(i)));
1104 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1105 "Unknown vector constant!");
1106 MVT::ValueType EltVT = TLI.getValueType(VecTy->getElementType());
1109 if (isa<UndefValue>(C))
1110 Op = DAG.getNode(ISD::UNDEF, EltVT);
1111 else if (MVT::isFloatingPoint(EltVT))
1112 Op = DAG.getConstantFP(0, EltVT);
1114 Op = DAG.getConstant(0, EltVT);
1115 Ops.assign(NumElements, Op);
1118 // Create a BUILD_VECTOR node.
1119 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1122 // If this is a static alloca, generate it as the frameindex instead of
1124 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1125 std::map<const AllocaInst*, int>::iterator SI =
1126 FuncInfo.StaticAllocaMap.find(AI);
1127 if (SI != FuncInfo.StaticAllocaMap.end())
1128 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1131 unsigned InReg = FuncInfo.ValueMap[V];
1132 assert(InReg && "Value not in map!");
1134 RegsForValue RFV(TLI, InReg, V->getType());
1135 SDOperand Chain = DAG.getEntryNode();
1136 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1140 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1141 if (I.getNumOperands() == 0) {
1142 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot()));
1146 SmallVector<SDOperand, 8> NewValues;
1147 NewValues.push_back(getControlRoot());
1148 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1149 SDOperand RetOp = getValue(I.getOperand(i));
1150 MVT::ValueType VT = RetOp.getValueType();
1152 // FIXME: C calling convention requires the return type to be promoted to
1153 // at least 32-bit. But this is not necessary for non-C calling conventions.
1154 if (MVT::isInteger(VT)) {
1155 MVT::ValueType MinVT = TLI.getRegisterType(MVT::i32);
1156 if (MVT::getSizeInBits(VT) < MVT::getSizeInBits(MinVT))
1160 unsigned NumParts = TLI.getNumRegisters(VT);
1161 MVT::ValueType PartVT = TLI.getRegisterType(VT);
1162 SmallVector<SDOperand, 4> Parts(NumParts);
1163 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1165 const Function *F = I.getParent()->getParent();
1166 if (F->paramHasAttr(0, ParamAttr::SExt))
1167 ExtendKind = ISD::SIGN_EXTEND;
1168 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1169 ExtendKind = ISD::ZERO_EXTEND;
1171 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, ExtendKind);
1173 for (unsigned i = 0; i < NumParts; ++i) {
1174 NewValues.push_back(Parts[i]);
1175 NewValues.push_back(DAG.getArgFlags(ISD::ArgFlagsTy()));
1178 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1179 &NewValues[0], NewValues.size()));
1182 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1183 /// the current basic block, add it to ValueMap now so that we'll get a
1185 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1186 // No need to export constants.
1187 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1189 // Already exported?
1190 if (FuncInfo.isExportedInst(V)) return;
1192 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1193 CopyValueToVirtualRegister(V, Reg);
1196 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1197 const BasicBlock *FromBB) {
1198 // The operands of the setcc have to be in this block. We don't know
1199 // how to export them from some other block.
1200 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1201 // Can export from current BB.
1202 if (VI->getParent() == FromBB)
1205 // Is already exported, noop.
1206 return FuncInfo.isExportedInst(V);
1209 // If this is an argument, we can export it if the BB is the entry block or
1210 // if it is already exported.
1211 if (isa<Argument>(V)) {
1212 if (FromBB == &FromBB->getParent()->getEntryBlock())
1215 // Otherwise, can only export this if it is already exported.
1216 return FuncInfo.isExportedInst(V);
1219 // Otherwise, constants can always be exported.
1223 static bool InBlock(const Value *V, const BasicBlock *BB) {
1224 if (const Instruction *I = dyn_cast<Instruction>(V))
1225 return I->getParent() == BB;
1229 /// FindMergedConditions - If Cond is an expression like
1230 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1231 MachineBasicBlock *TBB,
1232 MachineBasicBlock *FBB,
1233 MachineBasicBlock *CurBB,
1235 // If this node is not part of the or/and tree, emit it as a branch.
1236 Instruction *BOp = dyn_cast<Instruction>(Cond);
1238 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1239 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1240 BOp->getParent() != CurBB->getBasicBlock() ||
1241 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1242 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1243 const BasicBlock *BB = CurBB->getBasicBlock();
1245 // If the leaf of the tree is a comparison, merge the condition into
1247 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1248 // The operands of the cmp have to be in this block. We don't know
1249 // how to export them from some other block. If this is the first block
1250 // of the sequence, no exporting is needed.
1252 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1253 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1254 BOp = cast<Instruction>(Cond);
1255 ISD::CondCode Condition;
1256 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1257 switch (IC->getPredicate()) {
1258 default: assert(0 && "Unknown icmp predicate opcode!");
1259 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1260 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1261 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1262 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1263 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1264 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1265 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1266 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1267 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1268 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1270 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1271 ISD::CondCode FPC, FOC;
1272 switch (FC->getPredicate()) {
1273 default: assert(0 && "Unknown fcmp predicate opcode!");
1274 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1275 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1276 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1277 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1278 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1279 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1280 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1281 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1282 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1283 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1284 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1285 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1286 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1287 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1288 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1289 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1291 if (FiniteOnlyFPMath())
1296 Condition = ISD::SETEQ; // silence warning.
1297 assert(0 && "Unknown compare instruction");
1300 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1301 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1302 SwitchCases.push_back(CB);
1306 // Create a CaseBlock record representing this branch.
1307 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1308 NULL, TBB, FBB, CurBB);
1309 SwitchCases.push_back(CB);
1314 // Create TmpBB after CurBB.
1315 MachineFunction::iterator BBI = CurBB;
1316 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1317 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1319 if (Opc == Instruction::Or) {
1320 // Codegen X | Y as:
1328 // Emit the LHS condition.
1329 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1331 // Emit the RHS condition into TmpBB.
1332 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1334 assert(Opc == Instruction::And && "Unknown merge op!");
1335 // Codegen X & Y as:
1342 // This requires creation of TmpBB after CurBB.
1344 // Emit the LHS condition.
1345 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1347 // Emit the RHS condition into TmpBB.
1348 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1352 /// If the set of cases should be emitted as a series of branches, return true.
1353 /// If we should emit this as a bunch of and/or'd together conditions, return
1356 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1357 if (Cases.size() != 2) return true;
1359 // If this is two comparisons of the same values or'd or and'd together, they
1360 // will get folded into a single comparison, so don't emit two blocks.
1361 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1362 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1363 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1364 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1371 void SelectionDAGLowering::visitBr(BranchInst &I) {
1372 // Update machine-CFG edges.
1373 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1375 // Figure out which block is immediately after the current one.
1376 MachineBasicBlock *NextBlock = 0;
1377 MachineFunction::iterator BBI = CurMBB;
1378 if (++BBI != CurMBB->getParent()->end())
1381 if (I.isUnconditional()) {
1382 // If this is not a fall-through branch, emit the branch.
1383 if (Succ0MBB != NextBlock)
1384 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1385 DAG.getBasicBlock(Succ0MBB)));
1387 // Update machine-CFG edges.
1388 CurMBB->addSuccessor(Succ0MBB);
1392 // If this condition is one of the special cases we handle, do special stuff
1394 Value *CondVal = I.getCondition();
1395 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1397 // If this is a series of conditions that are or'd or and'd together, emit
1398 // this as a sequence of branches instead of setcc's with and/or operations.
1399 // For example, instead of something like:
1412 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1413 if (BOp->hasOneUse() &&
1414 (BOp->getOpcode() == Instruction::And ||
1415 BOp->getOpcode() == Instruction::Or)) {
1416 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1417 // If the compares in later blocks need to use values not currently
1418 // exported from this block, export them now. This block should always
1419 // be the first entry.
1420 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1422 // Allow some cases to be rejected.
1423 if (ShouldEmitAsBranches(SwitchCases)) {
1424 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1425 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1426 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1429 // Emit the branch for this block.
1430 visitSwitchCase(SwitchCases[0]);
1431 SwitchCases.erase(SwitchCases.begin());
1435 // Okay, we decided not to do this, remove any inserted MBB's and clear
1437 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1438 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1440 SwitchCases.clear();
1444 // Create a CaseBlock record representing this branch.
1445 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1446 NULL, Succ0MBB, Succ1MBB, CurMBB);
1447 // Use visitSwitchCase to actually insert the fast branch sequence for this
1449 visitSwitchCase(CB);
1452 /// visitSwitchCase - Emits the necessary code to represent a single node in
1453 /// the binary search tree resulting from lowering a switch instruction.
1454 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1456 SDOperand CondLHS = getValue(CB.CmpLHS);
1458 // Build the setcc now.
1459 if (CB.CmpMHS == NULL) {
1460 // Fold "(X == true)" to X and "(X == false)" to !X to
1461 // handle common cases produced by branch lowering.
1462 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1464 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1465 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1466 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1468 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1470 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1472 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1473 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1475 SDOperand CmpOp = getValue(CB.CmpMHS);
1476 MVT::ValueType VT = CmpOp.getValueType();
1478 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1479 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1481 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1482 Cond = DAG.getSetCC(MVT::i1, SUB,
1483 DAG.getConstant(High-Low, VT), ISD::SETULE);
1488 // Set NextBlock to be the MBB immediately after the current one, if any.
1489 // This is used to avoid emitting unnecessary branches to the next block.
1490 MachineBasicBlock *NextBlock = 0;
1491 MachineFunction::iterator BBI = CurMBB;
1492 if (++BBI != CurMBB->getParent()->end())
1495 // If the lhs block is the next block, invert the condition so that we can
1496 // fall through to the lhs instead of the rhs block.
1497 if (CB.TrueBB == NextBlock) {
1498 std::swap(CB.TrueBB, CB.FalseBB);
1499 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1500 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1502 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond,
1503 DAG.getBasicBlock(CB.TrueBB));
1504 if (CB.FalseBB == NextBlock)
1505 DAG.setRoot(BrCond);
1507 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1508 DAG.getBasicBlock(CB.FalseBB)));
1509 // Update successor info
1510 CurMBB->addSuccessor(CB.TrueBB);
1511 CurMBB->addSuccessor(CB.FalseBB);
1514 /// visitJumpTable - Emit JumpTable node in the current MBB
1515 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1516 // Emit the code for the jump table
1517 assert(JT.Reg != -1U && "Should lower JT Header first!");
1518 MVT::ValueType PTy = TLI.getPointerTy();
1519 SDOperand Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
1520 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1521 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1526 /// visitJumpTableHeader - This function emits necessary code to produce index
1527 /// in the JumpTable from switch case.
1528 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1529 SelectionDAGISel::JumpTableHeader &JTH) {
1530 // Subtract the lowest switch case value from the value being switched on
1531 // and conditional branch to default mbb if the result is greater than the
1532 // difference between smallest and largest cases.
1533 SDOperand SwitchOp = getValue(JTH.SValue);
1534 MVT::ValueType VT = SwitchOp.getValueType();
1535 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1536 DAG.getConstant(JTH.First, VT));
1538 // The SDNode we just created, which holds the value being switched on
1539 // minus the the smallest case value, needs to be copied to a virtual
1540 // register so it can be used as an index into the jump table in a
1541 // subsequent basic block. This value may be smaller or larger than the
1542 // target's pointer type, and therefore require extension or truncating.
1543 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
1544 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1546 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1548 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1549 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
1550 JT.Reg = JumpTableReg;
1552 // Emit the range check for the jump table, and branch to the default
1553 // block for the switch statement if the value being switched on exceeds
1554 // the largest case in the switch.
1555 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1556 DAG.getConstant(JTH.Last-JTH.First,VT),
1559 // Set NextBlock to be the MBB immediately after the current one, if any.
1560 // This is used to avoid emitting unnecessary branches to the next block.
1561 MachineBasicBlock *NextBlock = 0;
1562 MachineFunction::iterator BBI = CurMBB;
1563 if (++BBI != CurMBB->getParent()->end())
1566 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1567 DAG.getBasicBlock(JT.Default));
1569 if (JT.MBB == NextBlock)
1570 DAG.setRoot(BrCond);
1572 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1573 DAG.getBasicBlock(JT.MBB)));
1578 /// visitBitTestHeader - This function emits necessary code to produce value
1579 /// suitable for "bit tests"
1580 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1581 // Subtract the minimum value
1582 SDOperand SwitchOp = getValue(B.SValue);
1583 MVT::ValueType VT = SwitchOp.getValueType();
1584 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1585 DAG.getConstant(B.First, VT));
1588 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
1589 DAG.getConstant(B.Range, VT),
1593 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
1594 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1596 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1598 // Make desired shift
1599 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1600 DAG.getConstant(1, TLI.getPointerTy()),
1603 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1604 SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
1607 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1608 DAG.getBasicBlock(B.Default));
1610 // Set NextBlock to be the MBB immediately after the current one, if any.
1611 // This is used to avoid emitting unnecessary branches to the next block.
1612 MachineBasicBlock *NextBlock = 0;
1613 MachineFunction::iterator BBI = CurMBB;
1614 if (++BBI != CurMBB->getParent()->end())
1617 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1618 if (MBB == NextBlock)
1619 DAG.setRoot(BrRange);
1621 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1622 DAG.getBasicBlock(MBB)));
1624 CurMBB->addSuccessor(B.Default);
1625 CurMBB->addSuccessor(MBB);
1630 /// visitBitTestCase - this function produces one "bit test"
1631 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1633 SelectionDAGISel::BitTestCase &B) {
1634 // Emit bit tests and jumps
1635 SDOperand SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg, TLI.getPointerTy());
1637 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1639 DAG.getConstant(B.Mask,
1640 TLI.getPointerTy()));
1641 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
1642 DAG.getConstant(0, TLI.getPointerTy()),
1644 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(),
1645 AndCmp, DAG.getBasicBlock(B.TargetBB));
1647 // Set NextBlock to be the MBB immediately after the current one, if any.
1648 // This is used to avoid emitting unnecessary branches to the next block.
1649 MachineBasicBlock *NextBlock = 0;
1650 MachineFunction::iterator BBI = CurMBB;
1651 if (++BBI != CurMBB->getParent()->end())
1654 if (NextMBB == NextBlock)
1657 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1658 DAG.getBasicBlock(NextMBB)));
1660 CurMBB->addSuccessor(B.TargetBB);
1661 CurMBB->addSuccessor(NextMBB);
1666 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1667 // Retrieve successors.
1668 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1669 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1671 if (isa<InlineAsm>(I.getCalledValue()))
1674 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1676 // If the value of the invoke is used outside of its defining block, make it
1677 // available as a virtual register.
1678 if (!I.use_empty()) {
1679 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1680 if (VMI != FuncInfo.ValueMap.end())
1681 CopyValueToVirtualRegister(&I, VMI->second);
1684 // Drop into normal successor.
1685 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
1686 DAG.getBasicBlock(Return)));
1688 // Update successor info
1689 CurMBB->addSuccessor(Return);
1690 CurMBB->addSuccessor(LandingPad);
1693 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1696 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1697 /// small case ranges).
1698 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1699 CaseRecVector& WorkList,
1701 MachineBasicBlock* Default) {
1702 Case& BackCase = *(CR.Range.second-1);
1704 // Size is the number of Cases represented by this range.
1705 unsigned Size = CR.Range.second - CR.Range.first;
1709 // Get the MachineFunction which holds the current MBB. This is used when
1710 // inserting any additional MBBs necessary to represent the switch.
1711 MachineFunction *CurMF = CurMBB->getParent();
1713 // Figure out which block is immediately after the current one.
1714 MachineBasicBlock *NextBlock = 0;
1715 MachineFunction::iterator BBI = CR.CaseBB;
1717 if (++BBI != CurMBB->getParent()->end())
1720 // TODO: If any two of the cases has the same destination, and if one value
1721 // is the same as the other, but has one bit unset that the other has set,
1722 // use bit manipulation to do two compares at once. For example:
1723 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1725 // Rearrange the case blocks so that the last one falls through if possible.
1726 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1727 // The last case block won't fall through into 'NextBlock' if we emit the
1728 // branches in this order. See if rearranging a case value would help.
1729 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1730 if (I->BB == NextBlock) {
1731 std::swap(*I, BackCase);
1737 // Create a CaseBlock record representing a conditional branch to
1738 // the Case's target mbb if the value being switched on SV is equal
1740 MachineBasicBlock *CurBlock = CR.CaseBB;
1741 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1742 MachineBasicBlock *FallThrough;
1744 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1745 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1747 // If the last case doesn't match, go to the default block.
1748 FallThrough = Default;
1751 Value *RHS, *LHS, *MHS;
1753 if (I->High == I->Low) {
1754 // This is just small small case range :) containing exactly 1 case
1756 LHS = SV; RHS = I->High; MHS = NULL;
1759 LHS = I->Low; MHS = SV; RHS = I->High;
1761 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1762 I->BB, FallThrough, CurBlock);
1764 // If emitting the first comparison, just call visitSwitchCase to emit the
1765 // code into the current block. Otherwise, push the CaseBlock onto the
1766 // vector to be later processed by SDISel, and insert the node's MBB
1767 // before the next MBB.
1768 if (CurBlock == CurMBB)
1769 visitSwitchCase(CB);
1771 SwitchCases.push_back(CB);
1773 CurBlock = FallThrough;
1779 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1780 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1781 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1784 /// handleJTSwitchCase - Emit jumptable for current switch case range
1785 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1786 CaseRecVector& WorkList,
1788 MachineBasicBlock* Default) {
1789 Case& FrontCase = *CR.Range.first;
1790 Case& BackCase = *(CR.Range.second-1);
1792 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1793 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1796 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1800 if (!areJTsAllowed(TLI) || TSize <= 3)
1803 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1807 DOUT << "Lowering jump table\n"
1808 << "First entry: " << First << ". Last entry: " << Last << "\n"
1809 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1811 // Get the MachineFunction which holds the current MBB. This is used when
1812 // inserting any additional MBBs necessary to represent the switch.
1813 MachineFunction *CurMF = CurMBB->getParent();
1815 // Figure out which block is immediately after the current one.
1816 MachineBasicBlock *NextBlock = 0;
1817 MachineFunction::iterator BBI = CR.CaseBB;
1819 if (++BBI != CurMBB->getParent()->end())
1822 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1824 // Create a new basic block to hold the code for loading the address
1825 // of the jump table, and jumping to it. Update successor information;
1826 // we will either branch to the default case for the switch, or the jump
1828 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1829 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1830 CR.CaseBB->addSuccessor(Default);
1831 CR.CaseBB->addSuccessor(JumpTableBB);
1833 // Build a vector of destination BBs, corresponding to each target
1834 // of the jump table. If the value of the jump table slot corresponds to
1835 // a case statement, push the case's BB onto the vector, otherwise, push
1837 std::vector<MachineBasicBlock*> DestBBs;
1838 int64_t TEI = First;
1839 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1840 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1841 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1843 if ((Low <= TEI) && (TEI <= High)) {
1844 DestBBs.push_back(I->BB);
1848 DestBBs.push_back(Default);
1852 // Update successor info. Add one edge to each unique successor.
1853 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1854 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1855 E = DestBBs.end(); I != E; ++I) {
1856 if (!SuccsHandled[(*I)->getNumber()]) {
1857 SuccsHandled[(*I)->getNumber()] = true;
1858 JumpTableBB->addSuccessor(*I);
1862 // Create a jump table index for this jump table, or return an existing
1864 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1866 // Set the jump table information so that we can codegen it as a second
1867 // MachineBasicBlock
1868 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1869 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1870 (CR.CaseBB == CurMBB));
1871 if (CR.CaseBB == CurMBB)
1872 visitJumpTableHeader(JT, JTH);
1874 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1879 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1881 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1882 CaseRecVector& WorkList,
1884 MachineBasicBlock* Default) {
1885 // Get the MachineFunction which holds the current MBB. This is used when
1886 // inserting any additional MBBs necessary to represent the switch.
1887 MachineFunction *CurMF = CurMBB->getParent();
1889 // Figure out which block is immediately after the current one.
1890 MachineBasicBlock *NextBlock = 0;
1891 MachineFunction::iterator BBI = CR.CaseBB;
1893 if (++BBI != CurMBB->getParent()->end())
1896 Case& FrontCase = *CR.Range.first;
1897 Case& BackCase = *(CR.Range.second-1);
1898 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1900 // Size is the number of Cases represented by this range.
1901 unsigned Size = CR.Range.second - CR.Range.first;
1903 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1904 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1906 CaseItr Pivot = CR.Range.first + Size/2;
1908 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1909 // (heuristically) allow us to emit JumpTable's later.
1911 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1915 uint64_t LSize = FrontCase.size();
1916 uint64_t RSize = TSize-LSize;
1917 DOUT << "Selecting best pivot: \n"
1918 << "First: " << First << ", Last: " << Last <<"\n"
1919 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1920 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1922 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1923 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1924 assert((RBegin-LEnd>=1) && "Invalid case distance");
1925 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1926 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1927 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1928 // Should always split in some non-trivial place
1930 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1931 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1932 << "Metric: " << Metric << "\n";
1933 if (FMetric < Metric) {
1936 DOUT << "Current metric set to: " << FMetric << "\n";
1942 if (areJTsAllowed(TLI)) {
1943 // If our case is dense we *really* should handle it earlier!
1944 assert((FMetric > 0) && "Should handle dense range earlier!");
1946 Pivot = CR.Range.first + Size/2;
1949 CaseRange LHSR(CR.Range.first, Pivot);
1950 CaseRange RHSR(Pivot, CR.Range.second);
1951 Constant *C = Pivot->Low;
1952 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1954 // We know that we branch to the LHS if the Value being switched on is
1955 // less than the Pivot value, C. We use this to optimize our binary
1956 // tree a bit, by recognizing that if SV is greater than or equal to the
1957 // LHS's Case Value, and that Case Value is exactly one less than the
1958 // Pivot's Value, then we can branch directly to the LHS's Target,
1959 // rather than creating a leaf node for it.
1960 if ((LHSR.second - LHSR.first) == 1 &&
1961 LHSR.first->High == CR.GE &&
1962 cast<ConstantInt>(C)->getSExtValue() ==
1963 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1964 TrueBB = LHSR.first->BB;
1966 TrueBB = new MachineBasicBlock(LLVMBB);
1967 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1968 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1971 // Similar to the optimization above, if the Value being switched on is
1972 // known to be less than the Constant CR.LT, and the current Case Value
1973 // is CR.LT - 1, then we can branch directly to the target block for
1974 // the current Case Value, rather than emitting a RHS leaf node for it.
1975 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1976 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1977 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1978 FalseBB = RHSR.first->BB;
1980 FalseBB = new MachineBasicBlock(LLVMBB);
1981 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1982 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1985 // Create a CaseBlock record representing a conditional branch to
1986 // the LHS node if the value being switched on SV is less than C.
1987 // Otherwise, branch to LHS.
1988 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1989 TrueBB, FalseBB, CR.CaseBB);
1991 if (CR.CaseBB == CurMBB)
1992 visitSwitchCase(CB);
1994 SwitchCases.push_back(CB);
1999 /// handleBitTestsSwitchCase - if current case range has few destination and
2000 /// range span less, than machine word bitwidth, encode case range into series
2001 /// of masks and emit bit tests with these masks.
2002 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
2003 CaseRecVector& WorkList,
2005 MachineBasicBlock* Default){
2006 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
2008 Case& FrontCase = *CR.Range.first;
2009 Case& BackCase = *(CR.Range.second-1);
2011 // Get the MachineFunction which holds the current MBB. This is used when
2012 // inserting any additional MBBs necessary to represent the switch.
2013 MachineFunction *CurMF = CurMBB->getParent();
2015 unsigned numCmps = 0;
2016 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2018 // Single case counts one, case range - two.
2019 if (I->Low == I->High)
2025 // Count unique destinations
2026 SmallSet<MachineBasicBlock*, 4> Dests;
2027 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2028 Dests.insert(I->BB);
2029 if (Dests.size() > 3)
2030 // Don't bother the code below, if there are too much unique destinations
2033 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
2034 << "Total number of comparisons: " << numCmps << "\n";
2036 // Compute span of values.
2037 Constant* minValue = FrontCase.Low;
2038 Constant* maxValue = BackCase.High;
2039 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
2040 cast<ConstantInt>(minValue)->getSExtValue();
2041 DOUT << "Compare range: " << range << "\n"
2042 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
2043 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
2045 if (range>=IntPtrBits ||
2046 (!(Dests.size() == 1 && numCmps >= 3) &&
2047 !(Dests.size() == 2 && numCmps >= 5) &&
2048 !(Dests.size() >= 3 && numCmps >= 6)))
2051 DOUT << "Emitting bit tests\n";
2052 int64_t lowBound = 0;
2054 // Optimize the case where all the case values fit in a
2055 // word without having to subtract minValue. In this case,
2056 // we can optimize away the subtraction.
2057 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
2058 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
2059 range = cast<ConstantInt>(maxValue)->getSExtValue();
2061 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
2064 CaseBitsVector CasesBits;
2065 unsigned i, count = 0;
2067 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2068 MachineBasicBlock* Dest = I->BB;
2069 for (i = 0; i < count; ++i)
2070 if (Dest == CasesBits[i].BB)
2074 assert((count < 3) && "Too much destinations to test!");
2075 CasesBits.push_back(CaseBits(0, Dest, 0));
2079 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
2080 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
2082 for (uint64_t j = lo; j <= hi; j++) {
2083 CasesBits[i].Mask |= 1ULL << j;
2084 CasesBits[i].Bits++;
2088 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2090 SelectionDAGISel::BitTestInfo BTC;
2092 // Figure out which block is immediately after the current one.
2093 MachineFunction::iterator BBI = CR.CaseBB;
2096 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2099 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2100 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
2101 << ", BB: " << CasesBits[i].BB << "\n";
2103 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
2104 CurMF->getBasicBlockList().insert(BBI, CaseBB);
2105 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
2110 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
2111 -1U, (CR.CaseBB == CurMBB),
2112 CR.CaseBB, Default, BTC);
2114 if (CR.CaseBB == CurMBB)
2115 visitBitTestHeader(BTB);
2117 BitTestCases.push_back(BTB);
2123 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2124 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2125 const SwitchInst& SI) {
2126 unsigned numCmps = 0;
2128 // Start with "simple" cases
2129 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2130 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2131 Cases.push_back(Case(SI.getSuccessorValue(i),
2132 SI.getSuccessorValue(i),
2135 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2137 // Merge case into clusters
2138 if (Cases.size()>=2)
2139 // Must recompute end() each iteration because it may be
2140 // invalidated by erase if we hold on to it
2141 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2142 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2143 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2144 MachineBasicBlock* nextBB = J->BB;
2145 MachineBasicBlock* currentBB = I->BB;
2147 // If the two neighboring cases go to the same destination, merge them
2148 // into a single case.
2149 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2157 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2158 if (I->Low != I->High)
2159 // A range counts double, since it requires two compares.
2166 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2167 // Figure out which block is immediately after the current one.
2168 MachineBasicBlock *NextBlock = 0;
2169 MachineFunction::iterator BBI = CurMBB;
2171 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2173 // If there is only the default destination, branch to it if it is not the
2174 // next basic block. Otherwise, just fall through.
2175 if (SI.getNumOperands() == 2) {
2176 // Update machine-CFG edges.
2178 // If this is not a fall-through branch, emit the branch.
2179 if (Default != NextBlock)
2180 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(),
2181 DAG.getBasicBlock(Default)));
2183 CurMBB->addSuccessor(Default);
2187 // If there are any non-default case statements, create a vector of Cases
2188 // representing each one, and sort the vector so that we can efficiently
2189 // create a binary search tree from them.
2191 unsigned numCmps = Clusterify(Cases, SI);
2192 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2193 << ". Total compares: " << numCmps << "\n";
2195 // Get the Value to be switched on and default basic blocks, which will be
2196 // inserted into CaseBlock records, representing basic blocks in the binary
2198 Value *SV = SI.getOperand(0);
2200 // Push the initial CaseRec onto the worklist
2201 CaseRecVector WorkList;
2202 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2204 while (!WorkList.empty()) {
2205 // Grab a record representing a case range to process off the worklist
2206 CaseRec CR = WorkList.back();
2207 WorkList.pop_back();
2209 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2212 // If the range has few cases (two or less) emit a series of specific
2214 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2217 // If the switch has more than 5 blocks, and at least 40% dense, and the
2218 // target supports indirect branches, then emit a jump table rather than
2219 // lowering the switch to a binary tree of conditional branches.
2220 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2223 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2224 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2225 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2230 void SelectionDAGLowering::visitSub(User &I) {
2231 // -0.0 - X --> fneg
2232 const Type *Ty = I.getType();
2233 if (isa<VectorType>(Ty)) {
2234 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2235 const VectorType *DestTy = cast<VectorType>(I.getType());
2236 const Type *ElTy = DestTy->getElementType();
2237 if (ElTy->isFloatingPoint()) {
2238 unsigned VL = DestTy->getNumElements();
2239 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2240 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2242 SDOperand Op2 = getValue(I.getOperand(1));
2243 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2249 if (Ty->isFloatingPoint()) {
2250 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2251 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2252 SDOperand Op2 = getValue(I.getOperand(1));
2253 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2258 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2261 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2262 SDOperand Op1 = getValue(I.getOperand(0));
2263 SDOperand Op2 = getValue(I.getOperand(1));
2265 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2268 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2269 SDOperand Op1 = getValue(I.getOperand(0));
2270 SDOperand Op2 = getValue(I.getOperand(1));
2272 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2273 MVT::getSizeInBits(Op2.getValueType()))
2274 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2275 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2276 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2278 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2281 void SelectionDAGLowering::visitICmp(User &I) {
2282 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2283 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2284 predicate = IC->getPredicate();
2285 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2286 predicate = ICmpInst::Predicate(IC->getPredicate());
2287 SDOperand Op1 = getValue(I.getOperand(0));
2288 SDOperand Op2 = getValue(I.getOperand(1));
2289 ISD::CondCode Opcode;
2290 switch (predicate) {
2291 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2292 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2293 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2294 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2295 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2296 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2297 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2298 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2299 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2300 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2302 assert(!"Invalid ICmp predicate value");
2303 Opcode = ISD::SETEQ;
2306 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2309 void SelectionDAGLowering::visitFCmp(User &I) {
2310 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2311 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2312 predicate = FC->getPredicate();
2313 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2314 predicate = FCmpInst::Predicate(FC->getPredicate());
2315 SDOperand Op1 = getValue(I.getOperand(0));
2316 SDOperand Op2 = getValue(I.getOperand(1));
2317 ISD::CondCode Condition, FOC, FPC;
2318 switch (predicate) {
2319 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2320 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2321 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2322 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2323 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2324 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2325 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2326 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2327 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2328 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2329 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2330 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2331 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2332 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2333 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2334 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2336 assert(!"Invalid FCmp predicate value");
2337 FOC = FPC = ISD::SETFALSE;
2340 if (FiniteOnlyFPMath())
2344 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2347 void SelectionDAGLowering::visitVICmp(User &I) {
2348 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2349 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2350 predicate = IC->getPredicate();
2351 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2352 predicate = ICmpInst::Predicate(IC->getPredicate());
2353 SDOperand Op1 = getValue(I.getOperand(0));
2354 SDOperand Op2 = getValue(I.getOperand(1));
2355 ISD::CondCode Opcode;
2356 switch (predicate) {
2357 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2358 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2359 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2360 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2361 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2362 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2363 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2364 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2365 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2366 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2368 assert(!"Invalid ICmp predicate value");
2369 Opcode = ISD::SETEQ;
2372 setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
2375 void SelectionDAGLowering::visitVFCmp(User &I) {
2376 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2377 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2378 predicate = FC->getPredicate();
2379 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2380 predicate = FCmpInst::Predicate(FC->getPredicate());
2381 SDOperand Op1 = getValue(I.getOperand(0));
2382 SDOperand Op2 = getValue(I.getOperand(1));
2383 ISD::CondCode Condition, FOC, FPC;
2384 switch (predicate) {
2385 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2386 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2387 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2388 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2389 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2390 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2391 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2392 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
2393 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
2394 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2395 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2396 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2397 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2398 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2399 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2400 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2402 assert(!"Invalid VFCmp predicate value");
2403 FOC = FPC = ISD::SETFALSE;
2406 if (FiniteOnlyFPMath())
2411 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2413 setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
2416 void SelectionDAGLowering::visitSelect(User &I) {
2417 SDOperand Cond = getValue(I.getOperand(0));
2418 SDOperand TrueVal = getValue(I.getOperand(1));
2419 SDOperand FalseVal = getValue(I.getOperand(2));
2420 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2421 TrueVal, FalseVal));
2425 void SelectionDAGLowering::visitTrunc(User &I) {
2426 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2427 SDOperand N = getValue(I.getOperand(0));
2428 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2429 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2432 void SelectionDAGLowering::visitZExt(User &I) {
2433 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2434 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2435 SDOperand N = getValue(I.getOperand(0));
2436 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2437 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2440 void SelectionDAGLowering::visitSExt(User &I) {
2441 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2442 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2443 SDOperand N = getValue(I.getOperand(0));
2444 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2445 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2448 void SelectionDAGLowering::visitFPTrunc(User &I) {
2449 // FPTrunc is never a no-op cast, no need to check
2450 SDOperand N = getValue(I.getOperand(0));
2451 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2452 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2455 void SelectionDAGLowering::visitFPExt(User &I){
2456 // FPTrunc is never a no-op cast, no need to check
2457 SDOperand N = getValue(I.getOperand(0));
2458 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2459 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2462 void SelectionDAGLowering::visitFPToUI(User &I) {
2463 // FPToUI is never a no-op cast, no need to check
2464 SDOperand N = getValue(I.getOperand(0));
2465 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2466 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2469 void SelectionDAGLowering::visitFPToSI(User &I) {
2470 // FPToSI is never a no-op cast, no need to check
2471 SDOperand N = getValue(I.getOperand(0));
2472 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2473 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2476 void SelectionDAGLowering::visitUIToFP(User &I) {
2477 // UIToFP is never a no-op cast, no need to check
2478 SDOperand N = getValue(I.getOperand(0));
2479 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2480 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2483 void SelectionDAGLowering::visitSIToFP(User &I){
2484 // UIToFP is never a no-op cast, no need to check
2485 SDOperand N = getValue(I.getOperand(0));
2486 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2487 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2490 void SelectionDAGLowering::visitPtrToInt(User &I) {
2491 // What to do depends on the size of the integer and the size of the pointer.
2492 // We can either truncate, zero extend, or no-op, accordingly.
2493 SDOperand N = getValue(I.getOperand(0));
2494 MVT::ValueType SrcVT = N.getValueType();
2495 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2497 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2498 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2500 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2501 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2502 setValue(&I, Result);
2505 void SelectionDAGLowering::visitIntToPtr(User &I) {
2506 // What to do depends on the size of the integer and the size of the pointer.
2507 // We can either truncate, zero extend, or no-op, accordingly.
2508 SDOperand N = getValue(I.getOperand(0));
2509 MVT::ValueType SrcVT = N.getValueType();
2510 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2511 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2512 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2514 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2515 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2518 void SelectionDAGLowering::visitBitCast(User &I) {
2519 SDOperand N = getValue(I.getOperand(0));
2520 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2522 // BitCast assures us that source and destination are the same size so this
2523 // is either a BIT_CONVERT or a no-op.
2524 if (DestVT != N.getValueType())
2525 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2527 setValue(&I, N); // noop cast.
2530 void SelectionDAGLowering::visitInsertElement(User &I) {
2531 SDOperand InVec = getValue(I.getOperand(0));
2532 SDOperand InVal = getValue(I.getOperand(1));
2533 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2534 getValue(I.getOperand(2)));
2536 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2537 TLI.getValueType(I.getType()),
2538 InVec, InVal, InIdx));
2541 void SelectionDAGLowering::visitExtractElement(User &I) {
2542 SDOperand InVec = getValue(I.getOperand(0));
2543 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2544 getValue(I.getOperand(1)));
2545 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2546 TLI.getValueType(I.getType()), InVec, InIdx));
2549 void SelectionDAGLowering::visitShuffleVector(User &I) {
2550 SDOperand V1 = getValue(I.getOperand(0));
2551 SDOperand V2 = getValue(I.getOperand(1));
2552 SDOperand Mask = getValue(I.getOperand(2));
2554 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2555 TLI.getValueType(I.getType()),
2560 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2561 SDOperand N = getValue(I.getOperand(0));
2562 const Type *Ty = I.getOperand(0)->getType();
2564 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2567 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2568 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2571 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2572 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2573 DAG.getIntPtrConstant(Offset));
2575 Ty = StTy->getElementType(Field);
2577 Ty = cast<SequentialType>(Ty)->getElementType();
2579 // If this is a constant subscript, handle it quickly.
2580 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2581 if (CI->getZExtValue() == 0) continue;
2583 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2584 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2585 DAG.getIntPtrConstant(Offs));
2589 // N = N + Idx * ElementSize;
2590 uint64_t ElementSize = TD->getABITypeSize(Ty);
2591 SDOperand IdxN = getValue(Idx);
2593 // If the index is smaller or larger than intptr_t, truncate or extend
2595 if (IdxN.getValueType() < N.getValueType()) {
2596 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2597 } else if (IdxN.getValueType() > N.getValueType())
2598 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2600 // If this is a multiply by a power of two, turn it into a shl
2601 // immediately. This is a very common case.
2602 if (isPowerOf2_64(ElementSize)) {
2603 unsigned Amt = Log2_64(ElementSize);
2604 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2605 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2606 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2610 SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
2611 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2612 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2618 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2619 // If this is a fixed sized alloca in the entry block of the function,
2620 // allocate it statically on the stack.
2621 if (FuncInfo.StaticAllocaMap.count(&I))
2622 return; // getValue will auto-populate this.
2624 const Type *Ty = I.getAllocatedType();
2625 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2627 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2630 SDOperand AllocSize = getValue(I.getArraySize());
2631 MVT::ValueType IntPtr = TLI.getPointerTy();
2632 if (IntPtr < AllocSize.getValueType())
2633 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2634 else if (IntPtr > AllocSize.getValueType())
2635 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2637 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2638 DAG.getIntPtrConstant(TySize));
2640 // Handle alignment. If the requested alignment is less than or equal to
2641 // the stack alignment, ignore it. If the size is greater than or equal to
2642 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2643 unsigned StackAlign =
2644 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2645 if (Align <= StackAlign)
2648 // Round the size of the allocation up to the stack alignment size
2649 // by add SA-1 to the size.
2650 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2651 DAG.getIntPtrConstant(StackAlign-1));
2652 // Mask out the low bits for alignment purposes.
2653 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2654 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2656 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2657 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2659 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2661 DAG.setRoot(DSA.getValue(1));
2663 // Inform the Frame Information that we have just allocated a variable-sized
2665 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2668 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2669 SDOperand Ptr = getValue(I.getOperand(0));
2675 // Do not serialize non-volatile loads against each other.
2676 Root = DAG.getRoot();
2679 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2680 Root, I.isVolatile(), I.getAlignment()));
2683 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2684 const Value *SV, SDOperand Root,
2686 unsigned Alignment) {
2688 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2689 isVolatile, Alignment);
2692 DAG.setRoot(L.getValue(1));
2694 PendingLoads.push_back(L.getValue(1));
2700 void SelectionDAGLowering::visitStore(StoreInst &I) {
2701 Value *SrcV = I.getOperand(0);
2702 SDOperand Src = getValue(SrcV);
2703 SDOperand Ptr = getValue(I.getOperand(1));
2704 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2705 I.isVolatile(), I.getAlignment()));
2708 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2710 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2711 unsigned Intrinsic) {
2712 bool HasChain = !I.doesNotAccessMemory();
2713 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2715 // Build the operand list.
2716 SmallVector<SDOperand, 8> Ops;
2717 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2719 // We don't need to serialize loads against other loads.
2720 Ops.push_back(DAG.getRoot());
2722 Ops.push_back(getRoot());
2726 // Add the intrinsic ID as an integer operand.
2727 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2729 // Add all operands of the call to the operand list.
2730 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2731 SDOperand Op = getValue(I.getOperand(i));
2732 assert(TLI.isTypeLegal(Op.getValueType()) &&
2733 "Intrinsic uses a non-legal type?");
2737 std::vector<MVT::ValueType> VTs;
2738 if (I.getType() != Type::VoidTy) {
2739 MVT::ValueType VT = TLI.getValueType(I.getType());
2740 if (MVT::isVector(VT)) {
2741 const VectorType *DestTy = cast<VectorType>(I.getType());
2742 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2744 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2745 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2748 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2752 VTs.push_back(MVT::Other);
2754 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2759 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2760 &Ops[0], Ops.size());
2761 else if (I.getType() != Type::VoidTy)
2762 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2763 &Ops[0], Ops.size());
2765 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2766 &Ops[0], Ops.size());
2769 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2771 PendingLoads.push_back(Chain);
2775 if (I.getType() != Type::VoidTy) {
2776 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2777 MVT::ValueType VT = TLI.getValueType(PTy);
2778 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2780 setValue(&I, Result);
2784 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2785 static GlobalVariable *ExtractTypeInfo (Value *V) {
2786 V = V->stripPointerCasts();
2787 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2788 assert ((GV || isa<ConstantPointerNull>(V)) &&
2789 "TypeInfo must be a global variable or NULL");
2793 /// addCatchInfo - Extract the personality and type infos from an eh.selector
2794 /// call, and add them to the specified machine basic block.
2795 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2796 MachineBasicBlock *MBB) {
2797 // Inform the MachineModuleInfo of the personality for this landing pad.
2798 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2799 assert(CE->getOpcode() == Instruction::BitCast &&
2800 isa<Function>(CE->getOperand(0)) &&
2801 "Personality should be a function");
2802 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2804 // Gather all the type infos for this landing pad and pass them along to
2805 // MachineModuleInfo.
2806 std::vector<GlobalVariable *> TyInfo;
2807 unsigned N = I.getNumOperands();
2809 for (unsigned i = N - 1; i > 2; --i) {
2810 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2811 unsigned FilterLength = CI->getZExtValue();
2812 unsigned FirstCatch = i + FilterLength + !FilterLength;
2813 assert (FirstCatch <= N && "Invalid filter length");
2815 if (FirstCatch < N) {
2816 TyInfo.reserve(N - FirstCatch);
2817 for (unsigned j = FirstCatch; j < N; ++j)
2818 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2819 MMI->addCatchTypeInfo(MBB, TyInfo);
2823 if (!FilterLength) {
2825 MMI->addCleanup(MBB);
2828 TyInfo.reserve(FilterLength - 1);
2829 for (unsigned j = i + 1; j < FirstCatch; ++j)
2830 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2831 MMI->addFilterTypeInfo(MBB, TyInfo);
2840 TyInfo.reserve(N - 3);
2841 for (unsigned j = 3; j < N; ++j)
2842 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2843 MMI->addCatchTypeInfo(MBB, TyInfo);
2848 /// Inlined utility function to implement binary input atomic intrinsics for
2849 // visitIntrinsicCall: I is a call instruction
2850 // Op is the associated NodeType for I
2852 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
2853 SDOperand Root = getRoot();
2854 SDOperand O2 = getValue(I.getOperand(2));
2855 SDOperand L = DAG.getAtomic(Op, Root,
2856 getValue(I.getOperand(1)),
2857 O2, O2.getValueType());
2859 DAG.setRoot(L.getValue(1));
2863 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2864 /// we want to emit this as a call to a named external function, return the name
2865 /// otherwise lower it and return null.
2867 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2868 switch (Intrinsic) {
2870 // By default, turn this into a target intrinsic node.
2871 visitTargetIntrinsic(I, Intrinsic);
2873 case Intrinsic::vastart: visitVAStart(I); return 0;
2874 case Intrinsic::vaend: visitVAEnd(I); return 0;
2875 case Intrinsic::vacopy: visitVACopy(I); return 0;
2876 case Intrinsic::returnaddress:
2877 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2878 getValue(I.getOperand(1))));
2880 case Intrinsic::frameaddress:
2881 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2882 getValue(I.getOperand(1))));
2884 case Intrinsic::setjmp:
2885 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2887 case Intrinsic::longjmp:
2888 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2890 case Intrinsic::memcpy_i32:
2891 case Intrinsic::memcpy_i64: {
2892 SDOperand Op1 = getValue(I.getOperand(1));
2893 SDOperand Op2 = getValue(I.getOperand(2));
2894 SDOperand Op3 = getValue(I.getOperand(3));
2895 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
2896 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
2897 I.getOperand(1), 0, I.getOperand(2), 0));
2900 case Intrinsic::memset_i32:
2901 case Intrinsic::memset_i64: {
2902 SDOperand Op1 = getValue(I.getOperand(1));
2903 SDOperand Op2 = getValue(I.getOperand(2));
2904 SDOperand Op3 = getValue(I.getOperand(3));
2905 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
2906 DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
2907 I.getOperand(1), 0));
2910 case Intrinsic::memmove_i32:
2911 case Intrinsic::memmove_i64: {
2912 SDOperand Op1 = getValue(I.getOperand(1));
2913 SDOperand Op2 = getValue(I.getOperand(2));
2914 SDOperand Op3 = getValue(I.getOperand(3));
2915 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
2917 // If the source and destination are known to not be aliases, we can
2918 // lower memmove as memcpy.
2919 uint64_t Size = -1ULL;
2920 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
2921 Size = C->getValue();
2922 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
2923 AliasAnalysis::NoAlias) {
2924 DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
2925 I.getOperand(1), 0, I.getOperand(2), 0));
2929 DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
2930 I.getOperand(1), 0, I.getOperand(2), 0));
2933 case Intrinsic::dbg_stoppoint: {
2934 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2935 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2936 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2940 Ops[1] = getValue(SPI.getLineValue());
2941 Ops[2] = getValue(SPI.getColumnValue());
2943 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2944 assert(DD && "Not a debug information descriptor");
2945 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2947 Ops[3] = DAG.getString(CompileUnit->getFileName());
2948 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2950 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2955 case Intrinsic::dbg_region_start: {
2956 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2957 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2958 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2959 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2960 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2961 DAG.getConstant(LabelID, MVT::i32),
2962 DAG.getConstant(0, MVT::i32)));
2967 case Intrinsic::dbg_region_end: {
2968 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2969 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2970 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2971 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2972 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2973 DAG.getConstant(LabelID, MVT::i32),
2974 DAG.getConstant(0, MVT::i32)));
2979 case Intrinsic::dbg_func_start: {
2980 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2982 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2983 Value *SP = FSI.getSubprogram();
2984 if (SP && MMI->Verify(SP)) {
2985 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
2986 // what (most?) gdb expects.
2987 DebugInfoDesc *DD = MMI->getDescFor(SP);
2988 assert(DD && "Not a debug information descriptor");
2989 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
2990 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
2991 unsigned SrcFile = MMI->RecordSource(CompileUnit->getDirectory(),
2992 CompileUnit->getFileName());
2993 // Record the source line but does create a label. It will be emitted
2994 // at asm emission time.
2995 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
3000 case Intrinsic::dbg_declare: {
3001 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3002 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3003 Value *Variable = DI.getVariable();
3004 if (MMI && Variable && MMI->Verify(Variable))
3005 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
3006 getValue(DI.getAddress()), getValue(Variable)));
3010 case Intrinsic::eh_exception: {
3011 if (!CurMBB->isLandingPad()) {
3012 // FIXME: Mark exception register as live in. Hack for PR1508.
3013 unsigned Reg = TLI.getExceptionAddressRegister();
3014 if (Reg) CurMBB->addLiveIn(Reg);
3016 // Insert the EXCEPTIONADDR instruction.
3017 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3019 Ops[0] = DAG.getRoot();
3020 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
3022 DAG.setRoot(Op.getValue(1));
3026 case Intrinsic::eh_selector_i32:
3027 case Intrinsic::eh_selector_i64: {
3028 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3029 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3030 MVT::i32 : MVT::i64);
3033 if (CurMBB->isLandingPad())
3034 addCatchInfo(I, MMI, CurMBB);
3037 FuncInfo.CatchInfoLost.insert(&I);
3039 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3040 unsigned Reg = TLI.getExceptionSelectorRegister();
3041 if (Reg) CurMBB->addLiveIn(Reg);
3044 // Insert the EHSELECTION instruction.
3045 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
3047 Ops[0] = getValue(I.getOperand(1));
3049 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
3051 DAG.setRoot(Op.getValue(1));
3053 setValue(&I, DAG.getConstant(0, VT));
3059 case Intrinsic::eh_typeid_for_i32:
3060 case Intrinsic::eh_typeid_for_i64: {
3061 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3062 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
3063 MVT::i32 : MVT::i64);
3066 // Find the type id for the given typeinfo.
3067 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3069 unsigned TypeID = MMI->getTypeIDFor(GV);
3070 setValue(&I, DAG.getConstant(TypeID, VT));
3072 // Return something different to eh_selector.
3073 setValue(&I, DAG.getConstant(1, VT));
3079 case Intrinsic::eh_return: {
3080 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3083 MMI->setCallsEHReturn(true);
3084 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
3087 getValue(I.getOperand(1)),
3088 getValue(I.getOperand(2))));
3090 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3096 case Intrinsic::eh_unwind_init: {
3097 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3098 MMI->setCallsUnwindInit(true);
3104 case Intrinsic::eh_dwarf_cfa: {
3105 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
3107 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
3108 CfaArg = DAG.getNode(ISD::TRUNCATE,
3109 TLI.getPointerTy(), getValue(I.getOperand(1)));
3111 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
3112 TLI.getPointerTy(), getValue(I.getOperand(1)));
3114 SDOperand Offset = DAG.getNode(ISD::ADD,
3116 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
3117 TLI.getPointerTy()),
3119 setValue(&I, DAG.getNode(ISD::ADD,
3121 DAG.getNode(ISD::FRAMEADDR,
3124 TLI.getPointerTy())),
3129 case Intrinsic::sqrt:
3130 setValue(&I, DAG.getNode(ISD::FSQRT,
3131 getValue(I.getOperand(1)).getValueType(),
3132 getValue(I.getOperand(1))));
3134 case Intrinsic::powi:
3135 setValue(&I, DAG.getNode(ISD::FPOWI,
3136 getValue(I.getOperand(1)).getValueType(),
3137 getValue(I.getOperand(1)),
3138 getValue(I.getOperand(2))));
3140 case Intrinsic::sin:
3141 setValue(&I, DAG.getNode(ISD::FSIN,
3142 getValue(I.getOperand(1)).getValueType(),
3143 getValue(I.getOperand(1))));
3145 case Intrinsic::cos:
3146 setValue(&I, DAG.getNode(ISD::FCOS,
3147 getValue(I.getOperand(1)).getValueType(),
3148 getValue(I.getOperand(1))));
3150 case Intrinsic::pow:
3151 setValue(&I, DAG.getNode(ISD::FPOW,
3152 getValue(I.getOperand(1)).getValueType(),
3153 getValue(I.getOperand(1)),
3154 getValue(I.getOperand(2))));
3156 case Intrinsic::pcmarker: {
3157 SDOperand Tmp = getValue(I.getOperand(1));
3158 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
3161 case Intrinsic::readcyclecounter: {
3162 SDOperand Op = getRoot();
3163 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
3164 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
3167 DAG.setRoot(Tmp.getValue(1));
3170 case Intrinsic::part_select: {
3171 // Currently not implemented: just abort
3172 assert(0 && "part_select intrinsic not implemented");
3175 case Intrinsic::part_set: {
3176 // Currently not implemented: just abort
3177 assert(0 && "part_set intrinsic not implemented");
3180 case Intrinsic::bswap:
3181 setValue(&I, DAG.getNode(ISD::BSWAP,
3182 getValue(I.getOperand(1)).getValueType(),
3183 getValue(I.getOperand(1))));
3185 case Intrinsic::cttz: {
3186 SDOperand Arg = getValue(I.getOperand(1));
3187 MVT::ValueType Ty = Arg.getValueType();
3188 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
3189 setValue(&I, result);
3192 case Intrinsic::ctlz: {
3193 SDOperand Arg = getValue(I.getOperand(1));
3194 MVT::ValueType Ty = Arg.getValueType();
3195 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
3196 setValue(&I, result);
3199 case Intrinsic::ctpop: {
3200 SDOperand Arg = getValue(I.getOperand(1));
3201 MVT::ValueType Ty = Arg.getValueType();
3202 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
3203 setValue(&I, result);
3206 case Intrinsic::stacksave: {
3207 SDOperand Op = getRoot();
3208 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
3209 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
3211 DAG.setRoot(Tmp.getValue(1));
3214 case Intrinsic::stackrestore: {
3215 SDOperand Tmp = getValue(I.getOperand(1));
3216 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
3219 case Intrinsic::var_annotation:
3220 // Discard annotate attributes
3223 case Intrinsic::init_trampoline: {
3224 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
3228 Ops[1] = getValue(I.getOperand(1));
3229 Ops[2] = getValue(I.getOperand(2));
3230 Ops[3] = getValue(I.getOperand(3));
3231 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3232 Ops[5] = DAG.getSrcValue(F);
3234 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
3235 DAG.getNodeValueTypes(TLI.getPointerTy(),
3240 DAG.setRoot(Tmp.getValue(1));
3244 case Intrinsic::gcroot:
3246 Value *Alloca = I.getOperand(1);
3247 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3249 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3250 GCI->addStackRoot(FI->getIndex(), TypeMap);
3254 case Intrinsic::gcread:
3255 case Intrinsic::gcwrite:
3256 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3259 case Intrinsic::flt_rounds: {
3260 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3264 case Intrinsic::trap: {
3265 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3268 case Intrinsic::prefetch: {
3271 Ops[1] = getValue(I.getOperand(1));
3272 Ops[2] = getValue(I.getOperand(2));
3273 Ops[3] = getValue(I.getOperand(3));
3274 DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4));
3278 case Intrinsic::memory_barrier: {
3281 for (int x = 1; x < 6; ++x)
3282 Ops[x] = getValue(I.getOperand(x));
3284 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3287 case Intrinsic::atomic_lcs: {
3288 SDOperand Root = getRoot();
3289 SDOperand O3 = getValue(I.getOperand(3));
3290 SDOperand L = DAG.getAtomic(ISD::ATOMIC_LCS, Root,
3291 getValue(I.getOperand(1)),
3292 getValue(I.getOperand(2)),
3293 O3, O3.getValueType());
3295 DAG.setRoot(L.getValue(1));
3298 case Intrinsic::atomic_las:
3299 return implVisitBinaryAtomic(I, ISD::ATOMIC_LAS);
3300 case Intrinsic::atomic_lss:
3301 return implVisitBinaryAtomic(I, ISD::ATOMIC_LSS);
3302 case Intrinsic::atomic_load_and:
3303 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
3304 case Intrinsic::atomic_load_or:
3305 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
3306 case Intrinsic::atomic_load_xor:
3307 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
3308 case Intrinsic::atomic_load_min:
3309 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
3310 case Intrinsic::atomic_load_max:
3311 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
3312 case Intrinsic::atomic_load_umin:
3313 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
3314 case Intrinsic::atomic_load_umax:
3315 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
3316 case Intrinsic::atomic_swap:
3317 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
3322 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
3324 MachineBasicBlock *LandingPad) {
3325 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3326 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3327 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3328 unsigned BeginLabel = 0, EndLabel = 0;
3330 TargetLowering::ArgListTy Args;
3331 TargetLowering::ArgListEntry Entry;
3332 Args.reserve(CS.arg_size());
3333 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3335 SDOperand ArgNode = getValue(*i);
3336 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3338 unsigned attrInd = i - CS.arg_begin() + 1;
3339 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3340 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3341 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3342 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3343 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3344 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3345 Entry.Alignment = CS.getParamAlignment(attrInd);
3346 Args.push_back(Entry);
3349 if (LandingPad && MMI) {
3350 // Insert a label before the invoke call to mark the try range. This can be
3351 // used to detect deletion of the invoke via the MachineModuleInfo.
3352 BeginLabel = MMI->NextLabelID();
3353 // Both PendingLoads and PendingExports must be flushed here;
3354 // this call might not return.
3356 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getControlRoot(),
3357 DAG.getConstant(BeginLabel, MVT::i32),
3358 DAG.getConstant(1, MVT::i32)));
3361 std::pair<SDOperand,SDOperand> Result =
3362 TLI.LowerCallTo(getRoot(), CS.getType(),
3363 CS.paramHasAttr(0, ParamAttr::SExt),
3364 CS.paramHasAttr(0, ParamAttr::ZExt),
3365 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3367 if (CS.getType() != Type::VoidTy)
3368 setValue(CS.getInstruction(), Result.first);
3369 DAG.setRoot(Result.second);
3371 if (LandingPad && MMI) {
3372 // Insert a label at the end of the invoke call to mark the try range. This
3373 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3374 EndLabel = MMI->NextLabelID();
3375 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3376 DAG.getConstant(EndLabel, MVT::i32),
3377 DAG.getConstant(1, MVT::i32)));
3379 // Inform MachineModuleInfo of range.
3380 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3385 void SelectionDAGLowering::visitCall(CallInst &I) {
3386 const char *RenameFn = 0;
3387 if (Function *F = I.getCalledFunction()) {
3388 if (F->isDeclaration()) {
3389 if (unsigned IID = F->getIntrinsicID()) {
3390 RenameFn = visitIntrinsicCall(I, IID);
3396 // Check for well-known libc/libm calls. If the function is internal, it
3397 // can't be a library call.
3398 unsigned NameLen = F->getNameLen();
3399 if (!F->hasInternalLinkage() && NameLen) {
3400 const char *NameStr = F->getNameStart();
3401 if (NameStr[0] == 'c' &&
3402 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3403 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3404 if (I.getNumOperands() == 3 && // Basic sanity checks.
3405 I.getOperand(1)->getType()->isFloatingPoint() &&
3406 I.getType() == I.getOperand(1)->getType() &&
3407 I.getType() == I.getOperand(2)->getType()) {
3408 SDOperand LHS = getValue(I.getOperand(1));
3409 SDOperand RHS = getValue(I.getOperand(2));
3410 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3414 } else if (NameStr[0] == 'f' &&
3415 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3416 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3417 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3418 if (I.getNumOperands() == 2 && // Basic sanity checks.
3419 I.getOperand(1)->getType()->isFloatingPoint() &&
3420 I.getType() == I.getOperand(1)->getType()) {
3421 SDOperand Tmp = getValue(I.getOperand(1));
3422 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3425 } else if (NameStr[0] == 's' &&
3426 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3427 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3428 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3429 if (I.getNumOperands() == 2 && // Basic sanity checks.
3430 I.getOperand(1)->getType()->isFloatingPoint() &&
3431 I.getType() == I.getOperand(1)->getType()) {
3432 SDOperand Tmp = getValue(I.getOperand(1));
3433 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3436 } else if (NameStr[0] == 'c' &&
3437 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3438 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3439 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3440 if (I.getNumOperands() == 2 && // Basic sanity checks.
3441 I.getOperand(1)->getType()->isFloatingPoint() &&
3442 I.getType() == I.getOperand(1)->getType()) {
3443 SDOperand Tmp = getValue(I.getOperand(1));
3444 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3449 } else if (isa<InlineAsm>(I.getOperand(0))) {
3456 Callee = getValue(I.getOperand(0));
3458 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3460 LowerCallTo(&I, Callee, I.isTailCall());
3464 void SelectionDAGLowering::visitGetResult(GetResultInst &I) {
3465 if (isa<UndefValue>(I.getOperand(0))) {
3466 SDOperand Undef = DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType()));
3467 setValue(&I, Undef);
3471 // To add support for individual return values with aggregate types,
3472 // we'd need a way to take a getresult index and determine which
3473 // values of the Call SDNode are associated with it.
3474 assert(TLI.getValueType(I.getType(), true) != MVT::Other &&
3475 "Individual return values must not be aggregates!");
3477 SDOperand Call = getValue(I.getOperand(0));
3478 setValue(&I, SDOperand(Call.Val, I.getIndex()));
3482 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3483 /// this value and returns the result as a ValueVT value. This uses
3484 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3485 /// If the Flag pointer is NULL, no flag is used.
3486 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3488 SDOperand *Flag) const {
3489 // Assemble the legal parts into the final values.
3490 SmallVector<SDOperand, 4> Values(ValueVTs.size());
3491 SmallVector<SDOperand, 8> Parts;
3492 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3493 // Copy the legal parts from the registers.
3494 MVT::ValueType ValueVT = ValueVTs[Value];
3495 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
3496 MVT::ValueType RegisterVT = RegVTs[Value];
3498 Parts.resize(NumRegs);
3499 for (unsigned i = 0; i != NumRegs; ++i) {
3502 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
3504 P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
3505 *Flag = P.getValue(2);
3507 Chain = P.getValue(1);
3511 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
3516 if (ValueVTs.size() == 1)
3519 return DAG.getNode(ISD::MERGE_VALUES,
3520 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
3521 &Values[0], ValueVTs.size());
3524 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3525 /// specified value into the registers specified by this object. This uses
3526 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3527 /// If the Flag pointer is NULL, no flag is used.
3528 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3529 SDOperand &Chain, SDOperand *Flag) const {
3530 // Get the list of the values's legal parts.
3531 unsigned NumRegs = Regs.size();
3532 SmallVector<SDOperand, 8> Parts(NumRegs);
3533 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
3534 MVT::ValueType ValueVT = ValueVTs[Value];
3535 unsigned NumParts = TLI->getNumRegisters(ValueVT);
3536 MVT::ValueType RegisterVT = RegVTs[Value];
3538 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
3539 &Parts[Part], NumParts, RegisterVT);
3543 // Copy the parts into the registers.
3544 SmallVector<SDOperand, 8> Chains(NumRegs);
3545 for (unsigned i = 0; i != NumRegs; ++i) {
3548 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3550 Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
3551 *Flag = Part.getValue(1);
3553 Chains[i] = Part.getValue(0);
3556 if (NumRegs == 1 || Flag)
3557 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
3558 // flagged to it. That is the CopyToReg nodes and the user are considered
3559 // a single scheduling unit. If we create a TokenFactor and return it as
3560 // chain, then the TokenFactor is both a predecessor (operand) of the
3561 // user as well as a successor (the TF operands are flagged to the user).
3562 // c1, f1 = CopyToReg
3563 // c2, f2 = CopyToReg
3564 // c3 = TokenFactor c1, c2
3567 Chain = Chains[NumRegs-1];
3569 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
3572 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3573 /// operand list. This adds the code marker and includes the number of
3574 /// values added into it.
3575 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3576 std::vector<SDOperand> &Ops) const {
3577 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3578 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3579 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
3580 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
3581 MVT::ValueType RegisterVT = RegVTs[Value];
3582 for (unsigned i = 0; i != NumRegs; ++i)
3583 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
3587 /// isAllocatableRegister - If the specified register is safe to allocate,
3588 /// i.e. it isn't a stack pointer or some other special register, return the
3589 /// register class for the register. Otherwise, return null.
3590 static const TargetRegisterClass *
3591 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3592 const TargetLowering &TLI,
3593 const TargetRegisterInfo *TRI) {
3594 MVT::ValueType FoundVT = MVT::Other;
3595 const TargetRegisterClass *FoundRC = 0;
3596 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3597 E = TRI->regclass_end(); RCI != E; ++RCI) {
3598 MVT::ValueType ThisVT = MVT::Other;
3600 const TargetRegisterClass *RC = *RCI;
3601 // If none of the the value types for this register class are valid, we
3602 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3603 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3605 if (TLI.isTypeLegal(*I)) {
3606 // If we have already found this register in a different register class,
3607 // choose the one with the largest VT specified. For example, on
3608 // PowerPC, we favor f64 register classes over f32.
3609 if (FoundVT == MVT::Other ||
3610 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3617 if (ThisVT == MVT::Other) continue;
3619 // NOTE: This isn't ideal. In particular, this might allocate the
3620 // frame pointer in functions that need it (due to them not being taken
3621 // out of allocation, because a variable sized allocation hasn't been seen
3622 // yet). This is a slight code pessimization, but should still work.
3623 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3624 E = RC->allocation_order_end(MF); I != E; ++I)
3626 // We found a matching register class. Keep looking at others in case
3627 // we find one with larger registers that this physreg is also in.
3638 /// AsmOperandInfo - This contains information for each constraint that we are
3640 struct SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
3641 /// CallOperand - If this is the result output operand or a clobber
3642 /// this is null, otherwise it is the incoming operand to the CallInst.
3643 /// This gets modified as the asm is processed.
3644 SDOperand CallOperand;
3646 /// AssignedRegs - If this is a register or register class operand, this
3647 /// contains the set of register corresponding to the operand.
3648 RegsForValue AssignedRegs;
3650 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3651 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
3654 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3655 /// busy in OutputRegs/InputRegs.
3656 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3657 std::set<unsigned> &OutputRegs,
3658 std::set<unsigned> &InputRegs,
3659 const TargetRegisterInfo &TRI) const {
3661 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3662 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3665 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3666 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3671 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3673 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3674 const TargetRegisterInfo &TRI) {
3675 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3677 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3678 for (; *Aliases; ++Aliases)
3679 Regs.insert(*Aliases);
3682 } // end anon namespace.
3685 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3686 /// specified operand. We prefer to assign virtual registers, to allow the
3687 /// register allocator handle the assignment process. However, if the asm uses
3688 /// features that we can't model on machineinstrs, we have SDISel do the
3689 /// allocation. This produces generally horrible, but correct, code.
3691 /// OpInfo describes the operand.
3692 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3693 /// or any explicitly clobbered registers.
3694 /// Input and OutputRegs are the set of already allocated physical registers.
3696 void SelectionDAGLowering::
3697 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
3698 std::set<unsigned> &OutputRegs,
3699 std::set<unsigned> &InputRegs) {
3700 // Compute whether this value requires an input register, an output register,
3702 bool isOutReg = false;
3703 bool isInReg = false;
3704 switch (OpInfo.Type) {
3705 case InlineAsm::isOutput:
3708 // If this is an early-clobber output, or if there is an input
3709 // constraint that matches this, we need to reserve the input register
3710 // so no other inputs allocate to it.
3711 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3713 case InlineAsm::isInput:
3717 case InlineAsm::isClobber:
3724 MachineFunction &MF = DAG.getMachineFunction();
3725 SmallVector<unsigned, 4> Regs;
3727 // If this is a constraint for a single physreg, or a constraint for a
3728 // register class, find it.
3729 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3730 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3731 OpInfo.ConstraintVT);
3733 unsigned NumRegs = 1;
3734 if (OpInfo.ConstraintVT != MVT::Other)
3735 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3736 MVT::ValueType RegVT;
3737 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3740 // If this is a constraint for a specific physical register, like {r17},
3742 if (PhysReg.first) {
3743 if (OpInfo.ConstraintVT == MVT::Other)
3744 ValueVT = *PhysReg.second->vt_begin();
3746 // Get the actual register value type. This is important, because the user
3747 // may have asked for (e.g.) the AX register in i32 type. We need to
3748 // remember that AX is actually i16 to get the right extension.
3749 RegVT = *PhysReg.second->vt_begin();
3751 // This is a explicit reference to a physical register.
3752 Regs.push_back(PhysReg.first);
3754 // If this is an expanded reference, add the rest of the regs to Regs.
3756 TargetRegisterClass::iterator I = PhysReg.second->begin();
3757 TargetRegisterClass::iterator E = PhysReg.second->end();
3758 for (; *I != PhysReg.first; ++I)
3759 assert(I != E && "Didn't find reg!");
3761 // Already added the first reg.
3763 for (; NumRegs; --NumRegs, ++I) {
3764 assert(I != E && "Ran out of registers to allocate!");
3768 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
3769 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3770 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
3774 // Otherwise, if this was a reference to an LLVM register class, create vregs
3775 // for this reference.
3776 std::vector<unsigned> RegClassRegs;
3777 const TargetRegisterClass *RC = PhysReg.second;
3779 // If this is an early clobber or tied register, our regalloc doesn't know
3780 // how to maintain the constraint. If it isn't, go ahead and create vreg
3781 // and let the regalloc do the right thing.
3782 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3783 // If there is some other early clobber and this is an input register,
3784 // then we are forced to pre-allocate the input reg so it doesn't
3785 // conflict with the earlyclobber.
3786 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
3787 RegVT = *PhysReg.second->vt_begin();
3789 if (OpInfo.ConstraintVT == MVT::Other)
3792 // Create the appropriate number of virtual registers.
3793 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3794 for (; NumRegs; --NumRegs)
3795 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
3797 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
3801 // Otherwise, we can't allocate it. Let the code below figure out how to
3802 // maintain these constraints.
3803 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3806 // This is a reference to a register class that doesn't directly correspond
3807 // to an LLVM register class. Allocate NumRegs consecutive, available,
3808 // registers from the class.
3809 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3810 OpInfo.ConstraintVT);
3813 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3814 unsigned NumAllocated = 0;
3815 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3816 unsigned Reg = RegClassRegs[i];
3817 // See if this register is available.
3818 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3819 (isInReg && InputRegs.count(Reg))) { // Already used.
3820 // Make sure we find consecutive registers.
3825 // Check to see if this register is allocatable (i.e. don't give out the
3828 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
3829 if (!RC) { // Couldn't allocate this register.
3830 // Reset NumAllocated to make sure we return consecutive registers.
3836 // Okay, this register is good, we can use it.
3839 // If we allocated enough consecutive registers, succeed.
3840 if (NumAllocated == NumRegs) {
3841 unsigned RegStart = (i-NumAllocated)+1;
3842 unsigned RegEnd = i+1;
3843 // Mark all of the allocated registers used.
3844 for (unsigned i = RegStart; i != RegEnd; ++i)
3845 Regs.push_back(RegClassRegs[i]);
3847 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
3848 OpInfo.ConstraintVT);
3849 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
3854 // Otherwise, we couldn't allocate enough registers for this.
3858 /// visitInlineAsm - Handle a call to an InlineAsm object.
3860 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
3861 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
3863 /// ConstraintOperands - Information about all of the constraints.
3864 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
3866 SDOperand Chain = getRoot();
3869 std::set<unsigned> OutputRegs, InputRegs;
3871 // Do a prepass over the constraints, canonicalizing them, and building up the
3872 // ConstraintOperands list.
3873 std::vector<InlineAsm::ConstraintInfo>
3874 ConstraintInfos = IA->ParseConstraints();
3876 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3877 // constraint. If so, we can't let the register allocator allocate any input
3878 // registers, because it will not know to avoid the earlyclobbered output reg.
3879 bool SawEarlyClobber = false;
3881 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3882 unsigned ResNo = 0; // ResNo - The result number of the next output.
3883 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3884 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
3885 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
3887 MVT::ValueType OpVT = MVT::Other;
3889 // Compute the value type for each operand.
3890 switch (OpInfo.Type) {
3891 case InlineAsm::isOutput:
3892 // Indirect outputs just consume an argument.
3893 if (OpInfo.isIndirect) {
3894 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3897 // The return value of the call is this value. As such, there is no
3898 // corresponding argument.
3899 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3900 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
3901 OpVT = TLI.getValueType(STy->getElementType(ResNo));
3903 assert(ResNo == 0 && "Asm only has one result!");
3904 OpVT = TLI.getValueType(CS.getType());
3908 case InlineAsm::isInput:
3909 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3911 case InlineAsm::isClobber:
3916 // If this is an input or an indirect output, process the call argument.
3917 // BasicBlocks are labels, currently appearing only in asm's.
3918 if (OpInfo.CallOperandVal) {
3919 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal))
3920 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
3922 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3923 const Type *OpTy = OpInfo.CallOperandVal->getType();
3924 // If this is an indirect operand, the operand is a pointer to the
3926 if (OpInfo.isIndirect)
3927 OpTy = cast<PointerType>(OpTy)->getElementType();
3929 // If OpTy is not a first-class value, it may be a struct/union that we
3930 // can tile with integers.
3931 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3932 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3940 OpTy = IntegerType::get(BitSize);
3945 OpVT = TLI.getValueType(OpTy, true);
3949 OpInfo.ConstraintVT = OpVT;
3951 // Compute the constraint code and ConstraintType to use.
3952 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
3954 // Keep track of whether we see an earlyclobber.
3955 SawEarlyClobber |= OpInfo.isEarlyClobber;
3957 // If we see a clobber of a register, it is an early clobber.
3958 if (!SawEarlyClobber &&
3959 OpInfo.Type == InlineAsm::isClobber &&
3960 OpInfo.ConstraintType == TargetLowering::C_Register) {
3961 // Note that we want to ignore things that we don't trick here, like
3962 // dirflag, fpsr, flags, etc.
3963 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3964 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3965 OpInfo.ConstraintVT);
3966 if (PhysReg.first || PhysReg.second) {
3967 // This is a register we know of.
3968 SawEarlyClobber = true;
3972 // If this is a memory input, and if the operand is not indirect, do what we
3973 // need to to provide an address for the memory input.
3974 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3975 !OpInfo.isIndirect) {
3976 assert(OpInfo.Type == InlineAsm::isInput &&
3977 "Can only indirectify direct input operands!");
3979 // Memory operands really want the address of the value. If we don't have
3980 // an indirect input, put it in the constpool if we can, otherwise spill
3981 // it to a stack slot.
3983 // If the operand is a float, integer, or vector constant, spill to a
3984 // constant pool entry to get its address.
3985 Value *OpVal = OpInfo.CallOperandVal;
3986 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3987 isa<ConstantVector>(OpVal)) {
3988 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3989 TLI.getPointerTy());
3991 // Otherwise, create a stack slot and emit a store to it before the
3993 const Type *Ty = OpVal->getType();
3994 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3995 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3996 MachineFunction &MF = DAG.getMachineFunction();
3997 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3998 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3999 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
4000 OpInfo.CallOperand = StackSlot;
4003 // There is no longer a Value* corresponding to this operand.
4004 OpInfo.CallOperandVal = 0;
4005 // It is now an indirect operand.
4006 OpInfo.isIndirect = true;
4009 // If this constraint is for a specific register, allocate it before
4011 if (OpInfo.ConstraintType == TargetLowering::C_Register)
4012 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4014 ConstraintInfos.clear();
4017 // Second pass - Loop over all of the operands, assigning virtual or physregs
4018 // to registerclass operands.
4019 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4020 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4022 // C_Register operands have already been allocated, Other/Memory don't need
4024 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
4025 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
4028 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
4029 std::vector<SDOperand> AsmNodeOperands;
4030 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
4031 AsmNodeOperands.push_back(
4032 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
4035 // Loop over all of the inputs, copying the operand values into the
4036 // appropriate registers and processing the output regs.
4037 RegsForValue RetValRegs;
4039 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
4040 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
4042 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
4043 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
4045 switch (OpInfo.Type) {
4046 case InlineAsm::isOutput: {
4047 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
4048 OpInfo.ConstraintType != TargetLowering::C_Register) {
4049 // Memory output, or 'other' output (e.g. 'X' constraint).
4050 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
4052 // Add information to the INLINEASM node to know about this output.
4053 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4054 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4055 TLI.getPointerTy()));
4056 AsmNodeOperands.push_back(OpInfo.CallOperand);
4060 // Otherwise, this is a register or register class output.
4062 // Copy the output from the appropriate register. Find a register that
4064 if (OpInfo.AssignedRegs.Regs.empty()) {
4065 cerr << "Couldn't allocate output reg for contraint '"
4066 << OpInfo.ConstraintCode << "'!\n";
4070 // If this is an indirect operand, store through the pointer after the
4072 if (OpInfo.isIndirect) {
4073 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
4074 OpInfo.CallOperandVal));
4076 // This is the result value of the call.
4077 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
4078 // Concatenate this output onto the outputs list.
4079 RetValRegs.append(OpInfo.AssignedRegs);
4082 // Add information to the INLINEASM node to know that this register is
4084 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
4088 case InlineAsm::isInput: {
4089 SDOperand InOperandVal = OpInfo.CallOperand;
4091 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
4092 // If this is required to match an output register we have already set,
4093 // just use its register.
4094 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
4096 // Scan until we find the definition we already emitted of this operand.
4097 // When we find it, create a RegsForValue operand.
4098 unsigned CurOp = 2; // The first operand.
4099 for (; OperandNo; --OperandNo) {
4100 // Advance to the next operand.
4102 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4103 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
4104 (NumOps & 7) == 4 /*MEM*/) &&
4105 "Skipped past definitions?");
4106 CurOp += (NumOps>>3)+1;
4110 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
4111 if ((NumOps & 7) == 2 /*REGDEF*/) {
4112 // Add NumOps>>3 registers to MatchedRegs.
4113 RegsForValue MatchedRegs;
4114 MatchedRegs.TLI = &TLI;
4115 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
4116 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
4117 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
4119 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
4120 MatchedRegs.Regs.push_back(Reg);
4123 // Use the produced MatchedRegs object to
4124 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4125 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
4128 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
4129 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
4130 // Add information to the INLINEASM node to know about this input.
4131 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4132 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4133 TLI.getPointerTy()));
4134 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
4139 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
4140 assert(!OpInfo.isIndirect &&
4141 "Don't know how to handle indirect other inputs yet!");
4143 std::vector<SDOperand> Ops;
4144 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
4147 cerr << "Invalid operand for inline asm constraint '"
4148 << OpInfo.ConstraintCode << "'!\n";
4152 // Add information to the INLINEASM node to know about this input.
4153 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
4154 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4155 TLI.getPointerTy()));
4156 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
4158 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
4159 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
4160 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
4161 "Memory operands expect pointer values");
4163 // Add information to the INLINEASM node to know about this input.
4164 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
4165 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
4166 TLI.getPointerTy()));
4167 AsmNodeOperands.push_back(InOperandVal);
4171 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
4172 OpInfo.ConstraintType == TargetLowering::C_Register) &&
4173 "Unknown constraint type!");
4174 assert(!OpInfo.isIndirect &&
4175 "Don't know how to handle indirect register inputs yet!");
4177 // Copy the input into the appropriate registers.
4178 assert(!OpInfo.AssignedRegs.Regs.empty() &&
4179 "Couldn't allocate input reg!");
4181 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
4183 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
4187 case InlineAsm::isClobber: {
4188 // Add the clobbered value to the operand list, so that the register
4189 // allocator is aware that the physreg got clobbered.
4190 if (!OpInfo.AssignedRegs.Regs.empty())
4191 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
4198 // Finish up input operands.
4199 AsmNodeOperands[0] = Chain;
4200 if (Flag.Val) AsmNodeOperands.push_back(Flag);
4202 Chain = DAG.getNode(ISD::INLINEASM,
4203 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
4204 &AsmNodeOperands[0], AsmNodeOperands.size());
4205 Flag = Chain.getValue(1);
4207 // If this asm returns a register value, copy the result from that register
4208 // and set it as the value of the call.
4209 if (!RetValRegs.Regs.empty()) {
4210 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
4212 // If any of the results of the inline asm is a vector, it may have the
4213 // wrong width/num elts. This can happen for register classes that can
4214 // contain multiple different value types. The preg or vreg allocated may
4215 // not have the same VT as was expected. Convert it to the right type with
4217 if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
4218 for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
4219 if (MVT::isVector(Val.Val->getValueType(i)))
4220 Val = DAG.getNode(ISD::BIT_CONVERT,
4221 TLI.getValueType(ResSTy->getElementType(i)), Val);
4224 if (MVT::isVector(Val.getValueType()))
4225 Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
4229 setValue(CS.getInstruction(), Val);
4232 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
4234 // Process indirect outputs, first output all of the flagged copies out of
4236 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
4237 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
4238 Value *Ptr = IndirectStoresToEmit[i].second;
4239 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
4240 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
4243 // Emit the non-flagged stores from the physregs.
4244 SmallVector<SDOperand, 8> OutChains;
4245 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
4246 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
4247 getValue(StoresToEmit[i].second),
4248 StoresToEmit[i].second, 0));
4249 if (!OutChains.empty())
4250 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4251 &OutChains[0], OutChains.size());
4256 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4257 SDOperand Src = getValue(I.getOperand(0));
4259 MVT::ValueType IntPtr = TLI.getPointerTy();
4261 if (IntPtr < Src.getValueType())
4262 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4263 else if (IntPtr > Src.getValueType())
4264 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4266 // Scale the source by the type size.
4267 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4268 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4269 Src, DAG.getIntPtrConstant(ElementSize));
4271 TargetLowering::ArgListTy Args;
4272 TargetLowering::ArgListEntry Entry;
4274 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4275 Args.push_back(Entry);
4277 std::pair<SDOperand,SDOperand> Result =
4278 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4279 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4280 setValue(&I, Result.first); // Pointers always fit in registers
4281 DAG.setRoot(Result.second);
4284 void SelectionDAGLowering::visitFree(FreeInst &I) {
4285 TargetLowering::ArgListTy Args;
4286 TargetLowering::ArgListEntry Entry;
4287 Entry.Node = getValue(I.getOperand(0));
4288 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4289 Args.push_back(Entry);
4290 MVT::ValueType IntPtr = TLI.getPointerTy();
4291 std::pair<SDOperand,SDOperand> Result =
4292 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4293 CallingConv::C, true,
4294 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4295 DAG.setRoot(Result.second);
4298 // EmitInstrWithCustomInserter - This method should be implemented by targets
4299 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4300 // instructions are special in various ways, which require special support to
4301 // insert. The specified MachineInstr is created but not inserted into any
4302 // basic blocks, and the scheduler passes ownership of it to this method.
4303 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4304 MachineBasicBlock *MBB) {
4305 cerr << "If a target marks an instruction with "
4306 << "'usesCustomDAGSchedInserter', it must implement "
4307 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4312 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4313 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4314 getValue(I.getOperand(1)),
4315 DAG.getSrcValue(I.getOperand(1))));
4318 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4319 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4320 getValue(I.getOperand(0)),
4321 DAG.getSrcValue(I.getOperand(0)));
4323 DAG.setRoot(V.getValue(1));
4326 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4327 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4328 getValue(I.getOperand(1)),
4329 DAG.getSrcValue(I.getOperand(1))));
4332 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4333 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4334 getValue(I.getOperand(1)),
4335 getValue(I.getOperand(2)),
4336 DAG.getSrcValue(I.getOperand(1)),
4337 DAG.getSrcValue(I.getOperand(2))));
4340 /// TargetLowering::LowerArguments - This is the default LowerArguments
4341 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4342 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4343 /// integrated into SDISel.
4344 std::vector<SDOperand>
4345 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
4346 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4347 std::vector<SDOperand> Ops;
4348 Ops.push_back(DAG.getRoot());
4349 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4350 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4352 // Add one result value for each formal argument.
4353 std::vector<MVT::ValueType> RetVals;
4355 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4357 MVT::ValueType VT = getValueType(I->getType());
4358 ISD::ArgFlagsTy Flags;
4359 unsigned OriginalAlignment =
4360 getTargetData()->getABITypeAlignment(I->getType());
4362 if (F.paramHasAttr(j, ParamAttr::ZExt))
4364 if (F.paramHasAttr(j, ParamAttr::SExt))
4366 if (F.paramHasAttr(j, ParamAttr::InReg))
4368 if (F.paramHasAttr(j, ParamAttr::StructRet))
4370 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4372 const PointerType *Ty = cast<PointerType>(I->getType());
4373 const Type *ElementTy = Ty->getElementType();
4374 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4375 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4376 // For ByVal, alignment should be passed from FE. BE will guess if
4377 // this info is not there but there are cases it cannot get right.
4378 if (F.getParamAlignment(j))
4379 FrameAlign = F.getParamAlignment(j);
4380 Flags.setByValAlign(FrameAlign);
4381 Flags.setByValSize(FrameSize);
4383 if (F.paramHasAttr(j, ParamAttr::Nest))
4385 Flags.setOrigAlign(OriginalAlignment);
4387 MVT::ValueType RegisterVT = getRegisterType(VT);
4388 unsigned NumRegs = getNumRegisters(VT);
4389 for (unsigned i = 0; i != NumRegs; ++i) {
4390 RetVals.push_back(RegisterVT);
4391 ISD::ArgFlagsTy MyFlags = Flags;
4392 if (NumRegs > 1 && i == 0)
4394 // if it isn't first piece, alignment must be 1
4396 MyFlags.setOrigAlign(1);
4397 Ops.push_back(DAG.getArgFlags(MyFlags));
4401 RetVals.push_back(MVT::Other);
4404 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4405 DAG.getVTList(&RetVals[0], RetVals.size()),
4406 &Ops[0], Ops.size()).Val;
4408 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4409 // allows exposing the loads that may be part of the argument access to the
4410 // first DAGCombiner pass.
4411 SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG);
4413 // The number of results should match up, except that the lowered one may have
4414 // an extra flag result.
4415 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4416 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4417 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4418 && "Lowering produced unexpected number of results!");
4419 Result = TmpRes.Val;
4421 unsigned NumArgRegs = Result->getNumValues() - 1;
4422 DAG.setRoot(SDOperand(Result, NumArgRegs));
4424 // Set up the return result vector.
4428 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4430 MVT::ValueType VT = getValueType(I->getType());
4431 MVT::ValueType PartVT = getRegisterType(VT);
4433 unsigned NumParts = getNumRegisters(VT);
4434 SmallVector<SDOperand, 4> Parts(NumParts);
4435 for (unsigned j = 0; j != NumParts; ++j)
4436 Parts[j] = SDOperand(Result, i++);
4438 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4439 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4440 AssertOp = ISD::AssertSext;
4441 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4442 AssertOp = ISD::AssertZext;
4444 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4447 assert(i == NumArgRegs && "Argument register count mismatch!");
4452 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4453 /// implementation, which just inserts an ISD::CALL node, which is later custom
4454 /// lowered by the target to something concrete. FIXME: When all targets are
4455 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4456 std::pair<SDOperand, SDOperand>
4457 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4458 bool RetSExt, bool RetZExt, bool isVarArg,
4459 unsigned CallingConv, bool isTailCall,
4461 ArgListTy &Args, SelectionDAG &DAG) {
4462 SmallVector<SDOperand, 32> Ops;
4463 Ops.push_back(Chain); // Op#0 - Chain
4464 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4465 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4466 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4467 Ops.push_back(Callee);
4469 // Handle all of the outgoing arguments.
4470 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4471 MVT::ValueType VT = getValueType(Args[i].Ty);
4472 SDOperand Op = Args[i].Node;
4473 ISD::ArgFlagsTy Flags;
4474 unsigned OriginalAlignment =
4475 getTargetData()->getABITypeAlignment(Args[i].Ty);
4481 if (Args[i].isInReg)
4485 if (Args[i].isByVal) {
4487 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4488 const Type *ElementTy = Ty->getElementType();
4489 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
4490 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4491 // For ByVal, alignment should come from FE. BE will guess if this
4492 // info is not there but there are cases it cannot get right.
4493 if (Args[i].Alignment)
4494 FrameAlign = Args[i].Alignment;
4495 Flags.setByValAlign(FrameAlign);
4496 Flags.setByValSize(FrameSize);
4500 Flags.setOrigAlign(OriginalAlignment);
4502 MVT::ValueType PartVT = getRegisterType(VT);
4503 unsigned NumParts = getNumRegisters(VT);
4504 SmallVector<SDOperand, 4> Parts(NumParts);
4505 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4508 ExtendKind = ISD::SIGN_EXTEND;
4509 else if (Args[i].isZExt)
4510 ExtendKind = ISD::ZERO_EXTEND;
4512 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4514 for (unsigned i = 0; i != NumParts; ++i) {
4515 // if it isn't first piece, alignment must be 1
4516 ISD::ArgFlagsTy MyFlags = Flags;
4517 if (NumParts > 1 && i == 0)
4520 MyFlags.setOrigAlign(1);
4522 Ops.push_back(Parts[i]);
4523 Ops.push_back(DAG.getArgFlags(MyFlags));
4527 // Figure out the result value types. We start by making a list of
4528 // the potentially illegal return value types.
4529 SmallVector<MVT::ValueType, 4> LoweredRetTys;
4530 SmallVector<MVT::ValueType, 4> RetTys;
4531 ComputeValueVTs(*this, RetTy, RetTys);
4533 // Then we translate that to a list of legal types.
4534 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4535 MVT::ValueType VT = RetTys[I];
4536 MVT::ValueType RegisterVT = getRegisterType(VT);
4537 unsigned NumRegs = getNumRegisters(VT);
4538 for (unsigned i = 0; i != NumRegs; ++i)
4539 LoweredRetTys.push_back(RegisterVT);
4542 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
4544 // Create the CALL node.
4545 SDOperand Res = DAG.getNode(ISD::CALL,
4546 DAG.getVTList(&LoweredRetTys[0],
4547 LoweredRetTys.size()),
4548 &Ops[0], Ops.size());
4549 Chain = Res.getValue(LoweredRetTys.size() - 1);
4551 // Gather up the call result into a single value.
4552 if (RetTy != Type::VoidTy) {
4553 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4556 AssertOp = ISD::AssertSext;
4558 AssertOp = ISD::AssertZext;
4560 SmallVector<SDOperand, 4> ReturnValues;
4562 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4563 MVT::ValueType VT = RetTys[I];
4564 MVT::ValueType RegisterVT = getRegisterType(VT);
4565 unsigned NumRegs = getNumRegisters(VT);
4566 unsigned RegNoEnd = NumRegs + RegNo;
4567 SmallVector<SDOperand, 4> Results;
4568 for (; RegNo != RegNoEnd; ++RegNo)
4569 Results.push_back(Res.getValue(RegNo));
4570 SDOperand ReturnValue =
4571 getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4573 ReturnValues.push_back(ReturnValue);
4575 Res = ReturnValues.size() == 1 ? ReturnValues.front() :
4576 DAG.getNode(ISD::MERGE_VALUES,
4577 DAG.getVTList(&RetTys[0], RetTys.size()),
4578 &ReturnValues[0], ReturnValues.size());
4581 return std::make_pair(Res, Chain);
4584 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4585 assert(0 && "LowerOperation not implemented for this target!");
4590 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4591 SelectionDAG &DAG) {
4592 assert(0 && "CustomPromoteOperation not implemented for this target!");
4597 //===----------------------------------------------------------------------===//
4598 // SelectionDAGISel code
4599 //===----------------------------------------------------------------------===//
4601 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4602 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4605 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4606 AU.addRequired<AliasAnalysis>();
4607 AU.addRequired<CollectorModuleMetadata>();
4608 AU.setPreservesAll();
4611 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4612 // Get alias analysis for load/store combining.
4613 AA = &getAnalysis<AliasAnalysis>();
4615 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4616 if (MF.getFunction()->hasCollector())
4617 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4620 RegInfo = &MF.getRegInfo();
4621 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4623 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4625 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4626 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4627 // Mark landing pad.
4628 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4630 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4631 SelectBasicBlock(I, MF, FuncInfo);
4633 // Add function live-ins to entry block live-in set.
4634 BasicBlock *EntryBB = &Fn.getEntryBlock();
4635 BB = FuncInfo.MBBMap[EntryBB];
4636 if (!RegInfo->livein_empty())
4637 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4638 E = RegInfo->livein_end(); I != E; ++I)
4639 BB->addLiveIn(I->first);
4642 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4643 "Not all catch info was assigned to a landing pad!");
4649 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
4650 SDOperand Op = getValue(V);
4651 assert((Op.getOpcode() != ISD::CopyFromReg ||
4652 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4653 "Copy from a reg to the same reg!");
4654 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
4656 RegsForValue RFV(TLI, Reg, V->getType());
4657 SDOperand Chain = DAG.getEntryNode();
4658 RFV.getCopyToRegs(Op, DAG, Chain, 0);
4659 PendingExports.push_back(Chain);
4662 void SelectionDAGISel::
4663 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) {
4664 // If this is the entry block, emit arguments.
4665 Function &F = *LLVMBB->getParent();
4666 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4667 SDOperand OldRoot = SDL.DAG.getRoot();
4668 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4671 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4673 if (!AI->use_empty()) {
4674 SDL.setValue(AI, Args[a]);
4676 // If this argument is live outside of the entry block, insert a copy from
4677 // whereever we got it to the vreg that other BB's will reference it as.
4678 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4679 if (VMI != FuncInfo.ValueMap.end()) {
4680 SDL.CopyValueToVirtualRegister(AI, VMI->second);
4684 // Finally, if the target has anything special to do, allow it to do so.
4685 // FIXME: this should insert code into the DAG!
4686 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4689 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4690 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4691 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4692 if (isSelector(I)) {
4693 // Apply the catch info to DestBB.
4694 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4696 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4697 FLI.CatchInfoFound.insert(I);
4702 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
4703 /// whether object offset >= 0.
4705 IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDOperand Op) {
4706 if (!isa<FrameIndexSDNode>(Op)) return false;
4708 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
4709 int FrameIdx = FrameIdxNode->getIndex();
4710 return MFI->isFixedObjectIndex(FrameIdx) &&
4711 MFI->getObjectOffset(FrameIdx) >= 0;
4714 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
4715 /// possibly be overwritten when lowering the outgoing arguments in a tail
4716 /// call. Currently the implementation of this call is very conservative and
4717 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
4718 /// virtual registers would be overwritten by direct lowering.
4719 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDOperand Op,
4720 MachineFrameInfo * MFI) {
4721 RegisterSDNode * OpReg = NULL;
4722 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
4723 (Op.getOpcode()== ISD::CopyFromReg &&
4724 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
4725 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
4726 (Op.getOpcode() == ISD::LOAD &&
4727 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
4728 (Op.getOpcode() == ISD::MERGE_VALUES &&
4729 Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
4730 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
4736 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
4737 /// DAG and fixes their tailcall attribute operand.
4738 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4739 TargetLowering& TLI) {
4740 SDNode * Ret = NULL;
4741 SDOperand Terminator = DAG.getRoot();
4744 if (Terminator.getOpcode() == ISD::RET) {
4745 Ret = Terminator.Val;
4748 // Fix tail call attribute of CALL nodes.
4749 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
4750 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
4751 if (BI->getOpcode() == ISD::CALL) {
4752 SDOperand OpRet(Ret, 0);
4753 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
4754 bool isMarkedTailCall =
4755 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
4756 // If CALL node has tail call attribute set to true and the call is not
4757 // eligible (no RET or the target rejects) the attribute is fixed to
4758 // false. The TargetLowering::IsEligibleForTailCallOptimization function
4759 // must correctly identify tail call optimizable calls.
4760 if (!isMarkedTailCall) continue;
4762 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG)) {
4763 // Not eligible. Mark CALL node as non tail call.
4764 SmallVector<SDOperand, 32> Ops;
4766 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
4767 E = OpCall.Val->op_end(); I != E; I++, idx++) {
4771 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
4773 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4775 // Look for tail call clobbered arguments. Emit a series of
4776 // copyto/copyfrom virtual register nodes to protect them.
4777 SmallVector<SDOperand, 32> Ops;
4778 SDOperand Chain = OpCall.getOperand(0), InFlag;
4780 for(SDNode::op_iterator I = OpCall.Val->op_begin(),
4781 E = OpCall.Val->op_end(); I != E; I++, idx++) {
4783 if (idx > 4 && (idx % 2)) {
4784 bool isByVal = cast<ARG_FLAGSSDNode>(OpCall.getOperand(idx+1))->
4785 getArgFlags().isByVal();
4786 MachineFunction &MF = DAG.getMachineFunction();
4787 MachineFrameInfo *MFI = MF.getFrameInfo();
4789 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
4790 MVT::ValueType VT = Arg.getValueType();
4791 unsigned VReg = MF.getRegInfo().
4792 createVirtualRegister(TLI.getRegClassFor(VT));
4793 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
4794 InFlag = Chain.getValue(1);
4795 Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
4796 Chain = Arg.getValue(1);
4797 InFlag = Arg.getValue(2);
4802 // Link in chain of CopyTo/CopyFromReg.
4804 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4810 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4811 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4812 FunctionLoweringInfo &FuncInfo) {
4813 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
4815 // Lower any arguments needed in this block if this is the entry block.
4816 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4817 LowerArguments(LLVMBB, SDL);
4819 BB = FuncInfo.MBBMap[LLVMBB];
4820 SDL.setCurrentBasicBlock(BB);
4822 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4824 if (MMI && BB->isLandingPad()) {
4825 // Add a label to mark the beginning of the landing pad. Deletion of the
4826 // landing pad can thus be detected via the MachineModuleInfo.
4827 unsigned LabelID = MMI->addLandingPad(BB);
4828 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4829 DAG.getConstant(LabelID, MVT::i32),
4830 DAG.getConstant(1, MVT::i32)));
4832 // Mark exception register as live in.
4833 unsigned Reg = TLI.getExceptionAddressRegister();
4834 if (Reg) BB->addLiveIn(Reg);
4836 // Mark exception selector register as live in.
4837 Reg = TLI.getExceptionSelectorRegister();
4838 if (Reg) BB->addLiveIn(Reg);
4840 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4841 // function and list of typeids logically belong to the invoke (or, if you
4842 // like, the basic block containing the invoke), and need to be associated
4843 // with it in the dwarf exception handling tables. Currently however the
4844 // information is provided by an intrinsic (eh.selector) that can be moved
4845 // to unexpected places by the optimizers: if the unwind edge is critical,
4846 // then breaking it can result in the intrinsics being in the successor of
4847 // the landing pad, not the landing pad itself. This results in exceptions
4848 // not being caught because no typeids are associated with the invoke.
4849 // This may not be the only way things can go wrong, but it is the only way
4850 // we try to work around for the moment.
4851 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4853 if (Br && Br->isUnconditional()) { // Critical edge?
4854 BasicBlock::iterator I, E;
4855 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
4860 // No catch info found - try to extract some from the successor.
4861 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
4865 // Lower all of the non-terminator instructions.
4866 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4870 // Ensure that all instructions which are used outside of their defining
4871 // blocks are available as virtual registers. Invoke is handled elsewhere.
4872 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4873 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
4874 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4875 if (VMI != FuncInfo.ValueMap.end())
4876 SDL.CopyValueToVirtualRegister(I, VMI->second);
4879 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4880 // ensure constants are generated when needed. Remember the virtual registers
4881 // that need to be added to the Machine PHI nodes as input. We cannot just
4882 // directly add them, because expansion might result in multiple MBB's for one
4883 // BB. As such, the start of the BB might correspond to a different MBB than
4886 TerminatorInst *TI = LLVMBB->getTerminator();
4888 // Emit constants only once even if used by multiple PHI nodes.
4889 std::map<Constant*, unsigned> ConstantsOut;
4891 // Vector bool would be better, but vector<bool> is really slow.
4892 std::vector<unsigned char> SuccsHandled;
4893 if (TI->getNumSuccessors())
4894 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4896 // Check successor nodes' PHI nodes that expect a constant to be available
4898 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4899 BasicBlock *SuccBB = TI->getSuccessor(succ);
4900 if (!isa<PHINode>(SuccBB->begin())) continue;
4901 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4903 // If this terminator has multiple identical successors (common for
4904 // switches), only handle each succ once.
4905 unsigned SuccMBBNo = SuccMBB->getNumber();
4906 if (SuccsHandled[SuccMBBNo]) continue;
4907 SuccsHandled[SuccMBBNo] = true;
4909 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4912 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4913 // nodes and Machine PHI nodes, but the incoming operands have not been
4915 for (BasicBlock::iterator I = SuccBB->begin();
4916 (PN = dyn_cast<PHINode>(I)); ++I) {
4917 // Ignore dead phi's.
4918 if (PN->use_empty()) continue;
4921 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4923 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4924 unsigned &RegOut = ConstantsOut[C];
4926 RegOut = FuncInfo.CreateRegForValue(C);
4927 SDL.CopyValueToVirtualRegister(C, RegOut);
4931 Reg = FuncInfo.ValueMap[PHIOp];
4933 assert(isa<AllocaInst>(PHIOp) &&
4934 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4935 "Didn't codegen value into a register!??");
4936 Reg = FuncInfo.CreateRegForValue(PHIOp);
4937 SDL.CopyValueToVirtualRegister(PHIOp, Reg);
4941 // Remember that this register needs to added to the machine PHI node as
4942 // the input for this MBB.
4943 MVT::ValueType VT = TLI.getValueType(PN->getType());
4944 unsigned NumRegisters = TLI.getNumRegisters(VT);
4945 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
4946 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4949 ConstantsOut.clear();
4951 // Lower the terminator after the copies are emitted.
4952 SDL.visit(*LLVMBB->getTerminator());
4954 // Copy over any CaseBlock records that may now exist due to SwitchInst
4955 // lowering, as well as any jump table information.
4956 SwitchCases.clear();
4957 SwitchCases = SDL.SwitchCases;
4959 JTCases = SDL.JTCases;
4960 BitTestCases.clear();
4961 BitTestCases = SDL.BitTestCases;
4963 // Make sure the root of the DAG is up-to-date.
4964 DAG.setRoot(SDL.getControlRoot());
4966 // Check whether calls in this block are real tail calls. Fix up CALL nodes
4967 // with correct tailcall attribute so that the target can rely on the tailcall
4968 // attribute indicating whether the call is really eligible for tail call
4970 CheckDAGForTailCallsAndFixThem(DAG, TLI);
4973 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4974 DOUT << "Lowered selection DAG:\n";
4977 // Run the DAG combiner in pre-legalize mode.
4978 DAG.Combine(false, *AA);
4980 DOUT << "Optimized lowered selection DAG:\n";
4983 // Second step, hack on the DAG until it only uses operations and types that
4984 // the target supports.
4985 #if 0 // Enable this some day.
4986 DAG.LegalizeTypes();
4987 // Someday even later, enable a dag combine pass here.
4991 DOUT << "Legalized selection DAG:\n";
4994 // Run the DAG combiner in post-legalize mode.
4995 DAG.Combine(true, *AA);
4997 DOUT << "Optimized legalized selection DAG:\n";
5000 if (ViewISelDAGs) DAG.viewGraph();
5002 // Third, instruction select all of the operations to machine code, adding the
5003 // code to the MachineBasicBlock.
5004 InstructionSelectBasicBlock(DAG);
5006 DOUT << "Selected machine code:\n";
5010 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
5011 FunctionLoweringInfo &FuncInfo) {
5012 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
5014 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5017 // First step, lower LLVM code to some DAG. This DAG may use operations and
5018 // types that are not supported by the target.
5019 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
5021 // Second step, emit the lowered DAG as machine code.
5022 CodeGenAndEmitDAG(DAG);
5025 DOUT << "Total amount of phi nodes to update: "
5026 << PHINodesToUpdate.size() << "\n";
5027 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
5028 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
5029 << ", " << PHINodesToUpdate[i].second << ")\n";);
5031 // Next, now that we know what the last MBB the LLVM BB expanded is, update
5032 // PHI nodes in successors.
5033 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
5034 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5035 MachineInstr *PHI = PHINodesToUpdate[i].first;
5036 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5037 "This is not a machine PHI node that we are updating!");
5038 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5040 PHI->addOperand(MachineOperand::CreateMBB(BB));
5045 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
5046 // Lower header first, if it wasn't already lowered
5047 if (!BitTestCases[i].Emitted) {
5048 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5050 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5051 // Set the current basic block to the mbb we wish to insert the code into
5052 BB = BitTestCases[i].Parent;
5053 HSDL.setCurrentBasicBlock(BB);
5055 HSDL.visitBitTestHeader(BitTestCases[i]);
5056 HSDAG.setRoot(HSDL.getRoot());
5057 CodeGenAndEmitDAG(HSDAG);
5060 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5061 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5063 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
5064 // Set the current basic block to the mbb we wish to insert the code into
5065 BB = BitTestCases[i].Cases[j].ThisBB;
5066 BSDL.setCurrentBasicBlock(BB);
5069 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
5070 BitTestCases[i].Reg,
5071 BitTestCases[i].Cases[j]);
5073 BSDL.visitBitTestCase(BitTestCases[i].Default,
5074 BitTestCases[i].Reg,
5075 BitTestCases[i].Cases[j]);
5078 BSDAG.setRoot(BSDL.getRoot());
5079 CodeGenAndEmitDAG(BSDAG);
5083 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5084 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5085 MachineBasicBlock *PHIBB = PHI->getParent();
5086 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5087 "This is not a machine PHI node that we are updating!");
5088 // This is "default" BB. We have two jumps to it. From "header" BB and
5089 // from last "case" BB.
5090 if (PHIBB == BitTestCases[i].Default) {
5091 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5093 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5094 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5096 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5099 // One of "cases" BB.
5100 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5101 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5102 if (cBB->succ_end() !=
5103 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5104 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5106 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5112 // If the JumpTable record is filled in, then we need to emit a jump table.
5113 // Updating the PHI nodes is tricky in this case, since we need to determine
5114 // whether the PHI is a successor of the range check MBB or the jump table MBB
5115 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5116 // Lower header first, if it wasn't already lowered
5117 if (!JTCases[i].first.Emitted) {
5118 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5120 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5121 // Set the current basic block to the mbb we wish to insert the code into
5122 BB = JTCases[i].first.HeaderBB;
5123 HSDL.setCurrentBasicBlock(BB);
5125 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5126 HSDAG.setRoot(HSDL.getRoot());
5127 CodeGenAndEmitDAG(HSDAG);
5130 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5132 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
5133 // Set the current basic block to the mbb we wish to insert the code into
5134 BB = JTCases[i].second.MBB;
5135 JSDL.setCurrentBasicBlock(BB);
5137 JSDL.visitJumpTable(JTCases[i].second);
5138 JSDAG.setRoot(JSDL.getRoot());
5139 CodeGenAndEmitDAG(JSDAG);
5142 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5143 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5144 MachineBasicBlock *PHIBB = PHI->getParent();
5145 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5146 "This is not a machine PHI node that we are updating!");
5147 // "default" BB. We can go there only from header BB.
5148 if (PHIBB == JTCases[i].second.Default) {
5149 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5151 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5153 // JT BB. Just iterate over successors here
5154 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5155 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5157 PHI->addOperand(MachineOperand::CreateMBB(BB));
5162 // If the switch block involved a branch to one of the actual successors, we
5163 // need to update PHI nodes in that block.
5164 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5165 MachineInstr *PHI = PHINodesToUpdate[i].first;
5166 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5167 "This is not a machine PHI node that we are updating!");
5168 if (BB->isSuccessor(PHI->getParent())) {
5169 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5171 PHI->addOperand(MachineOperand::CreateMBB(BB));
5175 // If we generated any switch lowering information, build and codegen any
5176 // additional DAGs necessary.
5177 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5178 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5180 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
5182 // Set the current basic block to the mbb we wish to insert the code into
5183 BB = SwitchCases[i].ThisBB;
5184 SDL.setCurrentBasicBlock(BB);
5187 SDL.visitSwitchCase(SwitchCases[i]);
5188 SDAG.setRoot(SDL.getRoot());
5189 CodeGenAndEmitDAG(SDAG);
5191 // Handle any PHI nodes in successors of this chunk, as if we were coming
5192 // from the original BB before switch expansion. Note that PHI nodes can
5193 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5194 // handle them the right number of times.
5195 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5196 for (MachineBasicBlock::iterator Phi = BB->begin();
5197 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5198 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5199 for (unsigned pn = 0; ; ++pn) {
5200 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5201 if (PHINodesToUpdate[pn].first == Phi) {
5202 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5204 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5210 // Don't process RHS if same block as LHS.
5211 if (BB == SwitchCases[i].FalseBB)
5212 SwitchCases[i].FalseBB = 0;
5214 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5215 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5216 SwitchCases[i].FalseBB = 0;
5218 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5223 //===----------------------------------------------------------------------===//
5224 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
5225 /// target node in the graph.
5226 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
5227 if (ViewSchedDAGs) DAG.viewGraph();
5229 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5233 RegisterScheduler::setDefault(Ctor);
5236 ScheduleDAG *SL = Ctor(this, &DAG, BB);
5239 if (ViewSUnitDAGs) SL->viewGraph();
5245 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5246 return new HazardRecognizer();
5249 //===----------------------------------------------------------------------===//
5250 // Helper functions used by the generated instruction selector.
5251 //===----------------------------------------------------------------------===//
5252 // Calls to these methods are generated by tblgen.
5254 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5255 /// the dag combiner simplified the 255, we still want to match. RHS is the
5256 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5257 /// specified in the .td file (e.g. 255).
5258 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
5259 int64_t DesiredMaskS) const {
5260 const APInt &ActualMask = RHS->getAPIntValue();
5261 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5263 // If the actual mask exactly matches, success!
5264 if (ActualMask == DesiredMask)
5267 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5268 if (ActualMask.intersects(~DesiredMask))
5271 // Otherwise, the DAG Combiner may have proven that the value coming in is
5272 // either already zero or is not demanded. Check for known zero input bits.
5273 APInt NeededMask = DesiredMask & ~ActualMask;
5274 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5277 // TODO: check to see if missing bits are just not demanded.
5279 // Otherwise, this pattern doesn't match.
5283 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5284 /// the dag combiner simplified the 255, we still want to match. RHS is the
5285 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5286 /// specified in the .td file (e.g. 255).
5287 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5288 int64_t DesiredMaskS) const {
5289 const APInt &ActualMask = RHS->getAPIntValue();
5290 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
5292 // If the actual mask exactly matches, success!
5293 if (ActualMask == DesiredMask)
5296 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5297 if (ActualMask.intersects(~DesiredMask))
5300 // Otherwise, the DAG Combiner may have proven that the value coming in is
5301 // either already zero or is not demanded. Check for known zero input bits.
5302 APInt NeededMask = DesiredMask & ~ActualMask;
5304 APInt KnownZero, KnownOne;
5305 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5307 // If all the missing bits in the or are already known to be set, match!
5308 if ((NeededMask & KnownOne) == NeededMask)
5311 // TODO: check to see if missing bits are just not demanded.
5313 // Otherwise, this pattern doesn't match.
5318 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5319 /// by tblgen. Others should not call it.
5320 void SelectionDAGISel::
5321 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5322 std::vector<SDOperand> InOps;
5323 std::swap(InOps, Ops);
5325 Ops.push_back(InOps[0]); // input chain.
5326 Ops.push_back(InOps[1]); // input asm string.
5328 unsigned i = 2, e = InOps.size();
5329 if (InOps[e-1].getValueType() == MVT::Flag)
5330 --e; // Don't process a flag operand if it is here.
5333 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5334 if ((Flags & 7) != 4 /*MEM*/) {
5335 // Just skip over this operand, copying the operands verbatim.
5336 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5337 i += (Flags >> 3) + 1;
5339 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5340 // Otherwise, this is a memory operand. Ask the target to select it.
5341 std::vector<SDOperand> SelOps;
5342 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5343 cerr << "Could not match memory address. Inline asm failure!\n";
5347 // Add this to the output node.
5348 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5349 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5351 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5356 // Add the flag input back if present.
5357 if (e != InOps.size())
5358 Ops.push_back(InOps.back());
5361 char SelectionDAGISel::ID = 0;