1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/Timer.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/ADT/Statistic.h"
55 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
56 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
59 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
60 cl::desc("Enable verbose messages in the \"fast\" "
61 "instruction selector"));
63 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
64 cl::desc("Enable abort calls when \"fast\" instruction fails"));
68 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
69 cl::desc("Pop up a window to show dags before the first "
72 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
73 cl::desc("Pop up a window to show dags before legalize types"));
75 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
76 cl::desc("Pop up a window to show dags before legalize"));
78 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the second "
82 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
83 cl::desc("Pop up a window to show dags before the post legalize types"
84 " dag combine pass"));
86 ViewISelDAGs("view-isel-dags", cl::Hidden,
87 cl::desc("Pop up a window to show isel dags as they are selected"));
89 ViewSchedDAGs("view-sched-dags", cl::Hidden,
90 cl::desc("Pop up a window to show sched dags as they are processed"));
92 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
93 cl::desc("Pop up a window to show SUnit dags after they are processed"));
95 static const bool ViewDAGCombine1 = false,
96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
97 ViewDAGCombine2 = false,
98 ViewDAGCombineLT = false,
99 ViewISelDAGs = false, ViewSchedDAGs = false,
100 ViewSUnitDAGs = false;
103 //===---------------------------------------------------------------------===//
105 /// RegisterScheduler class - Track the registration of instruction schedulers.
107 //===---------------------------------------------------------------------===//
108 MachinePassRegistry RegisterScheduler::Registry;
110 //===---------------------------------------------------------------------===//
112 /// ISHeuristic command line option for instruction schedulers.
114 //===---------------------------------------------------------------------===//
115 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
116 RegisterPassParser<RegisterScheduler> >
117 ISHeuristic("pre-RA-sched",
118 cl::init(&createDefaultScheduler),
119 cl::desc("Instruction schedulers available (before register"
122 static RegisterScheduler
123 defaultListDAGScheduler("default", "Best scheduler for the target",
124 createDefaultScheduler);
127 //===--------------------------------------------------------------------===//
128 /// createDefaultScheduler - This creates an instruction scheduler appropriate
130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
131 CodeGenOpt::Level OptLevel) {
132 const TargetLowering &TLI = IS->getTargetLowering();
134 if (OptLevel == CodeGenOpt::None)
135 return createFastDAGScheduler(IS, OptLevel);
136 if (TLI.getSchedulingPreference() == Sched::Latency)
137 return createTDListDAGScheduler(IS, OptLevel);
138 if (TLI.getSchedulingPreference() == Sched::RegPressure)
139 return createBURRListDAGScheduler(IS, OptLevel);
140 assert(TLI.getSchedulingPreference() == Sched::Hybrid &&
141 "Unknown sched type!");
142 return createHybridListDAGScheduler(IS, OptLevel);
146 // EmitInstrWithCustomInserter - This method should be implemented by targets
147 // that mark instructions with the 'usesCustomInserter' flag. These
148 // instructions are special in various ways, which require special support to
149 // insert. The specified MachineInstr is created but not inserted into any
150 // basic blocks, and this method is called to expand it into a sequence of
151 // instructions, potentially also creating new basic blocks and control flow.
152 // When new basic blocks are inserted and the edges from MBB to its successors
153 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
156 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
157 MachineBasicBlock *MBB) const {
159 dbgs() << "If a target marks an instruction with "
160 "'usesCustomInserter', it must implement "
161 "TargetLowering::EmitInstrWithCustomInserter!";
167 //===----------------------------------------------------------------------===//
168 // SelectionDAGISel code
169 //===----------------------------------------------------------------------===//
171 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
172 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
173 FuncInfo(new FunctionLoweringInfo(TLI)),
174 CurDAG(new SelectionDAG(tm)),
175 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
181 SelectionDAGISel::~SelectionDAGISel() {
187 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
188 AU.addRequired<AliasAnalysis>();
189 AU.addPreserved<AliasAnalysis>();
190 AU.addRequired<GCModuleInfo>();
191 AU.addPreserved<GCModuleInfo>();
192 MachineFunctionPass::getAnalysisUsage(AU);
195 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
196 /// other function that gcc recognizes as "returning twice". This is used to
197 /// limit code-gen optimizations on the machine function.
199 /// FIXME: Remove after <rdar://problem/8031714> is fixed.
200 static bool FunctionCallsSetJmp(const Function *F) {
201 const Module *M = F->getParent();
202 static const char *ReturnsTwiceFns[] = {
211 #define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *)
213 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I)
214 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) {
215 if (!Callee->use_empty())
216 for (Value::const_use_iterator
217 I = Callee->use_begin(), E = Callee->use_end();
219 if (const CallInst *CI = dyn_cast<CallInst>(I))
220 if (CI->getParent()->getParent() == F)
225 #undef NUM_RETURNS_TWICE_FNS
228 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
229 // Do some sanity-checking on the command-line options.
230 assert((!EnableFastISelVerbose || EnableFastISel) &&
231 "-fast-isel-verbose requires -fast-isel");
232 assert((!EnableFastISelAbort || EnableFastISel) &&
233 "-fast-isel-abort requires -fast-isel");
235 const Function &Fn = *mf.getFunction();
236 const TargetInstrInfo &TII = *TM.getInstrInfo();
237 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
240 RegInfo = &MF->getRegInfo();
241 AA = &getAnalysis<AliasAnalysis>();
242 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
244 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
247 FuncInfo->set(Fn, *MF);
250 SelectAllBasicBlocks(Fn);
252 // If the first basic block in the function has live ins that need to be
253 // copied into vregs, emit the copies into the top of the block before
254 // emitting the code for the block.
255 MachineBasicBlock *EntryMBB = MF->begin();
256 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
258 DenseMap<unsigned, unsigned> LiveInMap;
259 if (!FuncInfo->ArgDbgValues.empty())
260 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
261 E = RegInfo->livein_end(); LI != E; ++LI)
263 LiveInMap.insert(std::make_pair(LI->first, LI->second));
265 // Insert DBG_VALUE instructions for function arguments to the entry block.
266 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
267 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
268 unsigned Reg = MI->getOperand(0).getReg();
269 if (TargetRegisterInfo::isPhysicalRegister(Reg))
270 EntryMBB->insert(EntryMBB->begin(), MI);
272 MachineInstr *Def = RegInfo->getVRegDef(Reg);
273 MachineBasicBlock::iterator InsertPos = Def;
274 // FIXME: VR def may not be in entry block.
275 Def->getParent()->insert(llvm::next(InsertPos), MI);
278 // If Reg is live-in then update debug info to track its copy in a vreg.
279 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
280 if (LDI != LiveInMap.end()) {
281 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
282 MachineBasicBlock::iterator InsertPos = Def;
283 const MDNode *Variable =
284 MI->getOperand(MI->getNumOperands()-1).getMetadata();
285 unsigned Offset = MI->getOperand(1).getImm();
286 // Def is never a terminator here, so it is ok to increment InsertPos.
287 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
288 TII.get(TargetOpcode::DBG_VALUE))
289 .addReg(LDI->second, RegState::Debug)
290 .addImm(Offset).addMetadata(Variable);
294 // Determine if there are any calls in this machine function.
295 MachineFrameInfo *MFI = MF->getFrameInfo();
296 if (!MFI->hasCalls()) {
297 for (MachineFunction::const_iterator
298 I = MF->begin(), E = MF->end(); I != E; ++I) {
299 const MachineBasicBlock *MBB = I;
300 for (MachineBasicBlock::const_iterator
301 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
302 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
303 if (II->isInlineAsm() || (TID.isCall() && !TID.isReturn())) {
304 MFI->setHasCalls(true);
312 // Determine if there is a call to setjmp in the machine function.
313 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
315 // Release function-specific state. SDB and CurDAG are already cleared
323 SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB,
324 const BasicBlock *LLVMBB,
325 BasicBlock::const_iterator Begin,
326 BasicBlock::const_iterator End,
328 // Lower all of the non-terminator instructions. If a call is emitted
329 // as a tail call, cease emitting nodes for this block. Terminators
330 // are handled below.
331 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
334 // Make sure the root of the DAG is up-to-date.
335 CurDAG->setRoot(SDB->getControlRoot());
336 HadTailCall = SDB->HasTailCall;
339 // Final step, emit the lowered DAG as machine code.
340 return CodeGenAndEmitDAG(BB);
344 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
345 /// nodes from the worklist.
346 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
347 SmallVector<SDNode*, 128> &Worklist;
348 SmallPtrSet<SDNode*, 128> &InWorklist;
350 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
351 SmallPtrSet<SDNode*, 128> &inwl)
352 : Worklist(wl), InWorklist(inwl) {}
354 void RemoveFromWorklist(SDNode *N) {
355 if (!InWorklist.erase(N)) return;
357 SmallVector<SDNode*, 128>::iterator I =
358 std::find(Worklist.begin(), Worklist.end(), N);
359 assert(I != Worklist.end() && "Not in worklist");
361 *I = Worklist.back();
365 virtual void NodeDeleted(SDNode *N, SDNode *E) {
366 RemoveFromWorklist(N);
369 virtual void NodeUpdated(SDNode *N) {
375 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
376 SmallPtrSet<SDNode*, 128> VisitedNodes;
377 SmallVector<SDNode*, 128> Worklist;
379 Worklist.push_back(CurDAG->getRoot().getNode());
386 SDNode *N = Worklist.pop_back_val();
388 // If we've already seen this node, ignore it.
389 if (!VisitedNodes.insert(N))
392 // Otherwise, add all chain operands to the worklist.
393 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
394 if (N->getOperand(i).getValueType() == MVT::Other)
395 Worklist.push_back(N->getOperand(i).getNode());
397 // If this is a CopyToReg with a vreg dest, process it.
398 if (N->getOpcode() != ISD::CopyToReg)
401 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
402 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
405 // Ignore non-scalar or non-integer values.
406 SDValue Src = N->getOperand(2);
407 EVT SrcVT = Src.getValueType();
408 if (!SrcVT.isInteger() || SrcVT.isVector())
411 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
412 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
413 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
415 // Only install this information if it tells us something.
416 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
417 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
418 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
419 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
420 FunctionLoweringInfo::LiveOutInfo &LOI =
421 FuncInfo->LiveOutRegInfo[DestReg];
422 LOI.NumSignBits = NumSignBits;
423 LOI.KnownOne = KnownOne;
424 LOI.KnownZero = KnownZero;
426 } while (!Worklist.empty());
429 MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) {
430 std::string GroupName;
431 if (TimePassesIsEnabled)
432 GroupName = "Instruction Selection and Scheduling";
433 std::string BlockName;
434 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
435 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
437 BlockName = MF->getFunction()->getNameStr() + ":" +
438 BB->getBasicBlock()->getNameStr();
440 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
442 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
444 // Run the DAG combiner in pre-legalize mode.
446 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
447 CurDAG->Combine(Unrestricted, *AA, OptLevel);
450 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump());
452 // Second step, hack on the DAG until it only uses operations and types that
453 // the target supports.
454 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
459 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
460 Changed = CurDAG->LegalizeTypes();
463 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump());
466 if (ViewDAGCombineLT)
467 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
469 // Run the DAG combiner in post-type-legalize mode.
471 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
472 TimePassesIsEnabled);
473 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
476 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n";
481 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
482 Changed = CurDAG->LegalizeVectors();
487 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
488 CurDAG->LegalizeTypes();
491 if (ViewDAGCombineLT)
492 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
494 // Run the DAG combiner in post-type-legalize mode.
496 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
497 TimePassesIsEnabled);
498 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
501 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n";
505 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
508 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
509 CurDAG->Legalize(OptLevel);
512 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump());
514 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
516 // Run the DAG combiner in post-legalize mode.
518 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
519 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
522 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump());
524 if (OptLevel != CodeGenOpt::None)
525 ComputeLiveOutVRegInfo();
527 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
529 // Third, instruction select all of the operations to machine code, adding the
530 // code to the MachineBasicBlock.
532 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
533 DoInstructionSelection();
536 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump());
538 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
540 // Schedule machine code.
541 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
543 NamedRegionTimer T("Instruction Scheduling", GroupName,
544 TimePassesIsEnabled);
545 Scheduler->Run(CurDAG, BB, BB->end());
548 if (ViewSUnitDAGs) Scheduler->viewGraph();
550 // Emit machine code to BB. This can change 'BB' to the last block being
553 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
554 BB = Scheduler->EmitSchedule();
557 // Free the scheduler state.
559 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
560 TimePassesIsEnabled);
564 // Free the SelectionDAG state, now that we're finished with it.
570 void SelectionDAGISel::DoInstructionSelection() {
571 DEBUG(errs() << "===== Instruction selection begins:\n");
575 // Select target instructions for the DAG.
577 // Number all nodes with a topological order and set DAGSize.
578 DAGSize = CurDAG->AssignTopologicalOrder();
580 // Create a dummy node (which is not added to allnodes), that adds
581 // a reference to the root node, preventing it from being deleted,
582 // and tracking any changes of the root.
583 HandleSDNode Dummy(CurDAG->getRoot());
584 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
587 // The AllNodes list is now topological-sorted. Visit the
588 // nodes by starting at the end of the list (the root of the
589 // graph) and preceding back toward the beginning (the entry
591 while (ISelPosition != CurDAG->allnodes_begin()) {
592 SDNode *Node = --ISelPosition;
593 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
594 // but there are currently some corner cases that it misses. Also, this
595 // makes it theoretically possible to disable the DAGCombiner.
596 if (Node->use_empty())
599 SDNode *ResNode = Select(Node);
601 // FIXME: This is pretty gross. 'Select' should be changed to not return
602 // anything at all and this code should be nuked with a tactical strike.
604 // If node should not be replaced, continue with the next one.
605 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
609 ReplaceUses(Node, ResNode);
611 // If after the replacement this node is not used any more,
612 // remove this dead node.
613 if (Node->use_empty()) { // Don't delete EntryToken, etc.
614 ISelUpdater ISU(ISelPosition);
615 CurDAG->RemoveDeadNode(Node, &ISU);
619 CurDAG->setRoot(Dummy.getValue());
622 DEBUG(errs() << "===== Instruction selection ends:\n");
624 PostprocessISelDAG();
627 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
628 /// do other setup for EH landing-pad blocks.
629 void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) {
630 // Add a label to mark the beginning of the landing pad. Deletion of the
631 // landing pad can thus be detected via the MachineModuleInfo.
632 MCSymbol *Label = MF->getMMI().addLandingPad(BB);
634 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
635 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
637 // Mark exception register as live in.
638 unsigned Reg = TLI.getExceptionAddressRegister();
639 if (Reg) BB->addLiveIn(Reg);
641 // Mark exception selector register as live in.
642 Reg = TLI.getExceptionSelectorRegister();
643 if (Reg) BB->addLiveIn(Reg);
645 // FIXME: Hack around an exception handling flaw (PR1508): the personality
646 // function and list of typeids logically belong to the invoke (or, if you
647 // like, the basic block containing the invoke), and need to be associated
648 // with it in the dwarf exception handling tables. Currently however the
649 // information is provided by an intrinsic (eh.selector) that can be moved
650 // to unexpected places by the optimizers: if the unwind edge is critical,
651 // then breaking it can result in the intrinsics being in the successor of
652 // the landing pad, not the landing pad itself. This results
653 // in exceptions not being caught because no typeids are associated with
654 // the invoke. This may not be the only way things can go wrong, but it
655 // is the only way we try to work around for the moment.
656 const BasicBlock *LLVMBB = BB->getBasicBlock();
657 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
659 if (Br && Br->isUnconditional()) { // Critical edge?
660 BasicBlock::const_iterator I, E;
661 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
662 if (isa<EHSelectorInst>(I))
666 // No catch info found - try to extract some from the successor.
667 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
671 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
672 // Initialize the Fast-ISel state, if needed.
673 FastISel *FastIS = 0;
675 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
676 FuncInfo->StaticAllocaMap,
677 FuncInfo->PHINodesToUpdate
679 , FuncInfo->CatchInfoLost
683 // Iterate over all basic blocks in the function.
684 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
685 const BasicBlock *LLVMBB = &*I;
686 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB];
688 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
689 BasicBlock::const_iterator const End = LLVMBB->end();
690 BasicBlock::const_iterator BI = Begin;
692 // Lower any arguments needed in this block if this is the entry block.
693 if (LLVMBB == &Fn.getEntryBlock())
694 LowerArguments(LLVMBB);
696 // Setup an EH landing-pad block.
697 if (BB->isLandingPad())
698 PrepareEHLandingPad(BB);
700 // Before doing SelectionDAG ISel, see if FastISel has been requested.
702 // Emit code for any incoming arguments. This must happen before
703 // beginning FastISel on the entry block.
704 if (LLVMBB == &Fn.getEntryBlock()) {
705 CurDAG->setRoot(SDB->getControlRoot());
707 BB = CodeGenAndEmitDAG(BB);
709 FastIS->startNewBlock(BB);
710 // Do FastISel on as many instructions as possible.
711 for (; BI != End; ++BI) {
713 // Defer instructions with no side effects; they'll be emitted
715 if (BI->isSafeToSpeculativelyExecute() &&
716 !FuncInfo->isExportedInst(BI))
720 // Try to select the instruction with FastISel.
721 if (FastIS->SelectInstruction(BI))
724 // Then handle certain instructions as single-LLVM-Instruction blocks.
725 if (isa<CallInst>(BI)) {
726 ++NumFastIselFailures;
727 if (EnableFastISelVerbose || EnableFastISelAbort) {
728 dbgs() << "FastISel missed call: ";
732 if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
733 unsigned &R = FuncInfo->ValueMap[BI];
735 R = FuncInfo->CreateRegs(BI->getType());
738 bool HadTailCall = false;
739 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall);
741 // If the call was emitted as a tail call, we're done with the block.
747 // If the instruction was codegen'd with multiple blocks,
748 // inform the FastISel object where to resume inserting.
749 FastIS->setCurrentBlock(BB);
753 // Otherwise, give up on FastISel for the rest of the block.
754 // For now, be a little lenient about non-branch terminators.
755 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
756 ++NumFastIselFailures;
757 if (EnableFastISelVerbose || EnableFastISelAbort) {
758 dbgs() << "FastISel miss: ";
761 if (EnableFastISelAbort)
762 // The "fast" selector couldn't handle something and bailed.
763 // For the purpose of debugging, just abort.
764 llvm_unreachable("FastISel didn't select the entire block");
770 // Run SelectionDAG instruction selection on the remainder of the block
771 // not handled by FastISel. If FastISel is not run, this is the entire
775 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall);
778 FinishBasicBlock(BB);
779 FuncInfo->PHINodesToUpdate.clear();
786 SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) {
788 DEBUG(dbgs() << "Total amount of phi nodes to update: "
789 << FuncInfo->PHINodesToUpdate.size() << "\n";
790 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
791 dbgs() << "Node " << i << " : ("
792 << FuncInfo->PHINodesToUpdate[i].first
793 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
795 // Next, now that we know what the last MBB the LLVM BB expanded is, update
796 // PHI nodes in successors.
797 if (SDB->SwitchCases.empty() &&
798 SDB->JTCases.empty() &&
799 SDB->BitTestCases.empty()) {
800 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
801 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
802 assert(PHI->isPHI() &&
803 "This is not a machine PHI node that we are updating!");
804 if (!BB->isSuccessor(PHI->getParent()))
807 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
808 PHI->addOperand(MachineOperand::CreateMBB(BB));
813 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
814 // Lower header first, if it wasn't already lowered
815 if (!SDB->BitTestCases[i].Emitted) {
816 // Set the current basic block to the mbb we wish to insert the code into
817 BB = SDB->BitTestCases[i].Parent;
819 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB);
820 CurDAG->setRoot(SDB->getRoot());
822 BB = CodeGenAndEmitDAG(BB);
825 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
826 // Set the current basic block to the mbb we wish to insert the code into
827 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
830 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
831 SDB->BitTestCases[i].Reg,
832 SDB->BitTestCases[i].Cases[j],
835 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
836 SDB->BitTestCases[i].Reg,
837 SDB->BitTestCases[i].Cases[j],
841 CurDAG->setRoot(SDB->getRoot());
843 BB = CodeGenAndEmitDAG(BB);
847 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
849 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
850 MachineBasicBlock *PHIBB = PHI->getParent();
851 assert(PHI->isPHI() &&
852 "This is not a machine PHI node that we are updating!");
853 // This is "default" BB. We have two jumps to it. From "header" BB and
854 // from last "case" BB.
855 if (PHIBB == SDB->BitTestCases[i].Default) {
856 PHI->addOperand(MachineOperand::
857 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
859 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
860 PHI->addOperand(MachineOperand::
861 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
863 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
866 // One of "cases" BB.
867 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
869 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
870 if (cBB->isSuccessor(PHIBB)) {
871 PHI->addOperand(MachineOperand::
872 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
874 PHI->addOperand(MachineOperand::CreateMBB(cBB));
879 SDB->BitTestCases.clear();
881 // If the JumpTable record is filled in, then we need to emit a jump table.
882 // Updating the PHI nodes is tricky in this case, since we need to determine
883 // whether the PHI is a successor of the range check MBB or the jump table MBB
884 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
885 // Lower header first, if it wasn't already lowered
886 if (!SDB->JTCases[i].first.Emitted) {
887 // Set the current basic block to the mbb we wish to insert the code into
888 BB = SDB->JTCases[i].first.HeaderBB;
890 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
892 CurDAG->setRoot(SDB->getRoot());
894 BB = CodeGenAndEmitDAG(BB);
897 // Set the current basic block to the mbb we wish to insert the code into
898 BB = SDB->JTCases[i].second.MBB;
900 SDB->visitJumpTable(SDB->JTCases[i].second);
901 CurDAG->setRoot(SDB->getRoot());
903 BB = CodeGenAndEmitDAG(BB);
906 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
908 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
909 MachineBasicBlock *PHIBB = PHI->getParent();
910 assert(PHI->isPHI() &&
911 "This is not a machine PHI node that we are updating!");
912 // "default" BB. We can go there only from header BB.
913 if (PHIBB == SDB->JTCases[i].second.Default) {
915 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
918 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
920 // JT BB. Just iterate over successors here
921 if (BB->isSuccessor(PHIBB)) {
923 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
925 PHI->addOperand(MachineOperand::CreateMBB(BB));
929 SDB->JTCases.clear();
931 // If the switch block involved a branch to one of the actual successors, we
932 // need to update PHI nodes in that block.
933 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
934 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
935 assert(PHI->isPHI() &&
936 "This is not a machine PHI node that we are updating!");
937 if (BB->isSuccessor(PHI->getParent())) {
939 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
940 PHI->addOperand(MachineOperand::CreateMBB(BB));
944 // If we generated any switch lowering information, build and codegen any
945 // additional DAGs necessary.
946 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
947 // Set the current basic block to the mbb we wish to insert the code into
948 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
950 // Determine the unique successors.
951 SmallVector<MachineBasicBlock *, 2> Succs;
952 Succs.push_back(SDB->SwitchCases[i].TrueBB);
953 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
954 Succs.push_back(SDB->SwitchCases[i].FalseBB);
956 // Emit the code. Note that this could result in ThisBB being split, so
957 // we need to check for updates.
958 SDB->visitSwitchCase(SDB->SwitchCases[i], BB);
959 CurDAG->setRoot(SDB->getRoot());
961 ThisBB = CodeGenAndEmitDAG(BB);
963 // Handle any PHI nodes in successors of this chunk, as if we were coming
964 // from the original BB before switch expansion. Note that PHI nodes can
965 // occur multiple times in PHINodesToUpdate. We have to be very careful to
966 // handle them the right number of times.
967 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
969 // BB may have been removed from the CFG if a branch was constant folded.
970 if (ThisBB->isSuccessor(BB)) {
971 for (MachineBasicBlock::iterator Phi = BB->begin();
972 Phi != BB->end() && Phi->isPHI();
974 // This value for this PHI node is recorded in PHINodesToUpdate.
975 for (unsigned pn = 0; ; ++pn) {
976 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
977 "Didn't find PHI entry!");
978 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
979 Phi->addOperand(MachineOperand::
980 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
982 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
990 SDB->SwitchCases.clear();
994 /// Create the scheduler. If a specific scheduler was specified
995 /// via the SchedulerRegistry, use it, otherwise select the
996 /// one preferred by the target.
998 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
999 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1003 RegisterScheduler::setDefault(Ctor);
1006 return Ctor(this, OptLevel);
1009 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1010 return new ScheduleHazardRecognizer();
1013 //===----------------------------------------------------------------------===//
1014 // Helper functions used by the generated instruction selector.
1015 //===----------------------------------------------------------------------===//
1016 // Calls to these methods are generated by tblgen.
1018 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1019 /// the dag combiner simplified the 255, we still want to match. RHS is the
1020 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1021 /// specified in the .td file (e.g. 255).
1022 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1023 int64_t DesiredMaskS) const {
1024 const APInt &ActualMask = RHS->getAPIntValue();
1025 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1027 // If the actual mask exactly matches, success!
1028 if (ActualMask == DesiredMask)
1031 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1032 if (ActualMask.intersects(~DesiredMask))
1035 // Otherwise, the DAG Combiner may have proven that the value coming in is
1036 // either already zero or is not demanded. Check for known zero input bits.
1037 APInt NeededMask = DesiredMask & ~ActualMask;
1038 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1041 // TODO: check to see if missing bits are just not demanded.
1043 // Otherwise, this pattern doesn't match.
1047 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1048 /// the dag combiner simplified the 255, we still want to match. RHS is the
1049 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1050 /// specified in the .td file (e.g. 255).
1051 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1052 int64_t DesiredMaskS) const {
1053 const APInt &ActualMask = RHS->getAPIntValue();
1054 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1056 // If the actual mask exactly matches, success!
1057 if (ActualMask == DesiredMask)
1060 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1061 if (ActualMask.intersects(~DesiredMask))
1064 // Otherwise, the DAG Combiner may have proven that the value coming in is
1065 // either already zero or is not demanded. Check for known zero input bits.
1066 APInt NeededMask = DesiredMask & ~ActualMask;
1068 APInt KnownZero, KnownOne;
1069 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1071 // If all the missing bits in the or are already known to be set, match!
1072 if ((NeededMask & KnownOne) == NeededMask)
1075 // TODO: check to see if missing bits are just not demanded.
1077 // Otherwise, this pattern doesn't match.
1082 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1083 /// by tblgen. Others should not call it.
1084 void SelectionDAGISel::
1085 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1086 std::vector<SDValue> InOps;
1087 std::swap(InOps, Ops);
1089 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1090 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1091 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1092 Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3
1094 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1095 if (InOps[e-1].getValueType() == MVT::Flag)
1096 --e; // Don't process a flag operand if it is here.
1099 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1100 if (!InlineAsm::isMemKind(Flags)) {
1101 // Just skip over this operand, copying the operands verbatim.
1102 Ops.insert(Ops.end(), InOps.begin()+i,
1103 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1104 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1106 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1107 "Memory operand with multiple values?");
1108 // Otherwise, this is a memory operand. Ask the target to select it.
1109 std::vector<SDValue> SelOps;
1110 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1111 report_fatal_error("Could not match memory address. Inline asm"
1114 // Add this to the output node.
1116 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1117 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1118 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1123 // Add the flag input back if present.
1124 if (e != InOps.size())
1125 Ops.push_back(InOps.back());
1128 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1131 static SDNode *findFlagUse(SDNode *N) {
1132 unsigned FlagResNo = N->getNumValues()-1;
1133 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1134 SDUse &Use = I.getUse();
1135 if (Use.getResNo() == FlagResNo)
1136 return Use.getUser();
1141 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1142 /// This function recursively traverses up the operand chain, ignoring
1144 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1145 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1146 bool IgnoreChains) {
1147 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1148 // greater than all of its (recursive) operands. If we scan to a point where
1149 // 'use' is smaller than the node we're scanning for, then we know we will
1152 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1153 // happen because we scan down to newly selected nodes in the case of flag
1155 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1158 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1159 // won't fail if we scan it again.
1160 if (!Visited.insert(Use))
1163 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1164 // Ignore chain uses, they are validated by HandleMergeInputChains.
1165 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1168 SDNode *N = Use->getOperand(i).getNode();
1170 if (Use == ImmedUse || Use == Root)
1171 continue; // We are not looking for immediate use.
1176 // Traverse up the operand chain.
1177 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1183 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1184 /// operand node N of U during instruction selection that starts at Root.
1185 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1186 SDNode *Root) const {
1187 if (OptLevel == CodeGenOpt::None) return false;
1188 return N.hasOneUse();
1191 /// IsLegalToFold - Returns true if the specific operand node N of
1192 /// U can be folded during instruction selection that starts at Root.
1193 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1194 CodeGenOpt::Level OptLevel,
1195 bool IgnoreChains) {
1196 if (OptLevel == CodeGenOpt::None) return false;
1198 // If Root use can somehow reach N through a path that that doesn't contain
1199 // U then folding N would create a cycle. e.g. In the following
1200 // diagram, Root can reach N through X. If N is folded into into Root, then
1201 // X is both a predecessor and a successor of U.
1212 // * indicates nodes to be folded together.
1214 // If Root produces a flag, then it gets (even more) interesting. Since it
1215 // will be "glued" together with its flag use in the scheduler, we need to
1216 // check if it might reach N.
1235 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1236 // (call it Fold), then X is a predecessor of FU and a successor of
1237 // Fold. But since Fold and FU are flagged together, this will create
1238 // a cycle in the scheduling graph.
1240 // If the node has flags, walk down the graph to the "lowest" node in the
1242 EVT VT = Root->getValueType(Root->getNumValues()-1);
1243 while (VT == MVT::Flag) {
1244 SDNode *FU = findFlagUse(Root);
1248 VT = Root->getValueType(Root->getNumValues()-1);
1250 // If our query node has a flag result with a use, we've walked up it. If
1251 // the user (which has already been selected) has a chain or indirectly uses
1252 // the chain, our WalkChainUsers predicate will not consider it. Because of
1253 // this, we cannot ignore chains in this predicate.
1254 IgnoreChains = false;
1258 SmallPtrSet<SDNode*, 16> Visited;
1259 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1262 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1263 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1264 SelectInlineAsmMemoryOperands(Ops);
1266 std::vector<EVT> VTs;
1267 VTs.push_back(MVT::Other);
1268 VTs.push_back(MVT::Flag);
1269 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1270 VTs, &Ops[0], Ops.size());
1272 return New.getNode();
1275 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1276 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1279 /// GetVBR - decode a vbr encoding whose top bit is set.
1280 ALWAYS_INLINE static uint64_t
1281 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1282 assert(Val >= 128 && "Not a VBR");
1283 Val &= 127; // Remove first vbr bit.
1288 NextBits = MatcherTable[Idx++];
1289 Val |= (NextBits&127) << Shift;
1291 } while (NextBits & 128);
1297 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1298 /// interior flag and chain results to use the new flag and chain results.
1299 void SelectionDAGISel::
1300 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1301 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1303 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1304 bool isMorphNodeTo) {
1305 SmallVector<SDNode*, 4> NowDeadNodes;
1307 ISelUpdater ISU(ISelPosition);
1309 // Now that all the normal results are replaced, we replace the chain and
1310 // flag results if present.
1311 if (!ChainNodesMatched.empty()) {
1312 assert(InputChain.getNode() != 0 &&
1313 "Matched input chains but didn't produce a chain");
1314 // Loop over all of the nodes we matched that produced a chain result.
1315 // Replace all the chain results with the final chain we ended up with.
1316 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1317 SDNode *ChainNode = ChainNodesMatched[i];
1319 // If this node was already deleted, don't look at it.
1320 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1323 // Don't replace the results of the root node if we're doing a
1325 if (ChainNode == NodeToMatch && isMorphNodeTo)
1328 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1329 if (ChainVal.getValueType() == MVT::Flag)
1330 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1331 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1332 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1334 // If the node became dead and we haven't already seen it, delete it.
1335 if (ChainNode->use_empty() &&
1336 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1337 NowDeadNodes.push_back(ChainNode);
1341 // If the result produces a flag, update any flag results in the matched
1342 // pattern with the flag result.
1343 if (InputFlag.getNode() != 0) {
1344 // Handle any interior nodes explicitly marked.
1345 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1346 SDNode *FRN = FlagResultNodesMatched[i];
1348 // If this node was already deleted, don't look at it.
1349 if (FRN->getOpcode() == ISD::DELETED_NODE)
1352 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1353 "Doesn't have a flag result");
1354 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1357 // If the node became dead and we haven't already seen it, delete it.
1358 if (FRN->use_empty() &&
1359 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1360 NowDeadNodes.push_back(FRN);
1364 if (!NowDeadNodes.empty())
1365 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1367 DEBUG(errs() << "ISEL: Match complete!\n");
1373 CR_LeadsToInteriorNode
1376 /// WalkChainUsers - Walk down the users of the specified chained node that is
1377 /// part of the pattern we're matching, looking at all of the users we find.
1378 /// This determines whether something is an interior node, whether we have a
1379 /// non-pattern node in between two pattern nodes (which prevent folding because
1380 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1381 /// between pattern nodes (in which case the TF becomes part of the pattern).
1383 /// The walk we do here is guaranteed to be small because we quickly get down to
1384 /// already selected nodes "below" us.
1386 WalkChainUsers(SDNode *ChainedNode,
1387 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1388 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1389 ChainResult Result = CR_Simple;
1391 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1392 E = ChainedNode->use_end(); UI != E; ++UI) {
1393 // Make sure the use is of the chain, not some other value we produce.
1394 if (UI.getUse().getValueType() != MVT::Other) continue;
1398 // If we see an already-selected machine node, then we've gone beyond the
1399 // pattern that we're selecting down into the already selected chunk of the
1401 if (User->isMachineOpcode() ||
1402 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1405 if (User->getOpcode() == ISD::CopyToReg ||
1406 User->getOpcode() == ISD::CopyFromReg ||
1407 User->getOpcode() == ISD::INLINEASM ||
1408 User->getOpcode() == ISD::EH_LABEL) {
1409 // If their node ID got reset to -1 then they've already been selected.
1410 // Treat them like a MachineOpcode.
1411 if (User->getNodeId() == -1)
1415 // If we have a TokenFactor, we handle it specially.
1416 if (User->getOpcode() != ISD::TokenFactor) {
1417 // If the node isn't a token factor and isn't part of our pattern, then it
1418 // must be a random chained node in between two nodes we're selecting.
1419 // This happens when we have something like:
1424 // Because we structurally match the load/store as a read/modify/write,
1425 // but the call is chained between them. We cannot fold in this case
1426 // because it would induce a cycle in the graph.
1427 if (!std::count(ChainedNodesInPattern.begin(),
1428 ChainedNodesInPattern.end(), User))
1429 return CR_InducesCycle;
1431 // Otherwise we found a node that is part of our pattern. For example in:
1435 // This would happen when we're scanning down from the load and see the
1436 // store as a user. Record that there is a use of ChainedNode that is
1437 // part of the pattern and keep scanning uses.
1438 Result = CR_LeadsToInteriorNode;
1439 InteriorChainedNodes.push_back(User);
1443 // If we found a TokenFactor, there are two cases to consider: first if the
1444 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1445 // uses of the TF are in our pattern) we just want to ignore it. Second,
1446 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1452 // | \ DAG's like cheese
1455 // [TokenFactor] [Op]
1462 // In this case, the TokenFactor becomes part of our match and we rewrite it
1463 // as a new TokenFactor.
1465 // To distinguish these two cases, do a recursive walk down the uses.
1466 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1468 // If the uses of the TokenFactor are just already-selected nodes, ignore
1469 // it, it is "below" our pattern.
1471 case CR_InducesCycle:
1472 // If the uses of the TokenFactor lead to nodes that are not part of our
1473 // pattern that are not selected, folding would turn this into a cycle,
1475 return CR_InducesCycle;
1476 case CR_LeadsToInteriorNode:
1477 break; // Otherwise, keep processing.
1480 // Okay, we know we're in the interesting interior case. The TokenFactor
1481 // is now going to be considered part of the pattern so that we rewrite its
1482 // uses (it may have uses that are not part of the pattern) with the
1483 // ultimate chain result of the generated code. We will also add its chain
1484 // inputs as inputs to the ultimate TokenFactor we create.
1485 Result = CR_LeadsToInteriorNode;
1486 ChainedNodesInPattern.push_back(User);
1487 InteriorChainedNodes.push_back(User);
1494 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1495 /// operation for when the pattern matched at least one node with a chains. The
1496 /// input vector contains a list of all of the chained nodes that we match. We
1497 /// must determine if this is a valid thing to cover (i.e. matching it won't
1498 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1499 /// be used as the input node chain for the generated nodes.
1501 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1502 SelectionDAG *CurDAG) {
1503 // Walk all of the chained nodes we've matched, recursively scanning down the
1504 // users of the chain result. This adds any TokenFactor nodes that are caught
1505 // in between chained nodes to the chained and interior nodes list.
1506 SmallVector<SDNode*, 3> InteriorChainedNodes;
1507 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1508 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1509 InteriorChainedNodes) == CR_InducesCycle)
1510 return SDValue(); // Would induce a cycle.
1513 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1514 // that we are interested in. Form our input TokenFactor node.
1515 SmallVector<SDValue, 3> InputChains;
1516 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1517 // Add the input chain of this node to the InputChains list (which will be
1518 // the operands of the generated TokenFactor) if it's not an interior node.
1519 SDNode *N = ChainNodesMatched[i];
1520 if (N->getOpcode() != ISD::TokenFactor) {
1521 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1524 // Otherwise, add the input chain.
1525 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1526 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1527 InputChains.push_back(InChain);
1531 // If we have a token factor, we want to add all inputs of the token factor
1532 // that are not part of the pattern we're matching.
1533 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1534 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1535 N->getOperand(op).getNode()))
1536 InputChains.push_back(N->getOperand(op));
1541 if (InputChains.size() == 1)
1542 return InputChains[0];
1543 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1544 MVT::Other, &InputChains[0], InputChains.size());
1547 /// MorphNode - Handle morphing a node in place for the selector.
1548 SDNode *SelectionDAGISel::
1549 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1550 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1551 // It is possible we're using MorphNodeTo to replace a node with no
1552 // normal results with one that has a normal result (or we could be
1553 // adding a chain) and the input could have flags and chains as well.
1554 // In this case we need to shift the operands down.
1555 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1556 // than the old isel though.
1557 int OldFlagResultNo = -1, OldChainResultNo = -1;
1559 unsigned NTMNumResults = Node->getNumValues();
1560 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1561 OldFlagResultNo = NTMNumResults-1;
1562 if (NTMNumResults != 1 &&
1563 Node->getValueType(NTMNumResults-2) == MVT::Other)
1564 OldChainResultNo = NTMNumResults-2;
1565 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1566 OldChainResultNo = NTMNumResults-1;
1568 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1569 // that this deletes operands of the old node that become dead.
1570 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1572 // MorphNodeTo can operate in two ways: if an existing node with the
1573 // specified operands exists, it can just return it. Otherwise, it
1574 // updates the node in place to have the requested operands.
1576 // If we updated the node in place, reset the node ID. To the isel,
1577 // this should be just like a newly allocated machine node.
1581 unsigned ResNumResults = Res->getNumValues();
1582 // Move the flag if needed.
1583 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1584 (unsigned)OldFlagResultNo != ResNumResults-1)
1585 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1586 SDValue(Res, ResNumResults-1));
1588 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1591 // Move the chain reference if needed.
1592 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1593 (unsigned)OldChainResultNo != ResNumResults-1)
1594 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1595 SDValue(Res, ResNumResults-1));
1597 // Otherwise, no replacement happened because the node already exists. Replace
1598 // Uses of the old node with the new one.
1600 CurDAG->ReplaceAllUsesWith(Node, Res);
1605 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1606 ALWAYS_INLINE static bool
1607 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1608 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1609 // Accept if it is exactly the same as a previously recorded node.
1610 unsigned RecNo = MatcherTable[MatcherIndex++];
1611 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1612 return N == RecordedNodes[RecNo];
1615 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1616 ALWAYS_INLINE static bool
1617 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1618 SelectionDAGISel &SDISel) {
1619 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1622 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1623 ALWAYS_INLINE static bool
1624 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1625 SelectionDAGISel &SDISel, SDNode *N) {
1626 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1629 ALWAYS_INLINE static bool
1630 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1632 uint16_t Opc = MatcherTable[MatcherIndex++];
1633 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1634 return N->getOpcode() == Opc;
1637 ALWAYS_INLINE static bool
1638 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1639 SDValue N, const TargetLowering &TLI) {
1640 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1641 if (N.getValueType() == VT) return true;
1643 // Handle the case when VT is iPTR.
1644 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1647 ALWAYS_INLINE static bool
1648 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1649 SDValue N, const TargetLowering &TLI,
1651 if (ChildNo >= N.getNumOperands())
1652 return false; // Match fails if out of range child #.
1653 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1657 ALWAYS_INLINE static bool
1658 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1660 return cast<CondCodeSDNode>(N)->get() ==
1661 (ISD::CondCode)MatcherTable[MatcherIndex++];
1664 ALWAYS_INLINE static bool
1665 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1666 SDValue N, const TargetLowering &TLI) {
1667 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1668 if (cast<VTSDNode>(N)->getVT() == VT)
1671 // Handle the case when VT is iPTR.
1672 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1675 ALWAYS_INLINE static bool
1676 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1678 int64_t Val = MatcherTable[MatcherIndex++];
1680 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1682 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1683 return C != 0 && C->getSExtValue() == Val;
1686 ALWAYS_INLINE static bool
1687 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1688 SDValue N, SelectionDAGISel &SDISel) {
1689 int64_t Val = MatcherTable[MatcherIndex++];
1691 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1693 if (N->getOpcode() != ISD::AND) return false;
1695 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1696 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1699 ALWAYS_INLINE static bool
1700 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1701 SDValue N, SelectionDAGISel &SDISel) {
1702 int64_t Val = MatcherTable[MatcherIndex++];
1704 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1706 if (N->getOpcode() != ISD::OR) return false;
1708 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1709 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1712 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1713 /// scope, evaluate the current node. If the current predicate is known to
1714 /// fail, set Result=true and return anything. If the current predicate is
1715 /// known to pass, set Result=false and return the MatcherIndex to continue
1716 /// with. If the current predicate is unknown, set Result=false and return the
1717 /// MatcherIndex to continue with.
1718 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1719 unsigned Index, SDValue N,
1720 bool &Result, SelectionDAGISel &SDISel,
1721 SmallVectorImpl<SDValue> &RecordedNodes){
1722 switch (Table[Index++]) {
1725 return Index-1; // Could not evaluate this predicate.
1726 case SelectionDAGISel::OPC_CheckSame:
1727 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1729 case SelectionDAGISel::OPC_CheckPatternPredicate:
1730 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1732 case SelectionDAGISel::OPC_CheckPredicate:
1733 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1735 case SelectionDAGISel::OPC_CheckOpcode:
1736 Result = !::CheckOpcode(Table, Index, N.getNode());
1738 case SelectionDAGISel::OPC_CheckType:
1739 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1741 case SelectionDAGISel::OPC_CheckChild0Type:
1742 case SelectionDAGISel::OPC_CheckChild1Type:
1743 case SelectionDAGISel::OPC_CheckChild2Type:
1744 case SelectionDAGISel::OPC_CheckChild3Type:
1745 case SelectionDAGISel::OPC_CheckChild4Type:
1746 case SelectionDAGISel::OPC_CheckChild5Type:
1747 case SelectionDAGISel::OPC_CheckChild6Type:
1748 case SelectionDAGISel::OPC_CheckChild7Type:
1749 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1750 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1752 case SelectionDAGISel::OPC_CheckCondCode:
1753 Result = !::CheckCondCode(Table, Index, N);
1755 case SelectionDAGISel::OPC_CheckValueType:
1756 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1758 case SelectionDAGISel::OPC_CheckInteger:
1759 Result = !::CheckInteger(Table, Index, N);
1761 case SelectionDAGISel::OPC_CheckAndImm:
1762 Result = !::CheckAndImm(Table, Index, N, SDISel);
1764 case SelectionDAGISel::OPC_CheckOrImm:
1765 Result = !::CheckOrImm(Table, Index, N, SDISel);
1773 /// FailIndex - If this match fails, this is the index to continue with.
1776 /// NodeStack - The node stack when the scope was formed.
1777 SmallVector<SDValue, 4> NodeStack;
1779 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1780 unsigned NumRecordedNodes;
1782 /// NumMatchedMemRefs - The number of matched memref entries.
1783 unsigned NumMatchedMemRefs;
1785 /// InputChain/InputFlag - The current chain/flag
1786 SDValue InputChain, InputFlag;
1788 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1789 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1794 SDNode *SelectionDAGISel::
1795 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1796 unsigned TableSize) {
1797 // FIXME: Should these even be selected? Handle these cases in the caller?
1798 switch (NodeToMatch->getOpcode()) {
1801 case ISD::EntryToken: // These nodes remain the same.
1802 case ISD::BasicBlock:
1804 //case ISD::VALUETYPE:
1805 //case ISD::CONDCODE:
1806 case ISD::HANDLENODE:
1807 case ISD::MDNODE_SDNODE:
1808 case ISD::TargetConstant:
1809 case ISD::TargetConstantFP:
1810 case ISD::TargetConstantPool:
1811 case ISD::TargetFrameIndex:
1812 case ISD::TargetExternalSymbol:
1813 case ISD::TargetBlockAddress:
1814 case ISD::TargetJumpTable:
1815 case ISD::TargetGlobalTLSAddress:
1816 case ISD::TargetGlobalAddress:
1817 case ISD::TokenFactor:
1818 case ISD::CopyFromReg:
1819 case ISD::CopyToReg:
1821 NodeToMatch->setNodeId(-1); // Mark selected.
1823 case ISD::AssertSext:
1824 case ISD::AssertZext:
1825 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1826 NodeToMatch->getOperand(0));
1828 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1829 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1832 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1834 // Set up the node stack with NodeToMatch as the only node on the stack.
1835 SmallVector<SDValue, 8> NodeStack;
1836 SDValue N = SDValue(NodeToMatch, 0);
1837 NodeStack.push_back(N);
1839 // MatchScopes - Scopes used when matching, if a match failure happens, this
1840 // indicates where to continue checking.
1841 SmallVector<MatchScope, 8> MatchScopes;
1843 // RecordedNodes - This is the set of nodes that have been recorded by the
1845 SmallVector<SDValue, 8> RecordedNodes;
1847 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1849 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1851 // These are the current input chain and flag for use when generating nodes.
1852 // Various Emit operations change these. For example, emitting a copytoreg
1853 // uses and updates these.
1854 SDValue InputChain, InputFlag;
1856 // ChainNodesMatched - If a pattern matches nodes that have input/output
1857 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1858 // which ones they are. The result is captured into this list so that we can
1859 // update the chain results when the pattern is complete.
1860 SmallVector<SDNode*, 3> ChainNodesMatched;
1861 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1863 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1864 NodeToMatch->dump(CurDAG);
1867 // Determine where to start the interpreter. Normally we start at opcode #0,
1868 // but if the state machine starts with an OPC_SwitchOpcode, then we
1869 // accelerate the first lookup (which is guaranteed to be hot) with the
1870 // OpcodeOffset table.
1871 unsigned MatcherIndex = 0;
1873 if (!OpcodeOffset.empty()) {
1874 // Already computed the OpcodeOffset table, just index into it.
1875 if (N.getOpcode() < OpcodeOffset.size())
1876 MatcherIndex = OpcodeOffset[N.getOpcode()];
1877 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1879 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1880 // Otherwise, the table isn't computed, but the state machine does start
1881 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1882 // is the first time we're selecting an instruction.
1885 // Get the size of this case.
1886 unsigned CaseSize = MatcherTable[Idx++];
1888 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1889 if (CaseSize == 0) break;
1891 // Get the opcode, add the index to the table.
1892 uint16_t Opc = MatcherTable[Idx++];
1893 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
1894 if (Opc >= OpcodeOffset.size())
1895 OpcodeOffset.resize((Opc+1)*2);
1896 OpcodeOffset[Opc] = Idx;
1900 // Okay, do the lookup for the first opcode.
1901 if (N.getOpcode() < OpcodeOffset.size())
1902 MatcherIndex = OpcodeOffset[N.getOpcode()];
1906 assert(MatcherIndex < TableSize && "Invalid index");
1908 unsigned CurrentOpcodeIndex = MatcherIndex;
1910 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
1913 // Okay, the semantics of this operation are that we should push a scope
1914 // then evaluate the first child. However, pushing a scope only to have
1915 // the first check fail (which then pops it) is inefficient. If we can
1916 // determine immediately that the first check (or first several) will
1917 // immediately fail, don't even bother pushing a scope for them.
1921 unsigned NumToSkip = MatcherTable[MatcherIndex++];
1922 if (NumToSkip & 128)
1923 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
1924 // Found the end of the scope with no match.
1925 if (NumToSkip == 0) {
1930 FailIndex = MatcherIndex+NumToSkip;
1932 unsigned MatcherIndexOfPredicate = MatcherIndex;
1933 (void)MatcherIndexOfPredicate; // silence warning.
1935 // If we can't evaluate this predicate without pushing a scope (e.g. if
1936 // it is a 'MoveParent') or if the predicate succeeds on this node, we
1937 // push the scope and evaluate the full predicate chain.
1939 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
1940 Result, *this, RecordedNodes);
1944 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
1945 << "index " << MatcherIndexOfPredicate
1946 << ", continuing at " << FailIndex << "\n");
1947 ++NumDAGIselRetries;
1949 // Otherwise, we know that this case of the Scope is guaranteed to fail,
1950 // move to the next case.
1951 MatcherIndex = FailIndex;
1954 // If the whole scope failed to match, bail.
1955 if (FailIndex == 0) break;
1957 // Push a MatchScope which indicates where to go if the first child fails
1959 MatchScope NewEntry;
1960 NewEntry.FailIndex = FailIndex;
1961 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
1962 NewEntry.NumRecordedNodes = RecordedNodes.size();
1963 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
1964 NewEntry.InputChain = InputChain;
1965 NewEntry.InputFlag = InputFlag;
1966 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
1967 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
1968 MatchScopes.push_back(NewEntry);
1971 case OPC_RecordNode:
1972 // Remember this node, it may end up being an operand in the pattern.
1973 RecordedNodes.push_back(N);
1976 case OPC_RecordChild0: case OPC_RecordChild1:
1977 case OPC_RecordChild2: case OPC_RecordChild3:
1978 case OPC_RecordChild4: case OPC_RecordChild5:
1979 case OPC_RecordChild6: case OPC_RecordChild7: {
1980 unsigned ChildNo = Opcode-OPC_RecordChild0;
1981 if (ChildNo >= N.getNumOperands())
1982 break; // Match fails if out of range child #.
1984 RecordedNodes.push_back(N->getOperand(ChildNo));
1987 case OPC_RecordMemRef:
1988 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
1991 case OPC_CaptureFlagInput:
1992 // If the current node has an input flag, capture it in InputFlag.
1993 if (N->getNumOperands() != 0 &&
1994 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
1995 InputFlag = N->getOperand(N->getNumOperands()-1);
1998 case OPC_MoveChild: {
1999 unsigned ChildNo = MatcherTable[MatcherIndex++];
2000 if (ChildNo >= N.getNumOperands())
2001 break; // Match fails if out of range child #.
2002 N = N.getOperand(ChildNo);
2003 NodeStack.push_back(N);
2007 case OPC_MoveParent:
2008 // Pop the current node off the NodeStack.
2009 NodeStack.pop_back();
2010 assert(!NodeStack.empty() && "Node stack imbalance!");
2011 N = NodeStack.back();
2015 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2017 case OPC_CheckPatternPredicate:
2018 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2020 case OPC_CheckPredicate:
2021 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2025 case OPC_CheckComplexPat: {
2026 unsigned CPNum = MatcherTable[MatcherIndex++];
2027 unsigned RecNo = MatcherTable[MatcherIndex++];
2028 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2029 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2034 case OPC_CheckOpcode:
2035 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2039 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2042 case OPC_SwitchOpcode: {
2043 unsigned CurNodeOpcode = N.getOpcode();
2044 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2047 // Get the size of this case.
2048 CaseSize = MatcherTable[MatcherIndex++];
2050 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2051 if (CaseSize == 0) break;
2053 uint16_t Opc = MatcherTable[MatcherIndex++];
2054 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2056 // If the opcode matches, then we will execute this case.
2057 if (CurNodeOpcode == Opc)
2060 // Otherwise, skip over this case.
2061 MatcherIndex += CaseSize;
2064 // If no cases matched, bail out.
2065 if (CaseSize == 0) break;
2067 // Otherwise, execute the case we found.
2068 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2069 << " to " << MatcherIndex << "\n");
2073 case OPC_SwitchType: {
2074 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2075 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2078 // Get the size of this case.
2079 CaseSize = MatcherTable[MatcherIndex++];
2081 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2082 if (CaseSize == 0) break;
2084 MVT::SimpleValueType CaseVT =
2085 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2086 if (CaseVT == MVT::iPTR)
2087 CaseVT = TLI.getPointerTy().SimpleTy;
2089 // If the VT matches, then we will execute this case.
2090 if (CurNodeVT == CaseVT)
2093 // Otherwise, skip over this case.
2094 MatcherIndex += CaseSize;
2097 // If no cases matched, bail out.
2098 if (CaseSize == 0) break;
2100 // Otherwise, execute the case we found.
2101 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2102 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2105 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2106 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2107 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2108 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2109 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2110 Opcode-OPC_CheckChild0Type))
2113 case OPC_CheckCondCode:
2114 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2116 case OPC_CheckValueType:
2117 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2119 case OPC_CheckInteger:
2120 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2122 case OPC_CheckAndImm:
2123 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2125 case OPC_CheckOrImm:
2126 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2129 case OPC_CheckFoldableChainNode: {
2130 assert(NodeStack.size() != 1 && "No parent node");
2131 // Verify that all intermediate nodes between the root and this one have
2133 bool HasMultipleUses = false;
2134 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2135 if (!NodeStack[i].hasOneUse()) {
2136 HasMultipleUses = true;
2139 if (HasMultipleUses) break;
2141 // Check to see that the target thinks this is profitable to fold and that
2142 // we can fold it without inducing cycles in the graph.
2143 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2145 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2146 NodeToMatch, OptLevel,
2147 true/*We validate our own chains*/))
2152 case OPC_EmitInteger: {
2153 MVT::SimpleValueType VT =
2154 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2155 int64_t Val = MatcherTable[MatcherIndex++];
2157 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2158 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2161 case OPC_EmitRegister: {
2162 MVT::SimpleValueType VT =
2163 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2164 unsigned RegNo = MatcherTable[MatcherIndex++];
2165 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2169 case OPC_EmitConvertToTarget: {
2170 // Convert from IMM/FPIMM to target version.
2171 unsigned RecNo = MatcherTable[MatcherIndex++];
2172 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2173 SDValue Imm = RecordedNodes[RecNo];
2175 if (Imm->getOpcode() == ISD::Constant) {
2176 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2177 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2178 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2179 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2180 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2183 RecordedNodes.push_back(Imm);
2187 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2188 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2189 // These are space-optimized forms of OPC_EmitMergeInputChains.
2190 assert(InputChain.getNode() == 0 &&
2191 "EmitMergeInputChains should be the first chain producing node");
2192 assert(ChainNodesMatched.empty() &&
2193 "Should only have one EmitMergeInputChains per match");
2195 // Read all of the chained nodes.
2196 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2197 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2198 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2200 // FIXME: What if other value results of the node have uses not matched
2202 if (ChainNodesMatched.back() != NodeToMatch &&
2203 !RecordedNodes[RecNo].hasOneUse()) {
2204 ChainNodesMatched.clear();
2208 // Merge the input chains if they are not intra-pattern references.
2209 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2211 if (InputChain.getNode() == 0)
2212 break; // Failed to merge.
2216 case OPC_EmitMergeInputChains: {
2217 assert(InputChain.getNode() == 0 &&
2218 "EmitMergeInputChains should be the first chain producing node");
2219 // This node gets a list of nodes we matched in the input that have
2220 // chains. We want to token factor all of the input chains to these nodes
2221 // together. However, if any of the input chains is actually one of the
2222 // nodes matched in this pattern, then we have an intra-match reference.
2223 // Ignore these because the newly token factored chain should not refer to
2225 unsigned NumChains = MatcherTable[MatcherIndex++];
2226 assert(NumChains != 0 && "Can't TF zero chains");
2228 assert(ChainNodesMatched.empty() &&
2229 "Should only have one EmitMergeInputChains per match");
2231 // Read all of the chained nodes.
2232 for (unsigned i = 0; i != NumChains; ++i) {
2233 unsigned RecNo = MatcherTable[MatcherIndex++];
2234 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2235 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2237 // FIXME: What if other value results of the node have uses not matched
2239 if (ChainNodesMatched.back() != NodeToMatch &&
2240 !RecordedNodes[RecNo].hasOneUse()) {
2241 ChainNodesMatched.clear();
2246 // If the inner loop broke out, the match fails.
2247 if (ChainNodesMatched.empty())
2250 // Merge the input chains if they are not intra-pattern references.
2251 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2253 if (InputChain.getNode() == 0)
2254 break; // Failed to merge.
2259 case OPC_EmitCopyToReg: {
2260 unsigned RecNo = MatcherTable[MatcherIndex++];
2261 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2262 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2264 if (InputChain.getNode() == 0)
2265 InputChain = CurDAG->getEntryNode();
2267 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2268 DestPhysReg, RecordedNodes[RecNo],
2271 InputFlag = InputChain.getValue(1);
2275 case OPC_EmitNodeXForm: {
2276 unsigned XFormNo = MatcherTable[MatcherIndex++];
2277 unsigned RecNo = MatcherTable[MatcherIndex++];
2278 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2279 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2284 case OPC_MorphNodeTo: {
2285 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2286 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2287 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2288 // Get the result VT list.
2289 unsigned NumVTs = MatcherTable[MatcherIndex++];
2290 SmallVector<EVT, 4> VTs;
2291 for (unsigned i = 0; i != NumVTs; ++i) {
2292 MVT::SimpleValueType VT =
2293 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2294 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2298 if (EmitNodeInfo & OPFL_Chain)
2299 VTs.push_back(MVT::Other);
2300 if (EmitNodeInfo & OPFL_FlagOutput)
2301 VTs.push_back(MVT::Flag);
2303 // This is hot code, so optimize the two most common cases of 1 and 2
2306 if (VTs.size() == 1)
2307 VTList = CurDAG->getVTList(VTs[0]);
2308 else if (VTs.size() == 2)
2309 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2311 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2313 // Get the operand list.
2314 unsigned NumOps = MatcherTable[MatcherIndex++];
2315 SmallVector<SDValue, 8> Ops;
2316 for (unsigned i = 0; i != NumOps; ++i) {
2317 unsigned RecNo = MatcherTable[MatcherIndex++];
2319 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2321 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2322 Ops.push_back(RecordedNodes[RecNo]);
2325 // If there are variadic operands to add, handle them now.
2326 if (EmitNodeInfo & OPFL_VariadicInfo) {
2327 // Determine the start index to copy from.
2328 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2329 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2330 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2331 "Invalid variadic node");
2332 // Copy all of the variadic operands, not including a potential flag
2334 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2336 SDValue V = NodeToMatch->getOperand(i);
2337 if (V.getValueType() == MVT::Flag) break;
2342 // If this has chain/flag inputs, add them.
2343 if (EmitNodeInfo & OPFL_Chain)
2344 Ops.push_back(InputChain);
2345 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2346 Ops.push_back(InputFlag);
2350 if (Opcode != OPC_MorphNodeTo) {
2351 // If this is a normal EmitNode command, just create the new node and
2352 // add the results to the RecordedNodes list.
2353 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2354 VTList, Ops.data(), Ops.size());
2356 // Add all the non-flag/non-chain results to the RecordedNodes list.
2357 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2358 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2359 RecordedNodes.push_back(SDValue(Res, i));
2363 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2367 // If the node had chain/flag results, update our notion of the current
2369 if (EmitNodeInfo & OPFL_FlagOutput) {
2370 InputFlag = SDValue(Res, VTs.size()-1);
2371 if (EmitNodeInfo & OPFL_Chain)
2372 InputChain = SDValue(Res, VTs.size()-2);
2373 } else if (EmitNodeInfo & OPFL_Chain)
2374 InputChain = SDValue(Res, VTs.size()-1);
2376 // If the OPFL_MemRefs flag is set on this node, slap all of the
2377 // accumulated memrefs onto it.
2379 // FIXME: This is vastly incorrect for patterns with multiple outputs
2380 // instructions that access memory and for ComplexPatterns that match
2382 if (EmitNodeInfo & OPFL_MemRefs) {
2383 MachineSDNode::mmo_iterator MemRefs =
2384 MF->allocateMemRefsArray(MatchedMemRefs.size());
2385 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2386 cast<MachineSDNode>(Res)
2387 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2391 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2392 << " node: "; Res->dump(CurDAG); errs() << "\n");
2394 // If this was a MorphNodeTo then we're completely done!
2395 if (Opcode == OPC_MorphNodeTo) {
2396 // Update chain and flag uses.
2397 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2398 InputFlag, FlagResultNodesMatched, true);
2405 case OPC_MarkFlagResults: {
2406 unsigned NumNodes = MatcherTable[MatcherIndex++];
2408 // Read and remember all the flag-result nodes.
2409 for (unsigned i = 0; i != NumNodes; ++i) {
2410 unsigned RecNo = MatcherTable[MatcherIndex++];
2412 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2414 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2415 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2420 case OPC_CompleteMatch: {
2421 // The match has been completed, and any new nodes (if any) have been
2422 // created. Patch up references to the matched dag to use the newly
2424 unsigned NumResults = MatcherTable[MatcherIndex++];
2426 for (unsigned i = 0; i != NumResults; ++i) {
2427 unsigned ResSlot = MatcherTable[MatcherIndex++];
2429 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2431 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2432 SDValue Res = RecordedNodes[ResSlot];
2434 assert(i < NodeToMatch->getNumValues() &&
2435 NodeToMatch->getValueType(i) != MVT::Other &&
2436 NodeToMatch->getValueType(i) != MVT::Flag &&
2437 "Invalid number of results to complete!");
2438 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2439 NodeToMatch->getValueType(i) == MVT::iPTR ||
2440 Res.getValueType() == MVT::iPTR ||
2441 NodeToMatch->getValueType(i).getSizeInBits() ==
2442 Res.getValueType().getSizeInBits()) &&
2443 "invalid replacement");
2444 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2447 // If the root node defines a flag, add it to the flag nodes to update
2449 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2450 FlagResultNodesMatched.push_back(NodeToMatch);
2452 // Update chain and flag uses.
2453 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2454 InputFlag, FlagResultNodesMatched, false);
2456 assert(NodeToMatch->use_empty() &&
2457 "Didn't replace all uses of the node?");
2459 // FIXME: We just return here, which interacts correctly with SelectRoot
2460 // above. We should fix this to not return an SDNode* anymore.
2465 // If the code reached this point, then the match failed. See if there is
2466 // another child to try in the current 'Scope', otherwise pop it until we
2467 // find a case to check.
2468 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2469 ++NumDAGIselRetries;
2471 if (MatchScopes.empty()) {
2472 CannotYetSelect(NodeToMatch);
2476 // Restore the interpreter state back to the point where the scope was
2478 MatchScope &LastScope = MatchScopes.back();
2479 RecordedNodes.resize(LastScope.NumRecordedNodes);
2481 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2482 N = NodeStack.back();
2484 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2485 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2486 MatcherIndex = LastScope.FailIndex;
2488 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2490 InputChain = LastScope.InputChain;
2491 InputFlag = LastScope.InputFlag;
2492 if (!LastScope.HasChainNodesMatched)
2493 ChainNodesMatched.clear();
2494 if (!LastScope.HasFlagResultNodesMatched)
2495 FlagResultNodesMatched.clear();
2497 // Check to see what the offset is at the new MatcherIndex. If it is zero
2498 // we have reached the end of this scope, otherwise we have another child
2499 // in the current scope to try.
2500 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2501 if (NumToSkip & 128)
2502 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2504 // If we have another child in this scope to match, update FailIndex and
2506 if (NumToSkip != 0) {
2507 LastScope.FailIndex = MatcherIndex+NumToSkip;
2511 // End of this scope, pop it and try the next child in the containing
2513 MatchScopes.pop_back();
2520 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2522 raw_string_ostream Msg(msg);
2523 Msg << "Cannot yet select: ";
2525 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2526 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2527 N->getOpcode() != ISD::INTRINSIC_VOID) {
2528 N->printrFull(Msg, CurDAG);
2530 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2532 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2533 if (iid < Intrinsic::num_intrinsics)
2534 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2535 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2536 Msg << "target intrinsic %" << TII->getName(iid);
2538 Msg << "unknown intrinsic #" << iid;
2540 report_fatal_error(Msg.str());
2543 char SelectionDAGISel::ID = 0;