1 //===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAG class, which is a base class used by
11 // scheduling implementation classes.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "pre-RA-sched"
16 #include "llvm/CodeGen/ScheduleDAGSDNodes.h"
17 #include "llvm/CodeGen/SelectionDAG.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
25 ScheduleDAGSDNodes::ScheduleDAGSDNodes(SelectionDAG *dag, MachineBasicBlock *bb,
26 const TargetMachine &tm)
27 : ScheduleDAG(dag, bb, tm) {
30 SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
31 SUnit *SU = NewSUnit(Old->getNode());
32 SU->OrigNode = Old->OrigNode;
33 SU->Latency = Old->Latency;
34 SU->isTwoAddress = Old->isTwoAddress;
35 SU->isCommutable = Old->isCommutable;
36 SU->hasPhysRegDefs = Old->hasPhysRegDefs;
40 /// CheckForPhysRegDependency - Check if the dependency between def and use of
41 /// a specified operand is a physical register dependency. If so, returns the
42 /// register and the cost of copying the register.
43 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
44 const TargetRegisterInfo *TRI,
45 const TargetInstrInfo *TII,
46 unsigned &PhysReg, int &Cost) {
47 if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
50 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
51 if (TargetRegisterInfo::isVirtualRegister(Reg))
54 unsigned ResNo = User->getOperand(2).getResNo();
55 if (Def->isMachineOpcode()) {
56 const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
57 if (ResNo >= II.getNumDefs() &&
58 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
60 const TargetRegisterClass *RC =
61 TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo));
62 Cost = RC->getCopyCost();
67 /// BuildSchedUnits - Build SUnits from the selection dag that we are input.
68 /// This SUnit graph is similar to the SelectionDAG, but represents flagged
69 /// together nodes with a single SUnit.
70 void ScheduleDAGSDNodes::BuildSchedUnits() {
71 // Reserve entries in the vector for each of the SUnits we are creating. This
72 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
74 SUnits.reserve(DAG->allnodes_size());
76 // During scheduling, the NodeId field of SDNode is used to map SDNodes
77 // to their associated SUnits by holding SUnits table indices. A value
78 // of -1 means the SDNode does not yet have an associated SUnit.
79 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
80 E = DAG->allnodes_end(); NI != E; ++NI)
83 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
84 E = DAG->allnodes_end(); NI != E; ++NI) {
85 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
88 // If this node has already been processed, stop now.
89 if (NI->getNodeId() != -1) continue;
91 SUnit *NodeSUnit = NewSUnit(NI);
93 // See if anything is flagged to this node, if so, add them to flagged
94 // nodes. Nodes can have at most one flag input and one flag output. Flags
95 // are required the be the last operand and result of a node.
97 // Scan up to find flagged preds.
99 if (N->getNumOperands() &&
100 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
102 N = N->getOperand(N->getNumOperands()-1).getNode();
103 assert(N->getNodeId() == -1 && "Node already inserted!");
104 N->setNodeId(NodeSUnit->NodeNum);
105 } while (N->getNumOperands() &&
106 N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag);
109 // Scan down to find any flagged succs.
111 while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
112 SDValue FlagVal(N, N->getNumValues()-1);
114 // There are either zero or one users of the Flag result.
115 bool HasFlagUse = false;
116 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
118 if (FlagVal.isOperandOf(*UI)) {
120 assert(N->getNodeId() == -1 && "Node already inserted!");
121 N->setNodeId(NodeSUnit->NodeNum);
125 if (!HasFlagUse) break;
128 // If there are flag operands involved, N is now the bottom-most node
129 // of the sequence of nodes that are flagged together.
131 NodeSUnit->setNode(N);
132 assert(N->getNodeId() == -1 && "Node already inserted!");
133 N->setNodeId(NodeSUnit->NodeNum);
135 ComputeLatency(NodeSUnit);
138 // Pass 2: add the preds, succs, etc.
139 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
140 SUnit *SU = &SUnits[su];
141 SDNode *MainNode = SU->getNode();
143 if (MainNode->isMachineOpcode()) {
144 unsigned Opc = MainNode->getMachineOpcode();
145 const TargetInstrDesc &TID = TII->get(Opc);
146 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
147 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
148 SU->isTwoAddress = true;
152 if (TID.isCommutable())
153 SU->isCommutable = true;
156 // Find all predecessors and successors of the group.
157 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
158 if (N->isMachineOpcode() &&
159 TII->get(N->getMachineOpcode()).getImplicitDefs() &&
160 CountResults(N) > TII->get(N->getMachineOpcode()).getNumDefs())
161 SU->hasPhysRegDefs = true;
163 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
164 SDNode *OpN = N->getOperand(i).getNode();
165 if (isPassiveNode(OpN)) continue; // Not scheduled.
166 SUnit *OpSU = &SUnits[OpN->getNodeId()];
167 assert(OpSU && "Node has no SUnit!");
168 if (OpSU == SU) continue; // In the same group.
170 MVT OpVT = N->getOperand(i).getValueType();
171 assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
172 bool isChain = OpVT == MVT::Other;
174 unsigned PhysReg = 0;
176 // Determine if this is a physical register dependency.
177 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
178 SU->addPred(OpSU, isChain, false, PhysReg, Cost);
184 void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
185 const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
187 // Compute the latency for the node. We use the sum of the latencies for
188 // all nodes flagged together into this SUnit.
189 if (InstrItins.isEmpty()) {
190 // No latency information.
196 bool SawMachineOpcode = false;
197 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
198 if (N->isMachineOpcode()) {
199 SawMachineOpcode = true;
201 InstrItins.getLatency(TII->get(N->getMachineOpcode()).getSchedClass());
204 // Ensure that CopyToReg and similar nodes have a non-zero latency.
205 if (!SawMachineOpcode)
209 /// CountResults - The results of target nodes have register or immediate
210 /// operands first, then an optional chain, and optional flag operands (which do
211 /// not go into the resulting MachineInstr).
212 unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) {
213 unsigned N = Node->getNumValues();
214 while (N && Node->getValueType(N - 1) == MVT::Flag)
216 if (N && Node->getValueType(N - 1) == MVT::Other)
217 --N; // Skip over chain result.
221 /// CountOperands - The inputs to target nodes have any actual inputs first,
222 /// followed by special operands that describe memory references, then an
223 /// optional chain operand, then an optional flag operand. Compute the number
224 /// of actual operands that will go into the resulting MachineInstr.
225 unsigned ScheduleDAGSDNodes::CountOperands(SDNode *Node) {
226 unsigned N = ComputeMemOperandsEnd(Node);
227 while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).getNode()))
228 --N; // Ignore MEMOPERAND nodes
232 /// ComputeMemOperandsEnd - Find the index one past the last MemOperandSDNode
234 unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) {
235 unsigned N = Node->getNumOperands();
236 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
238 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
239 --N; // Ignore chain if it exists.
244 void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
246 SU->getNode()->dump(DAG);
248 cerr << "CROSS RC COPY ";
250 SmallVector<SDNode *, 4> FlaggedNodes;
251 for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode())
252 FlaggedNodes.push_back(N);
253 while (!FlaggedNodes.empty()) {
255 FlaggedNodes.back()->dump(DAG);
257 FlaggedNodes.pop_back();