1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SetVector.h"
16 #include "llvm/ADT/SmallPtrSet.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/DebugInfo.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
40 #define DEBUG_TYPE "legalizedag"
42 //===----------------------------------------------------------------------===//
43 /// This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class SelectionDAGLegalize {
56 const TargetMachine &TM;
57 const TargetLowering &TLI;
60 /// \brief The set of nodes which have already been legalized. We hold a
61 /// reference to it in order to update as necessary on node deletion.
62 SmallPtrSetImpl<SDNode *> &LegalizedNodes;
64 /// \brief A set of all the nodes updated during legalization.
65 SmallSetVector<SDNode *, 16> *UpdatedNodes;
67 EVT getSetCCResultType(EVT VT) const {
68 return TLI.getSetCCResultType(*DAG.getContext(), VT);
71 // Libcall insertion helpers.
74 SelectionDAGLegalize(SelectionDAG &DAG,
75 SmallPtrSetImpl<SDNode *> &LegalizedNodes,
76 SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
77 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
78 LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
80 /// \brief Legalizes the given operation.
81 void LegalizeOp(SDNode *Node);
84 SDValue OptimizeFloatStore(StoreSDNode *ST);
86 void LegalizeLoadOps(SDNode *Node);
87 void LegalizeStoreOps(SDNode *Node);
89 /// Some targets cannot handle a variable
90 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
91 /// is necessary to spill the vector being inserted into to memory, perform
92 /// the insert there, and then read the result back.
93 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
94 SDValue Idx, SDLoc dl);
95 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
96 SDValue Idx, SDLoc dl);
98 /// Return a vector shuffle operation which
99 /// performs the same shuffe in terms of order or result bytes, but on a type
100 /// whose vector element type is narrower than the original shuffle type.
101 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
102 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
103 SDValue N1, SDValue N2,
104 ArrayRef<int> Mask) const;
106 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
107 bool &NeedInvert, SDLoc dl);
109 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
110 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
111 unsigned NumOps, bool isSigned, SDLoc dl);
113 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
114 SDNode *Node, bool isSigned);
115 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
116 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
117 RTLIB::Libcall Call_F128,
118 RTLIB::Libcall Call_PPCF128);
119 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
120 RTLIB::Libcall Call_I8,
121 RTLIB::Libcall Call_I16,
122 RTLIB::Libcall Call_I32,
123 RTLIB::Libcall Call_I64,
124 RTLIB::Libcall Call_I128);
125 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
126 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
128 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
129 SDValue ExpandBUILD_VECTOR(SDNode *Node);
130 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
131 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
132 SmallVectorImpl<SDValue> &Results);
133 SDValue ExpandFCOPYSIGN(SDNode *Node);
134 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
136 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
138 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
141 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
142 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
144 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
145 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
146 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
148 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
150 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
152 void ExpandNode(SDNode *Node);
153 void PromoteNode(SDNode *Node);
156 // Node replacement helpers
157 void ReplacedNode(SDNode *N) {
158 LegalizedNodes.erase(N);
160 UpdatedNodes->insert(N);
162 void ReplaceNode(SDNode *Old, SDNode *New) {
163 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
164 dbgs() << " with: "; New->dump(&DAG));
166 assert(Old->getNumValues() == New->getNumValues() &&
167 "Replacing one node with another that produces a different number "
169 DAG.ReplaceAllUsesWith(Old, New);
170 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i)
171 DAG.TransferDbgValues(SDValue(Old, i), SDValue(New, i));
173 UpdatedNodes->insert(New);
176 void ReplaceNode(SDValue Old, SDValue New) {
177 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
178 dbgs() << " with: "; New->dump(&DAG));
180 DAG.ReplaceAllUsesWith(Old, New);
181 DAG.TransferDbgValues(Old, New);
183 UpdatedNodes->insert(New.getNode());
184 ReplacedNode(Old.getNode());
186 void ReplaceNode(SDNode *Old, const SDValue *New) {
187 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
189 DAG.ReplaceAllUsesWith(Old, New);
190 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
191 DEBUG(dbgs() << (i == 0 ? " with: "
194 DAG.TransferDbgValues(SDValue(Old, i), New[i]);
196 UpdatedNodes->insert(New[i].getNode());
203 /// Return a vector shuffle operation which
204 /// performs the same shuffe in terms of order or result bytes, but on a type
205 /// whose vector element type is narrower than the original shuffle type.
206 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
208 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
209 SDValue N1, SDValue N2,
210 ArrayRef<int> Mask) const {
211 unsigned NumMaskElts = VT.getVectorNumElements();
212 unsigned NumDestElts = NVT.getVectorNumElements();
213 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
215 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
217 if (NumEltsGrowth == 1)
218 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
220 SmallVector<int, 8> NewMask;
221 for (unsigned i = 0; i != NumMaskElts; ++i) {
223 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
225 NewMask.push_back(-1);
227 NewMask.push_back(Idx * NumEltsGrowth + j);
230 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
231 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
232 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
235 /// Expands the ConstantFP node to an integer constant or
236 /// a load from the constant pool.
238 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
242 // If a FP immediate is precise when represented as a float and if the
243 // target can do an extending load from float to double, we put it into
244 // the constant pool as a float, even if it's is statically typed as a
245 // double. This shrinks FP constants and canonicalizes them for targets where
246 // an FP extending load is the same cost as a normal load (such as on the x87
247 // fp stack or PPC FP unit).
248 EVT VT = CFP->getValueType(0);
249 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
251 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
252 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
253 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
258 while (SVT != MVT::f32 && SVT != MVT::f16) {
259 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
260 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
261 // Only do this if the target has a native EXTLOAD instruction from
263 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
264 TLI.ShouldShrinkFPConstant(OrigVT)) {
265 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
266 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
272 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
273 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
276 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
278 CPIdx, MachinePointerInfo::getConstantPool(),
279 VT, false, false, false, Alignment);
283 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
284 MachinePointerInfo::getConstantPool(), false, false, false,
289 /// Expands an unaligned store to 2 half-size stores.
290 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
291 const TargetLowering &TLI,
292 SelectionDAGLegalize *DAGLegalize) {
293 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
294 "unaligned indexed stores not implemented!");
295 SDValue Chain = ST->getChain();
296 SDValue Ptr = ST->getBasePtr();
297 SDValue Val = ST->getValue();
298 EVT VT = Val.getValueType();
299 int Alignment = ST->getAlignment();
300 unsigned AS = ST->getAddressSpace();
303 if (ST->getMemoryVT().isFloatingPoint() ||
304 ST->getMemoryVT().isVector()) {
305 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
306 if (TLI.isTypeLegal(intVT)) {
307 // Expand to a bitconvert of the value to the integer type of the
308 // same size, then a (misaligned) int store.
309 // FIXME: Does not handle truncating floating point stores!
310 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
311 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
312 ST->isVolatile(), ST->isNonTemporal(), Alignment);
313 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
316 // Do a (aligned) store to a stack slot, then copy from the stack slot
317 // to the final destination using (unaligned) integer loads and stores.
318 EVT StoredVT = ST->getMemoryVT();
320 TLI.getRegisterType(*DAG.getContext(),
321 EVT::getIntegerVT(*DAG.getContext(),
322 StoredVT.getSizeInBits()));
323 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
324 unsigned RegBytes = RegVT.getSizeInBits() / 8;
325 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
327 // Make sure the stack slot is also aligned for the register type.
328 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
330 // Perform the original store, only redirected to the stack slot.
331 SDValue Store = DAG.getTruncStore(Chain, dl,
332 Val, StackPtr, MachinePointerInfo(),
333 StoredVT, false, false, 0);
334 SDValue Increment = DAG.getConstant(RegBytes, dl, TLI.getPointerTy(AS));
335 SmallVector<SDValue, 8> Stores;
338 // Do all but one copies using the full register width.
339 for (unsigned i = 1; i < NumRegs; i++) {
340 // Load one integer register's worth from the stack slot.
341 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
342 MachinePointerInfo(),
343 false, false, false, 0);
344 // Store it to the final location. Remember the store.
345 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
346 ST->getPointerInfo().getWithOffset(Offset),
347 ST->isVolatile(), ST->isNonTemporal(),
348 MinAlign(ST->getAlignment(), Offset)));
349 // Increment the pointers.
351 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
353 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
356 // The last store may be partial. Do a truncating store. On big-endian
357 // machines this requires an extending load from the stack slot to ensure
358 // that the bits are in the right place.
359 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
360 8 * (StoredBytes - Offset));
362 // Load from the stack slot.
363 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
364 MachinePointerInfo(),
365 MemVT, false, false, false, 0);
367 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
369 .getWithOffset(Offset),
370 MemVT, ST->isVolatile(),
372 MinAlign(ST->getAlignment(), Offset),
374 // The order of the stores doesn't matter - say it with a TokenFactor.
375 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
376 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
379 assert(ST->getMemoryVT().isInteger() &&
380 !ST->getMemoryVT().isVector() &&
381 "Unaligned store of unknown type.");
382 // Get the half-size VT
383 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
384 int NumBits = NewStoredVT.getSizeInBits();
385 int IncrementSize = NumBits / 8;
387 // Divide the stored value in two parts.
388 SDValue ShiftAmount = DAG.getConstant(NumBits, dl,
389 TLI.getShiftAmountTy(Val.getValueType()));
391 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
393 // Store the two parts
394 SDValue Store1, Store2;
395 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
396 ST->getPointerInfo(), NewStoredVT,
397 ST->isVolatile(), ST->isNonTemporal(), Alignment);
399 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
400 DAG.getConstant(IncrementSize, dl, TLI.getPointerTy(AS)));
401 Alignment = MinAlign(Alignment, IncrementSize);
402 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
403 ST->getPointerInfo().getWithOffset(IncrementSize),
404 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
405 Alignment, ST->getAAInfo());
408 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
409 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
412 /// Expands an unaligned load to 2 half-size loads.
414 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
415 const TargetLowering &TLI,
416 SDValue &ValResult, SDValue &ChainResult) {
417 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
418 "unaligned indexed loads not implemented!");
419 SDValue Chain = LD->getChain();
420 SDValue Ptr = LD->getBasePtr();
421 EVT VT = LD->getValueType(0);
422 EVT LoadedVT = LD->getMemoryVT();
424 if (VT.isFloatingPoint() || VT.isVector()) {
425 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
426 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
427 // Expand to a (misaligned) integer load of the same size,
428 // then bitconvert to floating point or vector.
429 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
430 LD->getMemOperand());
431 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
433 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
434 ISD::ANY_EXTEND, dl, VT, Result);
441 // Copy the value to a (aligned) stack slot using (unaligned) integer
442 // loads and stores, then do a (aligned) load from the stack slot.
443 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
444 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
445 unsigned RegBytes = RegVT.getSizeInBits() / 8;
446 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
448 // Make sure the stack slot is also aligned for the register type.
449 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
451 SDValue Increment = DAG.getConstant(RegBytes, dl, TLI.getPointerTy());
452 SmallVector<SDValue, 8> Stores;
453 SDValue StackPtr = StackBase;
456 // Do all but one copies using the full register width.
457 for (unsigned i = 1; i < NumRegs; i++) {
458 // Load one integer register's worth from the original location.
459 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
460 LD->getPointerInfo().getWithOffset(Offset),
461 LD->isVolatile(), LD->isNonTemporal(),
463 MinAlign(LD->getAlignment(), Offset),
465 // Follow the load with a store to the stack slot. Remember the store.
466 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
467 MachinePointerInfo(), false, false, 0));
468 // Increment the pointers.
470 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
471 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
475 // The last copy may be partial. Do an extending load.
476 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
477 8 * (LoadedBytes - Offset));
478 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
479 LD->getPointerInfo().getWithOffset(Offset),
480 MemVT, LD->isVolatile(),
483 MinAlign(LD->getAlignment(), Offset),
485 // Follow the load with a store to the stack slot. Remember the store.
486 // On big-endian machines this requires a truncating store to ensure
487 // that the bits end up in the right place.
488 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
489 MachinePointerInfo(), MemVT,
492 // The order of the stores doesn't matter - say it with a TokenFactor.
493 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
495 // Finally, perform the original load only redirected to the stack slot.
496 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
497 MachinePointerInfo(), LoadedVT, false,false, false,
500 // Callers expect a MERGE_VALUES node.
505 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
506 "Unaligned load of unsupported type.");
508 // Compute the new VT that is half the size of the old one. This is an
510 unsigned NumBits = LoadedVT.getSizeInBits();
512 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
515 unsigned Alignment = LD->getAlignment();
516 unsigned IncrementSize = NumBits / 8;
517 ISD::LoadExtType HiExtType = LD->getExtensionType();
519 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
520 if (HiExtType == ISD::NON_EXTLOAD)
521 HiExtType = ISD::ZEXTLOAD;
523 // Load the value in two parts
525 if (TLI.isLittleEndian()) {
526 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
527 NewLoadedVT, LD->isVolatile(),
528 LD->isNonTemporal(), LD->isInvariant(), Alignment,
530 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
531 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
532 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
533 LD->getPointerInfo().getWithOffset(IncrementSize),
534 NewLoadedVT, LD->isVolatile(),
535 LD->isNonTemporal(),LD->isInvariant(),
536 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
538 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
539 NewLoadedVT, LD->isVolatile(),
540 LD->isNonTemporal(), LD->isInvariant(), Alignment,
542 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
543 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
544 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
545 LD->getPointerInfo().getWithOffset(IncrementSize),
546 NewLoadedVT, LD->isVolatile(),
547 LD->isNonTemporal(), LD->isInvariant(),
548 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
551 // aggregate the two parts
552 SDValue ShiftAmount = DAG.getConstant(NumBits, dl,
553 TLI.getShiftAmountTy(Hi.getValueType()));
554 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
555 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
557 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
564 /// Some target cannot handle a variable insertion index for the
565 /// INSERT_VECTOR_ELT instruction. In this case, it
566 /// is necessary to spill the vector being inserted into to memory, perform
567 /// the insert there, and then read the result back.
568 SDValue SelectionDAGLegalize::
569 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
575 // If the target doesn't support this, we have to spill the input vector
576 // to a temporary stack slot, update the element, then reload it. This is
577 // badness. We could also load the value into a vector register (either
578 // with a "move to register" or "extload into register" instruction, then
579 // permute it into place, if the idx is a constant and if the idx is
580 // supported by the target.
581 EVT VT = Tmp1.getValueType();
582 EVT EltVT = VT.getVectorElementType();
583 EVT IdxVT = Tmp3.getValueType();
584 EVT PtrVT = TLI.getPointerTy();
585 SDValue StackPtr = DAG.CreateStackTemporary(VT);
587 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
590 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
591 MachinePointerInfo::getFixedStack(SPFI),
594 // Truncate or zero extend offset to target pointer type.
595 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
596 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
597 // Add the offset to the index.
598 unsigned EltSize = EltVT.getSizeInBits()/8;
599 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,
600 DAG.getConstant(EltSize, dl, IdxVT));
601 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
602 // Store the scalar value.
603 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
605 // Load the updated vector.
606 return DAG.getLoad(VT, dl, Ch, StackPtr,
607 MachinePointerInfo::getFixedStack(SPFI), false, false,
612 SDValue SelectionDAGLegalize::
613 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
614 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
615 // SCALAR_TO_VECTOR requires that the type of the value being inserted
616 // match the element type of the vector being created, except for
617 // integers in which case the inserted value can be over width.
618 EVT EltVT = Vec.getValueType().getVectorElementType();
619 if (Val.getValueType() == EltVT ||
620 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
621 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
622 Vec.getValueType(), Val);
624 unsigned NumElts = Vec.getValueType().getVectorNumElements();
625 // We generate a shuffle of InVec and ScVec, so the shuffle mask
626 // should be 0,1,2,3,4,5... with the appropriate element replaced with
628 SmallVector<int, 8> ShufOps;
629 for (unsigned i = 0; i != NumElts; ++i)
630 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
632 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
636 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
639 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
640 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
641 // FIXME: We shouldn't do this for TargetConstantFP's.
642 // FIXME: move this to the DAG Combiner! Note that we can't regress due
643 // to phase ordering between legalized code and the dag combiner. This
644 // probably means that we need to integrate dag combiner and legalizer
646 // We generally can't do this one for long doubles.
647 SDValue Chain = ST->getChain();
648 SDValue Ptr = ST->getBasePtr();
649 unsigned Alignment = ST->getAlignment();
650 bool isVolatile = ST->isVolatile();
651 bool isNonTemporal = ST->isNonTemporal();
652 AAMDNodes AAInfo = ST->getAAInfo();
654 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
655 if (CFP->getValueType(0) == MVT::f32 &&
656 TLI.isTypeLegal(MVT::i32)) {
657 SDValue Con = DAG.getConstant(CFP->getValueAPF().
658 bitcastToAPInt().zextOrTrunc(32),
659 SDLoc(CFP), MVT::i32);
660 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
661 isVolatile, isNonTemporal, Alignment, AAInfo);
664 if (CFP->getValueType(0) == MVT::f64) {
665 // If this target supports 64-bit registers, do a single 64-bit store.
666 if (TLI.isTypeLegal(MVT::i64)) {
667 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
668 zextOrTrunc(64), SDLoc(CFP), MVT::i64);
669 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
670 isVolatile, isNonTemporal, Alignment, AAInfo);
673 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
674 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
675 // stores. If the target supports neither 32- nor 64-bits, this
676 // xform is certainly not worth it.
677 const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
678 SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
679 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
680 if (TLI.isBigEndian()) std::swap(Lo, Hi);
682 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
683 isNonTemporal, Alignment, AAInfo);
684 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
685 DAG.getConstant(4, dl, Ptr.getValueType()));
686 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
687 ST->getPointerInfo().getWithOffset(4),
688 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
691 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
695 return SDValue(nullptr, 0);
698 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
699 StoreSDNode *ST = cast<StoreSDNode>(Node);
700 SDValue Chain = ST->getChain();
701 SDValue Ptr = ST->getBasePtr();
704 unsigned Alignment = ST->getAlignment();
705 bool isVolatile = ST->isVolatile();
706 bool isNonTemporal = ST->isNonTemporal();
707 AAMDNodes AAInfo = ST->getAAInfo();
709 if (!ST->isTruncatingStore()) {
710 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
711 ReplaceNode(ST, OptStore);
716 SDValue Value = ST->getValue();
717 MVT VT = Value.getSimpleValueType();
718 switch (TLI.getOperationAction(ISD::STORE, VT)) {
719 default: llvm_unreachable("This action is not supported yet!");
720 case TargetLowering::Legal: {
721 // If this is an unaligned store and the target doesn't support it,
723 unsigned AS = ST->getAddressSpace();
724 unsigned Align = ST->getAlignment();
725 if (!TLI.allowsMisalignedMemoryAccesses(ST->getMemoryVT(), AS, Align)) {
726 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
727 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
728 if (Align < ABIAlignment)
729 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
733 case TargetLowering::Custom: {
734 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
735 if (Res && Res != SDValue(Node, 0))
736 ReplaceNode(SDValue(Node, 0), Res);
739 case TargetLowering::Promote: {
740 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
741 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
742 "Can only promote stores to same size type");
743 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
745 DAG.getStore(Chain, dl, Value, Ptr,
746 ST->getPointerInfo(), isVolatile,
747 isNonTemporal, Alignment, AAInfo);
748 ReplaceNode(SDValue(Node, 0), Result);
755 SDValue Value = ST->getValue();
757 EVT StVT = ST->getMemoryVT();
758 unsigned StWidth = StVT.getSizeInBits();
760 if (StWidth != StVT.getStoreSizeInBits()) {
761 // Promote to a byte-sized store with upper bits zero if not
762 // storing an integral number of bytes. For example, promote
763 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
764 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
765 StVT.getStoreSizeInBits());
766 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
768 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
769 NVT, isVolatile, isNonTemporal, Alignment, AAInfo);
770 ReplaceNode(SDValue(Node, 0), Result);
771 } else if (StWidth & (StWidth - 1)) {
772 // If not storing a power-of-2 number of bits, expand as two stores.
773 assert(!StVT.isVector() && "Unsupported truncstore!");
774 unsigned RoundWidth = 1 << Log2_32(StWidth);
775 assert(RoundWidth < StWidth);
776 unsigned ExtraWidth = StWidth - RoundWidth;
777 assert(ExtraWidth < RoundWidth);
778 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
779 "Store size not an integral number of bytes!");
780 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
781 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
783 unsigned IncrementSize;
785 if (TLI.isLittleEndian()) {
786 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
787 // Store the bottom RoundWidth bits.
788 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
790 isVolatile, isNonTemporal, Alignment,
793 // Store the remaining ExtraWidth bits.
794 IncrementSize = RoundWidth / 8;
795 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
796 DAG.getConstant(IncrementSize, dl,
797 Ptr.getValueType()));
798 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
799 DAG.getConstant(RoundWidth, dl,
800 TLI.getShiftAmountTy(Value.getValueType())));
801 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
802 ST->getPointerInfo().getWithOffset(IncrementSize),
803 ExtraVT, isVolatile, isNonTemporal,
804 MinAlign(Alignment, IncrementSize), AAInfo);
806 // Big endian - avoid unaligned stores.
807 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
808 // Store the top RoundWidth bits.
809 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
810 DAG.getConstant(ExtraWidth, dl,
811 TLI.getShiftAmountTy(Value.getValueType())));
812 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
813 RoundVT, isVolatile, isNonTemporal, Alignment,
816 // Store the remaining ExtraWidth bits.
817 IncrementSize = RoundWidth / 8;
818 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
819 DAG.getConstant(IncrementSize, dl,
820 Ptr.getValueType()));
821 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
822 ST->getPointerInfo().getWithOffset(IncrementSize),
823 ExtraVT, isVolatile, isNonTemporal,
824 MinAlign(Alignment, IncrementSize), AAInfo);
827 // The order of the stores doesn't matter.
828 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
829 ReplaceNode(SDValue(Node, 0), Result);
831 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
832 StVT.getSimpleVT())) {
833 default: llvm_unreachable("This action is not supported yet!");
834 case TargetLowering::Legal: {
835 unsigned AS = ST->getAddressSpace();
836 unsigned Align = ST->getAlignment();
837 // If this is an unaligned store and the target doesn't support it,
839 if (!TLI.allowsMisalignedMemoryAccesses(ST->getMemoryVT(), AS, Align)) {
840 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
841 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
842 if (Align < ABIAlignment)
843 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
847 case TargetLowering::Custom: {
848 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
849 if (Res && Res != SDValue(Node, 0))
850 ReplaceNode(SDValue(Node, 0), Res);
853 case TargetLowering::Expand:
854 assert(!StVT.isVector() &&
855 "Vector Stores are handled in LegalizeVectorOps");
857 // TRUNCSTORE:i16 i32 -> STORE i16
858 assert(TLI.isTypeLegal(StVT) &&
859 "Do not know how to expand this store!");
860 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
862 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
863 isVolatile, isNonTemporal, Alignment, AAInfo);
864 ReplaceNode(SDValue(Node, 0), Result);
871 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
872 LoadSDNode *LD = cast<LoadSDNode>(Node);
873 SDValue Chain = LD->getChain(); // The chain.
874 SDValue Ptr = LD->getBasePtr(); // The base pointer.
875 SDValue Value; // The value returned by the load op.
878 ISD::LoadExtType ExtType = LD->getExtensionType();
879 if (ExtType == ISD::NON_EXTLOAD) {
880 MVT VT = Node->getSimpleValueType(0);
881 SDValue RVal = SDValue(Node, 0);
882 SDValue RChain = SDValue(Node, 1);
884 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
885 default: llvm_unreachable("This action is not supported yet!");
886 case TargetLowering::Legal: {
887 unsigned AS = LD->getAddressSpace();
888 unsigned Align = LD->getAlignment();
889 // If this is an unaligned load and the target doesn't support it,
891 if (!TLI.allowsMisalignedMemoryAccesses(LD->getMemoryVT(), AS, Align)) {
892 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
893 unsigned ABIAlignment =
894 TLI.getDataLayout()->getABITypeAlignment(Ty);
895 if (Align < ABIAlignment){
896 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
901 case TargetLowering::Custom: {
902 SDValue Res = TLI.LowerOperation(RVal, DAG);
905 RChain = Res.getValue(1);
909 case TargetLowering::Promote: {
910 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
911 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
912 "Can only promote loads to same size type");
914 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
915 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
916 RChain = Res.getValue(1);
920 if (RChain.getNode() != Node) {
921 assert(RVal.getNode() != Node && "Load must be completely replaced");
922 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
923 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
925 UpdatedNodes->insert(RVal.getNode());
926 UpdatedNodes->insert(RChain.getNode());
933 EVT SrcVT = LD->getMemoryVT();
934 unsigned SrcWidth = SrcVT.getSizeInBits();
935 unsigned Alignment = LD->getAlignment();
936 bool isVolatile = LD->isVolatile();
937 bool isNonTemporal = LD->isNonTemporal();
938 bool isInvariant = LD->isInvariant();
939 AAMDNodes AAInfo = LD->getAAInfo();
941 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
942 // Some targets pretend to have an i1 loading operation, and actually
943 // load an i8. This trick is correct for ZEXTLOAD because the top 7
944 // bits are guaranteed to be zero; it helps the optimizers understand
945 // that these bits are zero. It is also useful for EXTLOAD, since it
946 // tells the optimizers that those bits are undefined. It would be
947 // nice to have an effective generic way of getting these benefits...
948 // Until such a way is found, don't insist on promoting i1 here.
950 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
951 TargetLowering::Promote)) {
952 // Promote to a byte-sized load if not loading an integral number of
953 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
954 unsigned NewWidth = SrcVT.getStoreSizeInBits();
955 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
958 // The extra bits are guaranteed to be zero, since we stored them that
959 // way. A zext load from NVT thus automatically gives zext from SrcVT.
961 ISD::LoadExtType NewExtType =
962 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
965 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
966 Chain, Ptr, LD->getPointerInfo(),
967 NVT, isVolatile, isNonTemporal, isInvariant, Alignment,
970 Ch = Result.getValue(1); // The chain.
972 if (ExtType == ISD::SEXTLOAD)
973 // Having the top bits zero doesn't help when sign extending.
974 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
975 Result.getValueType(),
976 Result, DAG.getValueType(SrcVT));
977 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
978 // All the top bits are guaranteed to be zero - inform the optimizers.
979 Result = DAG.getNode(ISD::AssertZext, dl,
980 Result.getValueType(), Result,
981 DAG.getValueType(SrcVT));
985 } else if (SrcWidth & (SrcWidth - 1)) {
986 // If not loading a power-of-2 number of bits, expand as two loads.
987 assert(!SrcVT.isVector() && "Unsupported extload!");
988 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
989 assert(RoundWidth < SrcWidth);
990 unsigned ExtraWidth = SrcWidth - RoundWidth;
991 assert(ExtraWidth < RoundWidth);
992 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
993 "Load size not an integral number of bytes!");
994 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
995 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
997 unsigned IncrementSize;
999 if (TLI.isLittleEndian()) {
1000 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1001 // Load the bottom RoundWidth bits.
1002 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1004 LD->getPointerInfo(), RoundVT, isVolatile,
1005 isNonTemporal, isInvariant, Alignment, AAInfo);
1007 // Load the remaining ExtraWidth bits.
1008 IncrementSize = RoundWidth / 8;
1009 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1010 DAG.getConstant(IncrementSize, dl,
1011 Ptr.getValueType()));
1012 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1013 LD->getPointerInfo().getWithOffset(IncrementSize),
1014 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1015 MinAlign(Alignment, IncrementSize), AAInfo);
1017 // Build a factor node to remember that this load is independent of
1019 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1022 // Move the top bits to the right place.
1023 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1024 DAG.getConstant(RoundWidth, dl,
1025 TLI.getShiftAmountTy(Hi.getValueType())));
1027 // Join the hi and lo parts.
1028 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1030 // Big endian - avoid unaligned loads.
1031 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1032 // Load the top RoundWidth bits.
1033 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1034 LD->getPointerInfo(), RoundVT, isVolatile,
1035 isNonTemporal, isInvariant, Alignment, AAInfo);
1037 // Load the remaining ExtraWidth bits.
1038 IncrementSize = RoundWidth / 8;
1039 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1040 DAG.getConstant(IncrementSize, dl,
1041 Ptr.getValueType()));
1042 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1043 dl, Node->getValueType(0), Chain, Ptr,
1044 LD->getPointerInfo().getWithOffset(IncrementSize),
1045 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1046 MinAlign(Alignment, IncrementSize), AAInfo);
1048 // Build a factor node to remember that this load is independent of
1050 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1053 // Move the top bits to the right place.
1054 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1055 DAG.getConstant(ExtraWidth, dl,
1056 TLI.getShiftAmountTy(Hi.getValueType())));
1058 // Join the hi and lo parts.
1059 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1064 bool isCustom = false;
1065 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
1066 SrcVT.getSimpleVT())) {
1067 default: llvm_unreachable("This action is not supported yet!");
1068 case TargetLowering::Custom:
1071 case TargetLowering::Legal: {
1072 Value = SDValue(Node, 0);
1073 Chain = SDValue(Node, 1);
1076 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1077 if (Res.getNode()) {
1079 Chain = Res.getValue(1);
1082 // If this is an unaligned load and the target doesn't support
1084 EVT MemVT = LD->getMemoryVT();
1085 unsigned AS = LD->getAddressSpace();
1086 unsigned Align = LD->getAlignment();
1087 if (!TLI.allowsMisalignedMemoryAccesses(MemVT, AS, Align)) {
1088 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1089 unsigned ABIAlignment = TLI.getDataLayout()->getABITypeAlignment(Ty);
1090 if (Align < ABIAlignment){
1091 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, Value, Chain);
1097 case TargetLowering::Expand:
1098 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, Node->getValueType(0), SrcVT)) {
1099 // If the source type is not legal, see if there is a legal extload to
1100 // an intermediate type that we can then extend further.
1101 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
1102 if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
1103 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
1104 // If we are loading a legal type, this is a non-extload followed by a
1106 ISD::LoadExtType MidExtType =
1107 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
1109 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
1110 SrcVT, LD->getMemOperand());
1112 ISD::getExtForLoadExtType(SrcVT.isFloatingPoint(), ExtType);
1113 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1114 Chain = Load.getValue(1);
1119 assert(!SrcVT.isVector() &&
1120 "Vector Loads are handled in LegalizeVectorOps");
1122 // FIXME: This does not work for vectors on most targets. Sign-
1123 // and zero-extend operations are currently folded into extending
1124 // loads, whether they are legal or not, and then we end up here
1125 // without any support for legalizing them.
1126 assert(ExtType != ISD::EXTLOAD &&
1127 "EXTLOAD should always be supported!");
1128 // Turn the unsupported load into an EXTLOAD followed by an
1129 // explicit zero/sign extend inreg.
1130 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1131 Node->getValueType(0),
1133 LD->getMemOperand());
1135 if (ExtType == ISD::SEXTLOAD)
1136 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1137 Result.getValueType(),
1138 Result, DAG.getValueType(SrcVT));
1140 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1142 Chain = Result.getValue(1);
1147 // Since loads produce two values, make sure to remember that we legalized
1149 if (Chain.getNode() != Node) {
1150 assert(Value.getNode() != Node && "Load must be completely replaced");
1151 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1152 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1154 UpdatedNodes->insert(Value.getNode());
1155 UpdatedNodes->insert(Chain.getNode());
1161 /// Return a legal replacement for the given operation, with all legal operands.
1162 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1163 DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
1165 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1168 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1169 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1170 TargetLowering::TypeLegal &&
1171 "Unexpected illegal type!");
1173 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1174 assert((TLI.getTypeAction(*DAG.getContext(),
1175 Node->getOperand(i).getValueType()) ==
1176 TargetLowering::TypeLegal ||
1177 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1178 "Unexpected illegal type!");
1180 // Figure out the correct action; the way to query this varies by opcode
1181 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1182 bool SimpleFinishLegalizing = true;
1183 switch (Node->getOpcode()) {
1184 case ISD::INTRINSIC_W_CHAIN:
1185 case ISD::INTRINSIC_WO_CHAIN:
1186 case ISD::INTRINSIC_VOID:
1187 case ISD::STACKSAVE:
1188 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1191 Action = TLI.getOperationAction(Node->getOpcode(),
1192 Node->getValueType(0));
1193 if (Action != TargetLowering::Promote)
1194 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1196 case ISD::FP_TO_FP16:
1197 case ISD::SINT_TO_FP:
1198 case ISD::UINT_TO_FP:
1199 case ISD::EXTRACT_VECTOR_ELT:
1200 Action = TLI.getOperationAction(Node->getOpcode(),
1201 Node->getOperand(0).getValueType());
1203 case ISD::FP_ROUND_INREG:
1204 case ISD::SIGN_EXTEND_INREG: {
1205 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1206 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1209 case ISD::ATOMIC_STORE: {
1210 Action = TLI.getOperationAction(Node->getOpcode(),
1211 Node->getOperand(2).getValueType());
1214 case ISD::SELECT_CC:
1217 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1218 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1219 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1220 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1221 ISD::CondCode CCCode =
1222 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1223 Action = TLI.getCondCodeAction(CCCode, OpVT);
1224 if (Action == TargetLowering::Legal) {
1225 if (Node->getOpcode() == ISD::SELECT_CC)
1226 Action = TLI.getOperationAction(Node->getOpcode(),
1227 Node->getValueType(0));
1229 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1235 // FIXME: Model these properly. LOAD and STORE are complicated, and
1236 // STORE expects the unlegalized operand in some cases.
1237 SimpleFinishLegalizing = false;
1239 case ISD::CALLSEQ_START:
1240 case ISD::CALLSEQ_END:
1241 // FIXME: This shouldn't be necessary. These nodes have special properties
1242 // dealing with the recursive nature of legalization. Removing this
1243 // special case should be done as part of making LegalizeDAG non-recursive.
1244 SimpleFinishLegalizing = false;
1246 case ISD::EXTRACT_ELEMENT:
1247 case ISD::FLT_ROUNDS_:
1255 case ISD::MERGE_VALUES:
1256 case ISD::EH_RETURN:
1257 case ISD::FRAME_TO_ARGS_OFFSET:
1258 case ISD::EH_SJLJ_SETJMP:
1259 case ISD::EH_SJLJ_LONGJMP:
1260 // These operations lie about being legal: when they claim to be legal,
1261 // they should actually be expanded.
1262 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1263 if (Action == TargetLowering::Legal)
1264 Action = TargetLowering::Expand;
1266 case ISD::INIT_TRAMPOLINE:
1267 case ISD::ADJUST_TRAMPOLINE:
1268 case ISD::FRAMEADDR:
1269 case ISD::RETURNADDR:
1270 // These operations lie about being legal: when they claim to be legal,
1271 // they should actually be custom-lowered.
1272 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1273 if (Action == TargetLowering::Legal)
1274 Action = TargetLowering::Custom;
1276 case ISD::READ_REGISTER:
1277 case ISD::WRITE_REGISTER:
1278 // Named register is legal in the DAG, but blocked by register name
1279 // selection if not implemented by target (to chose the correct register)
1280 // They'll be converted to Copy(To/From)Reg.
1281 Action = TargetLowering::Legal;
1283 case ISD::DEBUGTRAP:
1284 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1285 if (Action == TargetLowering::Expand) {
1286 // replace ISD::DEBUGTRAP with ISD::TRAP
1288 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1289 Node->getOperand(0));
1290 ReplaceNode(Node, NewVal.getNode());
1291 LegalizeOp(NewVal.getNode());
1297 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1298 Action = TargetLowering::Legal;
1300 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1305 if (SimpleFinishLegalizing) {
1306 SDNode *NewNode = Node;
1307 switch (Node->getOpcode()) {
1314 // Legalizing shifts/rotates requires adjusting the shift amount
1315 // to the appropriate width.
1316 if (!Node->getOperand(1).getValueType().isVector()) {
1318 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1319 Node->getOperand(1));
1320 HandleSDNode Handle(SAO);
1321 LegalizeOp(SAO.getNode());
1322 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1326 case ISD::SRL_PARTS:
1327 case ISD::SRA_PARTS:
1328 case ISD::SHL_PARTS:
1329 // Legalizing shifts/rotates requires adjusting the shift amount
1330 // to the appropriate width.
1331 if (!Node->getOperand(2).getValueType().isVector()) {
1333 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1334 Node->getOperand(2));
1335 HandleSDNode Handle(SAO);
1336 LegalizeOp(SAO.getNode());
1337 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1338 Node->getOperand(1),
1344 if (NewNode != Node) {
1345 ReplaceNode(Node, NewNode);
1349 case TargetLowering::Legal:
1351 case TargetLowering::Custom: {
1352 // FIXME: The handling for custom lowering with multiple results is
1354 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1355 if (Res.getNode()) {
1356 if (!(Res.getNode() != Node || Res.getResNo() != 0))
1359 if (Node->getNumValues() == 1) {
1360 // We can just directly replace this node with the lowered value.
1361 ReplaceNode(SDValue(Node, 0), Res);
1365 SmallVector<SDValue, 8> ResultVals;
1366 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1367 ResultVals.push_back(Res.getValue(i));
1368 ReplaceNode(Node, ResultVals.data());
1373 case TargetLowering::Expand:
1376 case TargetLowering::Promote:
1382 switch (Node->getOpcode()) {
1389 llvm_unreachable("Do not know how to legalize this operator!");
1391 case ISD::CALLSEQ_START:
1392 case ISD::CALLSEQ_END:
1395 return LegalizeLoadOps(Node);
1398 return LegalizeStoreOps(Node);
1403 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1404 SDValue Vec = Op.getOperand(0);
1405 SDValue Idx = Op.getOperand(1);
1408 // Before we generate a new store to a temporary stack slot, see if there is
1409 // already one that we can use. There often is because when we scalarize
1410 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1411 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1412 // the vector. If all are expanded here, we don't want one store per vector
1414 SDValue StackPtr, Ch;
1415 for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1416 UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1418 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1419 if (ST->isIndexed() || ST->isTruncatingStore() ||
1420 ST->getValue() != Vec)
1423 // Make sure that nothing else could have stored into the destination of
1425 if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1428 StackPtr = ST->getBasePtr();
1429 Ch = SDValue(ST, 0);
1434 if (!Ch.getNode()) {
1435 // Store the value to a temporary stack slot, then LOAD the returned part.
1436 StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1437 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1438 MachinePointerInfo(), false, false, 0);
1441 // Add the offset to the index.
1443 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1444 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1445 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1447 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1448 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1452 if (Op.getValueType().isVector())
1453 NewLoad = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,
1454 MachinePointerInfo(), false, false, false, 0);
1456 NewLoad = DAG.getExtLoad(
1457 ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, MachinePointerInfo(),
1458 Vec.getValueType().getVectorElementType(), false, false, false, 0);
1460 // Replace the chain going out of the store, by the one out of the load.
1461 DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1463 // We introduced a cycle though, so update the loads operands, making sure
1464 // to use the original store's chain as an incoming chain.
1465 SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1467 NewLoadOperands[0] = Ch;
1469 SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1473 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1474 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1476 SDValue Vec = Op.getOperand(0);
1477 SDValue Part = Op.getOperand(1);
1478 SDValue Idx = Op.getOperand(2);
1481 // Store the value to a temporary stack slot, then LOAD the returned part.
1483 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1484 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1485 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1487 // First store the whole vector.
1488 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1491 // Then store the inserted part.
1493 // Add the offset to the index.
1495 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1497 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1498 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1499 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1501 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1504 // Store the subvector.
1505 Ch = DAG.getStore(Ch, dl, Part, SubStackPtr,
1506 MachinePointerInfo(), false, false, 0);
1508 // Finally, load the updated vector.
1509 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1510 false, false, false, 0);
1513 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1514 // We can't handle this case efficiently. Allocate a sufficiently
1515 // aligned object on the stack, store each element into it, then load
1516 // the result as a vector.
1517 // Create the stack frame object.
1518 EVT VT = Node->getValueType(0);
1519 EVT EltVT = VT.getVectorElementType();
1521 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1522 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1523 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1525 // Emit a store of each element to the stack slot.
1526 SmallVector<SDValue, 8> Stores;
1527 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1528 // Store (in the right endianness) the elements to memory.
1529 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1530 // Ignore undef elements.
1531 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1533 unsigned Offset = TypeByteSize*i;
1535 SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1536 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1538 // If the destination vector element type is narrower than the source
1539 // element type, only store the bits necessary.
1540 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1541 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1542 Node->getOperand(i), Idx,
1543 PtrInfo.getWithOffset(Offset),
1544 EltVT, false, false, 0));
1546 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1547 Node->getOperand(i), Idx,
1548 PtrInfo.getWithOffset(Offset),
1553 if (!Stores.empty()) // Not all undef elements?
1554 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1556 StoreChain = DAG.getEntryNode();
1558 // Result is a load from the stack slot.
1559 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1560 false, false, false, 0);
1563 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1565 SDValue Tmp1 = Node->getOperand(0);
1566 SDValue Tmp2 = Node->getOperand(1);
1568 // Get the sign bit of the RHS. First obtain a value that has the same
1569 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1571 EVT FloatVT = Tmp2.getValueType();
1572 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1573 if (TLI.isTypeLegal(IVT)) {
1574 // Convert to an integer with the same sign bit.
1575 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1577 // Store the float to memory, then load the sign part out as an integer.
1578 MVT LoadTy = TLI.getPointerTy();
1579 // First create a temporary that is aligned for both the load and store.
1580 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1581 // Then store the float to it.
1583 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1585 if (TLI.isBigEndian()) {
1586 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1587 // Load out a legal integer with the same sign bit as the float.
1588 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1589 false, false, false, 0);
1590 } else { // Little endian
1591 SDValue LoadPtr = StackPtr;
1592 // The float may be wider than the integer we are going to load. Advance
1593 // the pointer so that the loaded integer will contain the sign bit.
1594 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1595 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1596 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
1597 DAG.getConstant(ByteOffset, dl,
1598 LoadPtr.getValueType()));
1599 // Load a legal integer containing the sign bit.
1600 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1601 false, false, false, 0);
1602 // Move the sign bit to the top bit of the loaded integer.
1603 unsigned BitShift = LoadTy.getSizeInBits() -
1604 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1605 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1607 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1608 DAG.getConstant(BitShift, dl,
1609 TLI.getShiftAmountTy(SignBit.getValueType())));
1612 // Now get the sign bit proper, by seeing whether the value is negative.
1613 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1615 DAG.getConstant(0, dl, SignBit.getValueType()),
1617 // Get the absolute value of the result.
1618 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1619 // Select between the nabs and abs value based on the sign bit of
1621 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1622 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1626 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1627 SmallVectorImpl<SDValue> &Results) {
1628 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1629 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1630 " not tell us which reg is the stack pointer!");
1632 EVT VT = Node->getValueType(0);
1633 SDValue Tmp1 = SDValue(Node, 0);
1634 SDValue Tmp2 = SDValue(Node, 1);
1635 SDValue Tmp3 = Node->getOperand(2);
1636 SDValue Chain = Tmp1.getOperand(0);
1638 // Chain the dynamic stack allocation so that it doesn't modify the stack
1639 // pointer when other instructions are using the stack.
1640 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
1642 SDValue Size = Tmp2.getOperand(1);
1643 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1644 Chain = SP.getValue(1);
1645 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1646 unsigned StackAlign =
1647 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1648 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1649 if (Align > StackAlign)
1650 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1651 DAG.getConstant(-(uint64_t)Align, dl, VT));
1652 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1654 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1655 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1657 Results.push_back(Tmp1);
1658 Results.push_back(Tmp2);
1661 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1664 /// If the SETCC has been legalized using AND / OR, then the legalized node
1665 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1666 /// will be set to false.
1668 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1669 /// then the values of LHS and RHS will be swapped, CC will be set to the
1670 /// new condition, and NeedInvert will be set to false.
1672 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1673 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1674 /// will be set to true. The caller must invert the result of the SETCC with
1675 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1676 /// of a true/false result.
1678 /// \returns true if the SetCC has been legalized, false if it hasn't.
1679 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1680 SDValue &LHS, SDValue &RHS,
1684 MVT OpVT = LHS.getSimpleValueType();
1685 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1687 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1688 default: llvm_unreachable("Unknown condition code action!");
1689 case TargetLowering::Legal:
1692 case TargetLowering::Expand: {
1693 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1694 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1695 std::swap(LHS, RHS);
1696 CC = DAG.getCondCode(InvCC);
1699 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1702 default: llvm_unreachable("Don't know how to expand this condition!");
1704 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1705 == TargetLowering::Legal
1706 && "If SETO is expanded, SETOEQ must be legal!");
1707 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1709 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1710 == TargetLowering::Legal
1711 && "If SETUO is expanded, SETUNE must be legal!");
1712 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1725 // If we are floating point, assign and break, otherwise fall through.
1726 if (!OpVT.isInteger()) {
1727 // We can use the 4th bit to tell if we are the unordered
1728 // or ordered version of the opcode.
1729 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1730 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1731 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1734 // Fallthrough if we are unsigned integer.
1739 // We only support using the inverted operation, which is computed above
1740 // and not a different manner of supporting expanding these cases.
1741 llvm_unreachable("Don't know how to expand this condition!");
1744 // Try inverting the result of the inverse condition.
1745 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1746 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1747 CC = DAG.getCondCode(InvCC);
1751 // If inverting the condition didn't work then we have no means to expand
1753 llvm_unreachable("Don't know how to expand this condition!");
1756 SDValue SetCC1, SetCC2;
1757 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1758 // If we aren't the ordered or unorder operation,
1759 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1760 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1761 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1763 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1764 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1765 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1767 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1776 /// Emit a store/load combination to the stack. This stores
1777 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1778 /// a load from the stack slot to DestVT, extending it if needed.
1779 /// The resultant code need not be legal.
1780 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1784 // Create the stack frame object.
1786 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1787 getTypeForEVT(*DAG.getContext()));
1788 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1790 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1791 int SPFI = StackPtrFI->getIndex();
1792 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1794 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1795 unsigned SlotSize = SlotVT.getSizeInBits();
1796 unsigned DestSize = DestVT.getSizeInBits();
1797 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1798 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1800 // Emit a store to the stack slot. Use a truncstore if the input value is
1801 // later than DestVT.
1804 if (SrcSize > SlotSize)
1805 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1806 PtrInfo, SlotVT, false, false, SrcAlign);
1808 assert(SrcSize == SlotSize && "Invalid store");
1809 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1810 PtrInfo, false, false, SrcAlign);
1813 // Result is a load from the stack slot.
1814 if (SlotSize == DestSize)
1815 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1816 false, false, false, DestAlign);
1818 assert(SlotSize < DestSize && "Unknown extension!");
1819 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1820 PtrInfo, SlotVT, false, false, false, DestAlign);
1823 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1825 // Create a vector sized/aligned stack slot, store the value to element #0,
1826 // then load the whole vector back out.
1827 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1829 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1830 int SPFI = StackPtrFI->getIndex();
1832 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1834 MachinePointerInfo::getFixedStack(SPFI),
1835 Node->getValueType(0).getVectorElementType(),
1837 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1838 MachinePointerInfo::getFixedStack(SPFI),
1839 false, false, false, 0);
1843 ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1844 const TargetLowering &TLI, SDValue &Res) {
1845 unsigned NumElems = Node->getNumOperands();
1847 EVT VT = Node->getValueType(0);
1849 // Try to group the scalars into pairs, shuffle the pairs together, then
1850 // shuffle the pairs of pairs together, etc. until the vector has
1851 // been built. This will work only if all of the necessary shuffle masks
1854 // We do this in two phases; first to check the legality of the shuffles,
1855 // and next, assuming that all shuffles are legal, to create the new nodes.
1856 for (int Phase = 0; Phase < 2; ++Phase) {
1857 SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
1859 for (unsigned i = 0; i < NumElems; ++i) {
1860 SDValue V = Node->getOperand(i);
1861 if (V.getOpcode() == ISD::UNDEF)
1866 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1867 IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1870 while (IntermedVals.size() > 2) {
1871 NewIntermedVals.clear();
1872 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1873 // This vector and the next vector are shuffled together (simply to
1874 // append the one to the other).
1875 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1877 SmallVector<int, 16> FinalIndices;
1878 FinalIndices.reserve(IntermedVals[i].second.size() +
1879 IntermedVals[i+1].second.size());
1882 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1885 FinalIndices.push_back(IntermedVals[i].second[j]);
1887 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1889 ShuffleVec[k] = NumElems + j;
1890 FinalIndices.push_back(IntermedVals[i+1].second[j]);
1895 Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1896 IntermedVals[i+1].first,
1898 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1900 NewIntermedVals.push_back(
1901 std::make_pair(Shuffle, std::move(FinalIndices)));
1904 // If we had an odd number of defined values, then append the last
1905 // element to the array of new vectors.
1906 if ((IntermedVals.size() & 1) != 0)
1907 NewIntermedVals.push_back(IntermedVals.back());
1909 IntermedVals.swap(NewIntermedVals);
1912 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1913 "Invalid number of intermediate vectors");
1914 SDValue Vec1 = IntermedVals[0].first;
1916 if (IntermedVals.size() > 1)
1917 Vec2 = IntermedVals[1].first;
1919 Vec2 = DAG.getUNDEF(VT);
1921 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1922 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1923 ShuffleVec[IntermedVals[0].second[i]] = i;
1924 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1925 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1928 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1929 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1936 /// Expand a BUILD_VECTOR node on targets that don't
1937 /// support the operation, but do support the resultant vector type.
1938 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1939 unsigned NumElems = Node->getNumOperands();
1940 SDValue Value1, Value2;
1942 EVT VT = Node->getValueType(0);
1943 EVT OpVT = Node->getOperand(0).getValueType();
1944 EVT EltVT = VT.getVectorElementType();
1946 // If the only non-undef value is the low element, turn this into a
1947 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1948 bool isOnlyLowElement = true;
1949 bool MoreThanTwoValues = false;
1950 bool isConstant = true;
1951 for (unsigned i = 0; i < NumElems; ++i) {
1952 SDValue V = Node->getOperand(i);
1953 if (V.getOpcode() == ISD::UNDEF)
1956 isOnlyLowElement = false;
1957 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1960 if (!Value1.getNode()) {
1962 } else if (!Value2.getNode()) {
1965 } else if (V != Value1 && V != Value2) {
1966 MoreThanTwoValues = true;
1970 if (!Value1.getNode())
1971 return DAG.getUNDEF(VT);
1973 if (isOnlyLowElement)
1974 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1976 // If all elements are constants, create a load from the constant pool.
1978 SmallVector<Constant*, 16> CV;
1979 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1980 if (ConstantFPSDNode *V =
1981 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1982 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1983 } else if (ConstantSDNode *V =
1984 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1986 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1988 // If OpVT and EltVT don't match, EltVT is not legal and the
1989 // element values have been promoted/truncated earlier. Undo this;
1990 // we don't want a v16i8 to become a v16i32 for example.
1991 const ConstantInt *CI = V->getConstantIntValue();
1992 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1993 CI->getZExtValue()));
1996 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1997 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1998 CV.push_back(UndefValue::get(OpNTy));
2001 Constant *CP = ConstantVector::get(CV);
2002 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
2003 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2004 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
2005 MachinePointerInfo::getConstantPool(),
2006 false, false, false, Alignment);
2009 SmallSet<SDValue, 16> DefinedValues;
2010 for (unsigned i = 0; i < NumElems; ++i) {
2011 if (Node->getOperand(i).getOpcode() == ISD::UNDEF)
2013 DefinedValues.insert(Node->getOperand(i));
2016 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
2017 if (!MoreThanTwoValues) {
2018 SmallVector<int, 8> ShuffleVec(NumElems, -1);
2019 for (unsigned i = 0; i < NumElems; ++i) {
2020 SDValue V = Node->getOperand(i);
2021 if (V.getOpcode() == ISD::UNDEF)
2023 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2025 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2026 // Get the splatted value into the low element of a vector register.
2027 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2029 if (Value2.getNode())
2030 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2032 Vec2 = DAG.getUNDEF(VT);
2034 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2035 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2039 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2044 // Otherwise, we can't handle this case efficiently.
2045 return ExpandVectorBuildThroughStack(Node);
2048 // Expand a node into a call to a libcall. If the result value
2049 // does not fit into a register, return the lo part and set the hi part to the
2050 // by-reg argument. If it does fit into a single register, return the result
2051 // and leave the Hi part unset.
2052 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2054 TargetLowering::ArgListTy Args;
2055 TargetLowering::ArgListEntry Entry;
2056 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2057 EVT ArgVT = Node->getOperand(i).getValueType();
2058 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2059 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2060 Entry.isSExt = isSigned;
2061 Entry.isZExt = !isSigned;
2062 Args.push_back(Entry);
2064 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2065 TLI.getPointerTy());
2067 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2069 // By default, the input chain to this libcall is the entry node of the
2070 // function. If the libcall is going to be emitted as a tail call then
2071 // TLI.isUsedByReturnOnly will change it to the right chain if the return
2072 // node which is being folded has a non-entry input chain.
2073 SDValue InChain = DAG.getEntryNode();
2075 // isTailCall may be true since the callee does not reference caller stack
2076 // frame. Check if it's in the right position.
2077 SDValue TCChain = InChain;
2078 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
2082 TargetLowering::CallLoweringInfo CLI(DAG);
2083 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2084 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2085 .setTailCall(isTailCall).setSExtResult(isSigned).setZExtResult(!isSigned);
2087 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2089 if (!CallInfo.second.getNode())
2090 // It's a tailcall, return the chain (which is the DAG root).
2091 return DAG.getRoot();
2093 return CallInfo.first;
2096 /// Generate a libcall taking the given operands as arguments
2097 /// and returning a result of type RetVT.
2098 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2099 const SDValue *Ops, unsigned NumOps,
2100 bool isSigned, SDLoc dl) {
2101 TargetLowering::ArgListTy Args;
2102 Args.reserve(NumOps);
2104 TargetLowering::ArgListEntry Entry;
2105 for (unsigned i = 0; i != NumOps; ++i) {
2106 Entry.Node = Ops[i];
2107 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2108 Entry.isSExt = isSigned;
2109 Entry.isZExt = !isSigned;
2110 Args.push_back(Entry);
2112 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2113 TLI.getPointerTy());
2115 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2117 TargetLowering::CallLoweringInfo CLI(DAG);
2118 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
2119 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2120 .setSExtResult(isSigned).setZExtResult(!isSigned);
2122 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
2124 return CallInfo.first;
2127 // Expand a node into a call to a libcall. Similar to
2128 // ExpandLibCall except that the first operand is the in-chain.
2129 std::pair<SDValue, SDValue>
2130 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2133 SDValue InChain = Node->getOperand(0);
2135 TargetLowering::ArgListTy Args;
2136 TargetLowering::ArgListEntry Entry;
2137 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2138 EVT ArgVT = Node->getOperand(i).getValueType();
2139 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2140 Entry.Node = Node->getOperand(i);
2142 Entry.isSExt = isSigned;
2143 Entry.isZExt = !isSigned;
2144 Args.push_back(Entry);
2146 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2147 TLI.getPointerTy());
2149 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2151 TargetLowering::CallLoweringInfo CLI(DAG);
2152 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2153 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2154 .setSExtResult(isSigned).setZExtResult(!isSigned);
2156 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2161 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2162 RTLIB::Libcall Call_F32,
2163 RTLIB::Libcall Call_F64,
2164 RTLIB::Libcall Call_F80,
2165 RTLIB::Libcall Call_F128,
2166 RTLIB::Libcall Call_PPCF128) {
2168 switch (Node->getSimpleValueType(0).SimpleTy) {
2169 default: llvm_unreachable("Unexpected request for libcall!");
2170 case MVT::f32: LC = Call_F32; break;
2171 case MVT::f64: LC = Call_F64; break;
2172 case MVT::f80: LC = Call_F80; break;
2173 case MVT::f128: LC = Call_F128; break;
2174 case MVT::ppcf128: LC = Call_PPCF128; break;
2176 return ExpandLibCall(LC, Node, false);
2179 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2180 RTLIB::Libcall Call_I8,
2181 RTLIB::Libcall Call_I16,
2182 RTLIB::Libcall Call_I32,
2183 RTLIB::Libcall Call_I64,
2184 RTLIB::Libcall Call_I128) {
2186 switch (Node->getSimpleValueType(0).SimpleTy) {
2187 default: llvm_unreachable("Unexpected request for libcall!");
2188 case MVT::i8: LC = Call_I8; break;
2189 case MVT::i16: LC = Call_I16; break;
2190 case MVT::i32: LC = Call_I32; break;
2191 case MVT::i64: LC = Call_I64; break;
2192 case MVT::i128: LC = Call_I128; break;
2194 return ExpandLibCall(LC, Node, isSigned);
2197 /// Return true if divmod libcall is available.
2198 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2199 const TargetLowering &TLI) {
2201 switch (Node->getSimpleValueType(0).SimpleTy) {
2202 default: llvm_unreachable("Unexpected request for libcall!");
2203 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2204 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2205 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2206 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2207 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2210 return TLI.getLibcallName(LC) != nullptr;
2213 /// Only issue divrem libcall if both quotient and remainder are needed.
2214 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2215 // The other use might have been replaced with a divrem already.
2216 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2217 unsigned OtherOpcode = 0;
2219 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2221 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2223 SDValue Op0 = Node->getOperand(0);
2224 SDValue Op1 = Node->getOperand(1);
2225 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2226 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2230 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2231 User->getOperand(0) == Op0 &&
2232 User->getOperand(1) == Op1)
2238 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2240 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2241 SmallVectorImpl<SDValue> &Results) {
2242 unsigned Opcode = Node->getOpcode();
2243 bool isSigned = Opcode == ISD::SDIVREM;
2246 switch (Node->getSimpleValueType(0).SimpleTy) {
2247 default: llvm_unreachable("Unexpected request for libcall!");
2248 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2249 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2250 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2251 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2252 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2255 // The input chain to this libcall is the entry node of the function.
2256 // Legalizing the call will automatically add the previous call to the
2258 SDValue InChain = DAG.getEntryNode();
2260 EVT RetVT = Node->getValueType(0);
2261 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2263 TargetLowering::ArgListTy Args;
2264 TargetLowering::ArgListEntry Entry;
2265 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2266 EVT ArgVT = Node->getOperand(i).getValueType();
2267 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2268 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2269 Entry.isSExt = isSigned;
2270 Entry.isZExt = !isSigned;
2271 Args.push_back(Entry);
2274 // Also pass the return address of the remainder.
2275 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2277 Entry.Ty = RetTy->getPointerTo();
2278 Entry.isSExt = isSigned;
2279 Entry.isZExt = !isSigned;
2280 Args.push_back(Entry);
2282 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2283 TLI.getPointerTy());
2286 TargetLowering::CallLoweringInfo CLI(DAG);
2287 CLI.setDebugLoc(dl).setChain(InChain)
2288 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2289 .setSExtResult(isSigned).setZExtResult(!isSigned);
2291 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2293 // Remainder is loaded back from the stack frame.
2294 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2295 MachinePointerInfo(), false, false, false, 0);
2296 Results.push_back(CallInfo.first);
2297 Results.push_back(Rem);
2300 /// Return true if sincos libcall is available.
2301 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2303 switch (Node->getSimpleValueType(0).SimpleTy) {
2304 default: llvm_unreachable("Unexpected request for libcall!");
2305 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2306 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2307 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2308 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2309 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2311 return TLI.getLibcallName(LC) != nullptr;
2314 /// Return true if sincos libcall is available and can be used to combine sin
2316 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2317 const TargetMachine &TM) {
2318 if (!isSinCosLibcallAvailable(Node, TLI))
2320 // GNU sin/cos functions set errno while sincos does not. Therefore
2321 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2322 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2323 if (isGNU && !TM.Options.UnsafeFPMath)
2328 /// Only issue sincos libcall if both sin and cos are needed.
2329 static bool useSinCos(SDNode *Node) {
2330 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2331 ? ISD::FCOS : ISD::FSIN;
2333 SDValue Op0 = Node->getOperand(0);
2334 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2335 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2339 // The other user might have been turned into sincos already.
2340 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2346 /// Issue libcalls to sincos to compute sin / cos pairs.
2348 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2349 SmallVectorImpl<SDValue> &Results) {
2351 switch (Node->getSimpleValueType(0).SimpleTy) {
2352 default: llvm_unreachable("Unexpected request for libcall!");
2353 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2354 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2355 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2356 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2357 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2360 // The input chain to this libcall is the entry node of the function.
2361 // Legalizing the call will automatically add the previous call to the
2363 SDValue InChain = DAG.getEntryNode();
2365 EVT RetVT = Node->getValueType(0);
2366 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2368 TargetLowering::ArgListTy Args;
2369 TargetLowering::ArgListEntry Entry;
2371 // Pass the argument.
2372 Entry.Node = Node->getOperand(0);
2374 Entry.isSExt = false;
2375 Entry.isZExt = false;
2376 Args.push_back(Entry);
2378 // Pass the return address of sin.
2379 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2380 Entry.Node = SinPtr;
2381 Entry.Ty = RetTy->getPointerTo();
2382 Entry.isSExt = false;
2383 Entry.isZExt = false;
2384 Args.push_back(Entry);
2386 // Also pass the return address of the cos.
2387 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2388 Entry.Node = CosPtr;
2389 Entry.Ty = RetTy->getPointerTo();
2390 Entry.isSExt = false;
2391 Entry.isZExt = false;
2392 Args.push_back(Entry);
2394 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2395 TLI.getPointerTy());
2398 TargetLowering::CallLoweringInfo CLI(DAG);
2399 CLI.setDebugLoc(dl).setChain(InChain)
2400 .setCallee(TLI.getLibcallCallingConv(LC),
2401 Type::getVoidTy(*DAG.getContext()), Callee, std::move(Args), 0);
2403 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2405 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2406 MachinePointerInfo(), false, false, false, 0));
2407 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2408 MachinePointerInfo(), false, false, false, 0));
2411 /// This function is responsible for legalizing a
2412 /// INT_TO_FP operation of the specified operand when the target requests that
2413 /// we expand it. At this point, we know that the result and operand types are
2414 /// legal for the target.
2415 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2419 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2420 // simple 32-bit [signed|unsigned] integer to float/double expansion
2422 // Get the stack frame index of a 8 byte buffer.
2423 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2425 // word offset constant for Hi/Lo address computation
2426 SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2427 StackSlot.getValueType());
2428 // set up Hi and Lo (into buffer) address based on endian
2429 SDValue Hi = StackSlot;
2430 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2431 StackSlot, WordOff);
2432 if (TLI.isLittleEndian())
2435 // if signed map to unsigned space
2438 // constant used to invert sign bit (signed to unsigned mapping)
2439 SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2440 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2444 // store the lo of the constructed double - based on integer input
2445 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2446 Op0Mapped, Lo, MachinePointerInfo(),
2448 // initial hi portion of constructed double
2449 SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2450 // store the hi of the constructed double - biased exponent
2451 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2452 MachinePointerInfo(),
2454 // load the constructed double
2455 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2456 MachinePointerInfo(), false, false, false, 0);
2457 // FP constant to bias correct the final result
2458 SDValue Bias = DAG.getConstantFP(isSigned ?
2459 BitsToDouble(0x4330000080000000ULL) :
2460 BitsToDouble(0x4330000000000000ULL),
2462 // subtract the bias
2463 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2466 // handle final rounding
2467 if (DestVT == MVT::f64) {
2470 } else if (DestVT.bitsLT(MVT::f64)) {
2471 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2472 DAG.getIntPtrConstant(0, dl));
2473 } else if (DestVT.bitsGT(MVT::f64)) {
2474 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2478 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2479 // Code below here assumes !isSigned without checking again.
2481 // Implementation of unsigned i64 to f64 following the algorithm in
2482 // __floatundidf in compiler_rt. This implementation has the advantage
2483 // of performing rounding correctly, both in the default rounding mode
2484 // and in all alternate rounding modes.
2485 // TODO: Generalize this for use with other types.
2486 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2488 DAG.getConstant(UINT64_C(0x4330000000000000), dl, MVT::i64);
2489 SDValue TwoP84PlusTwoP52 =
2490 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), dl,
2493 DAG.getConstant(UINT64_C(0x4530000000000000), dl, MVT::i64);
2495 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2496 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2497 DAG.getConstant(32, dl, MVT::i64));
2498 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2499 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2500 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2501 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2502 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2504 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2507 // Implementation of unsigned i64 to f32.
2508 // TODO: Generalize this for use with other types.
2509 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2510 // For unsigned conversions, convert them to signed conversions using the
2511 // algorithm from the x86_64 __floatundidf in compiler_rt.
2513 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2515 SDValue ShiftConst =
2516 DAG.getConstant(1, dl, TLI.getShiftAmountTy(Op0.getValueType()));
2517 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2518 SDValue AndConst = DAG.getConstant(1, dl, MVT::i64);
2519 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2520 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2522 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2523 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2525 // TODO: This really should be implemented using a branch rather than a
2526 // select. We happen to get lucky and machinesink does the right
2527 // thing most of the time. This would be a good candidate for a
2528 //pseudo-op, or, even better, for whole-function isel.
2529 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2530 Op0, DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
2531 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2534 // Otherwise, implement the fully general conversion.
2536 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2537 DAG.getConstant(UINT64_C(0xfffffffffffff800), dl, MVT::i64));
2538 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2539 DAG.getConstant(UINT64_C(0x800), dl, MVT::i64));
2540 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2541 DAG.getConstant(UINT64_C(0x7ff), dl, MVT::i64));
2542 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), And2,
2543 DAG.getConstant(UINT64_C(0), dl, MVT::i64),
2545 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2546 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), Op0,
2547 DAG.getConstant(UINT64_C(0x0020000000000000), dl,
2550 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2551 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2553 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2554 DAG.getConstant(32, dl, SHVT));
2555 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2556 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2558 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), dl,
2560 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2561 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2562 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2563 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2564 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2565 DAG.getIntPtrConstant(0, dl));
2568 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2570 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2572 DAG.getConstant(0, dl, Op0.getValueType()),
2574 SDValue Zero = DAG.getIntPtrConstant(0, dl),
2575 Four = DAG.getIntPtrConstant(4, dl);
2576 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2577 SignSet, Four, Zero);
2579 // If the sign bit of the integer is set, the large number will be treated
2580 // as a negative number. To counteract this, the dynamic code adds an
2581 // offset depending on the data type.
2583 switch (Op0.getSimpleValueType().SimpleTy) {
2584 default: llvm_unreachable("Unsupported integer type!");
2585 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2586 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2587 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2588 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2590 if (TLI.isLittleEndian()) FF <<= 32;
2591 Constant *FudgeFactor = ConstantInt::get(
2592 Type::getInt64Ty(*DAG.getContext()), FF);
2594 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2595 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2596 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2597 Alignment = std::min(Alignment, 4u);
2599 if (DestVT == MVT::f32)
2600 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2601 MachinePointerInfo::getConstantPool(),
2602 false, false, false, Alignment);
2604 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2605 DAG.getEntryNode(), CPIdx,
2606 MachinePointerInfo::getConstantPool(),
2607 MVT::f32, false, false, false, Alignment);
2608 HandleSDNode Handle(Load);
2609 LegalizeOp(Load.getNode());
2610 FudgeInReg = Handle.getValue();
2613 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2616 /// This function is responsible for legalizing a
2617 /// *INT_TO_FP operation of the specified operand when the target requests that
2618 /// we promote it. At this point, we know that the result and operand types are
2619 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2620 /// operation that takes a larger input.
2621 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2625 // First step, figure out the appropriate *INT_TO_FP operation to use.
2626 EVT NewInTy = LegalOp.getValueType();
2628 unsigned OpToUse = 0;
2630 // Scan for the appropriate larger type to use.
2632 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2633 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2635 // If the target supports SINT_TO_FP of this type, use it.
2636 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2637 OpToUse = ISD::SINT_TO_FP;
2640 if (isSigned) continue;
2642 // If the target supports UINT_TO_FP of this type, use it.
2643 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2644 OpToUse = ISD::UINT_TO_FP;
2648 // Otherwise, try a larger type.
2651 // Okay, we found the operation and type to use. Zero extend our input to the
2652 // desired type then run the operation on it.
2653 return DAG.getNode(OpToUse, dl, DestVT,
2654 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2655 dl, NewInTy, LegalOp));
2658 /// This function is responsible for legalizing a
2659 /// FP_TO_*INT operation of the specified operand when the target requests that
2660 /// we promote it. At this point, we know that the result and operand types are
2661 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2662 /// operation that returns a larger result.
2663 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2667 // First step, figure out the appropriate FP_TO*INT operation to use.
2668 EVT NewOutTy = DestVT;
2670 unsigned OpToUse = 0;
2672 // Scan for the appropriate larger type to use.
2674 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2675 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2677 // A larger signed type can hold all unsigned values of the requested type,
2678 // so using FP_TO_SINT is valid
2679 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2680 OpToUse = ISD::FP_TO_SINT;
2684 // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2685 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2686 OpToUse = ISD::FP_TO_UINT;
2690 // Otherwise, try a larger type.
2694 // Okay, we found the operation and type to use.
2695 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2697 // Truncate the result of the extended FP_TO_*INT operation to the desired
2699 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2702 /// Open code the operations for BSWAP of the specified operation.
2703 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2704 EVT VT = Op.getValueType();
2705 EVT SHVT = TLI.getShiftAmountTy(VT);
2706 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2707 switch (VT.getSimpleVT().SimpleTy) {
2708 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2710 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2711 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2712 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2714 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2715 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2716 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2717 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2718 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2719 DAG.getConstant(0xFF0000, dl, VT));
2720 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2721 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2722 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2723 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2725 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2726 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2727 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2728 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2729 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2730 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2731 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2732 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2733 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2734 DAG.getConstant(255ULL<<48, dl, VT));
2735 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2736 DAG.getConstant(255ULL<<40, dl, VT));
2737 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2738 DAG.getConstant(255ULL<<32, dl, VT));
2739 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2740 DAG.getConstant(255ULL<<24, dl, VT));
2741 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2742 DAG.getConstant(255ULL<<16, dl, VT));
2743 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2744 DAG.getConstant(255ULL<<8 , dl, VT));
2745 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2746 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2747 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2748 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2749 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2750 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2751 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2755 /// Expand the specified bitcount instruction into operations.
2756 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2759 default: llvm_unreachable("Cannot expand this yet!");
2761 EVT VT = Op.getValueType();
2762 EVT ShVT = TLI.getShiftAmountTy(VT);
2763 unsigned Len = VT.getSizeInBits();
2765 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2766 "CTPOP not implemented for this type.");
2768 // This is the "best" algorithm from
2769 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2771 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)),
2773 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)),
2775 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)),
2777 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)),
2780 // v = v - ((v >> 1) & 0x55555555...)
2781 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2782 DAG.getNode(ISD::AND, dl, VT,
2783 DAG.getNode(ISD::SRL, dl, VT, Op,
2784 DAG.getConstant(1, dl, ShVT)),
2786 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2787 Op = DAG.getNode(ISD::ADD, dl, VT,
2788 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2789 DAG.getNode(ISD::AND, dl, VT,
2790 DAG.getNode(ISD::SRL, dl, VT, Op,
2791 DAG.getConstant(2, dl, ShVT)),
2793 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2794 Op = DAG.getNode(ISD::AND, dl, VT,
2795 DAG.getNode(ISD::ADD, dl, VT, Op,
2796 DAG.getNode(ISD::SRL, dl, VT, Op,
2797 DAG.getConstant(4, dl, ShVT))),
2799 // v = (v * 0x01010101...) >> (Len - 8)
2800 Op = DAG.getNode(ISD::SRL, dl, VT,
2801 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2802 DAG.getConstant(Len - 8, dl, ShVT));
2806 case ISD::CTLZ_ZERO_UNDEF:
2807 // This trivially expands to CTLZ.
2808 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2810 // for now, we do this:
2811 // x = x | (x >> 1);
2812 // x = x | (x >> 2);
2814 // x = x | (x >>16);
2815 // x = x | (x >>32); // for 64-bit input
2816 // return popcount(~x);
2818 // Ref: "Hacker's Delight" by Henry Warren
2819 EVT VT = Op.getValueType();
2820 EVT ShVT = TLI.getShiftAmountTy(VT);
2821 unsigned len = VT.getSizeInBits();
2822 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2823 SDValue Tmp3 = DAG.getConstant(1ULL << i, dl, ShVT);
2824 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2825 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2827 Op = DAG.getNOT(dl, Op, VT);
2828 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2830 case ISD::CTTZ_ZERO_UNDEF:
2831 // This trivially expands to CTTZ.
2832 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2834 // for now, we use: { return popcount(~x & (x - 1)); }
2835 // unless the target has ctlz but not ctpop, in which case we use:
2836 // { return 32 - nlz(~x & (x-1)); }
2837 // Ref: "Hacker's Delight" by Henry Warren
2838 EVT VT = Op.getValueType();
2839 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2840 DAG.getNOT(dl, Op, VT),
2841 DAG.getNode(ISD::SUB, dl, VT, Op,
2842 DAG.getConstant(1, dl, VT)));
2843 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2844 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2845 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2846 return DAG.getNode(ISD::SUB, dl, VT,
2847 DAG.getConstant(VT.getSizeInBits(), dl, VT),
2848 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2849 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2854 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2855 unsigned Opc = Node->getOpcode();
2856 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2857 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
2858 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
2860 return ExpandChainLibCall(LC, Node, false);
2863 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2864 SmallVector<SDValue, 8> Results;
2866 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2868 switch (Node->getOpcode()) {
2871 case ISD::CTLZ_ZERO_UNDEF:
2873 case ISD::CTTZ_ZERO_UNDEF:
2874 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2875 Results.push_back(Tmp1);
2878 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2880 case ISD::FRAMEADDR:
2881 case ISD::RETURNADDR:
2882 case ISD::FRAME_TO_ARGS_OFFSET:
2883 Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
2885 case ISD::FLT_ROUNDS_:
2886 Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
2888 case ISD::EH_RETURN:
2892 case ISD::EH_SJLJ_LONGJMP:
2893 // If the target didn't expand these, there's nothing to do, so just
2894 // preserve the chain and be done.
2895 Results.push_back(Node->getOperand(0));
2897 case ISD::EH_SJLJ_SETJMP:
2898 // If the target didn't expand this, just return 'zero' and preserve the
2900 Results.push_back(DAG.getConstant(0, dl, MVT::i32));
2901 Results.push_back(Node->getOperand(0));
2903 case ISD::ATOMIC_FENCE: {
2904 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2905 // FIXME: handle "fence singlethread" more efficiently.
2906 TargetLowering::ArgListTy Args;
2908 TargetLowering::CallLoweringInfo CLI(DAG);
2909 CLI.setDebugLoc(dl).setChain(Node->getOperand(0))
2910 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2911 DAG.getExternalSymbol("__sync_synchronize",
2912 TLI.getPointerTy()), std::move(Args), 0);
2914 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2916 Results.push_back(CallResult.second);
2919 case ISD::ATOMIC_LOAD: {
2920 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2921 SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
2922 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2923 SDValue Swap = DAG.getAtomicCmpSwap(
2924 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2925 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
2926 cast<AtomicSDNode>(Node)->getMemOperand(),
2927 cast<AtomicSDNode>(Node)->getOrdering(),
2928 cast<AtomicSDNode>(Node)->getOrdering(),
2929 cast<AtomicSDNode>(Node)->getSynchScope());
2930 Results.push_back(Swap.getValue(0));
2931 Results.push_back(Swap.getValue(1));
2934 case ISD::ATOMIC_STORE: {
2935 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2936 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2937 cast<AtomicSDNode>(Node)->getMemoryVT(),
2938 Node->getOperand(0),
2939 Node->getOperand(1), Node->getOperand(2),
2940 cast<AtomicSDNode>(Node)->getMemOperand(),
2941 cast<AtomicSDNode>(Node)->getOrdering(),
2942 cast<AtomicSDNode>(Node)->getSynchScope());
2943 Results.push_back(Swap.getValue(1));
2946 // By default, atomic intrinsics are marked Legal and lowered. Targets
2947 // which don't support them directly, however, may want libcalls, in which
2948 // case they mark them Expand, and we get here.
2949 case ISD::ATOMIC_SWAP:
2950 case ISD::ATOMIC_LOAD_ADD:
2951 case ISD::ATOMIC_LOAD_SUB:
2952 case ISD::ATOMIC_LOAD_AND:
2953 case ISD::ATOMIC_LOAD_OR:
2954 case ISD::ATOMIC_LOAD_XOR:
2955 case ISD::ATOMIC_LOAD_NAND:
2956 case ISD::ATOMIC_LOAD_MIN:
2957 case ISD::ATOMIC_LOAD_MAX:
2958 case ISD::ATOMIC_LOAD_UMIN:
2959 case ISD::ATOMIC_LOAD_UMAX:
2960 case ISD::ATOMIC_CMP_SWAP: {
2961 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2962 Results.push_back(Tmp.first);
2963 Results.push_back(Tmp.second);
2966 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
2967 // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
2968 // splits out the success value as a comparison. Expanding the resulting
2969 // ATOMIC_CMP_SWAP will produce a libcall.
2970 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2971 SDValue Res = DAG.getAtomicCmpSwap(
2972 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2973 Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
2974 Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand(),
2975 cast<AtomicSDNode>(Node)->getSuccessOrdering(),
2976 cast<AtomicSDNode>(Node)->getFailureOrdering(),
2977 cast<AtomicSDNode>(Node)->getSynchScope());
2979 SDValue Success = DAG.getSetCC(SDLoc(Node), Node->getValueType(1),
2980 Res, Node->getOperand(2), ISD::SETEQ);
2982 Results.push_back(Res.getValue(0));
2983 Results.push_back(Success);
2984 Results.push_back(Res.getValue(1));
2987 case ISD::DYNAMIC_STACKALLOC:
2988 ExpandDYNAMIC_STACKALLOC(Node, Results);
2990 case ISD::MERGE_VALUES:
2991 for (unsigned i = 0; i < Node->getNumValues(); i++)
2992 Results.push_back(Node->getOperand(i));
2995 EVT VT = Node->getValueType(0);
2997 Results.push_back(DAG.getConstant(0, dl, VT));
2999 assert(VT.isFloatingPoint() && "Unknown value type!");
3000 Results.push_back(DAG.getConstantFP(0, dl, VT));
3005 // If this operation is not supported, lower it to 'abort()' call
3006 TargetLowering::ArgListTy Args;
3007 TargetLowering::CallLoweringInfo CLI(DAG);
3008 CLI.setDebugLoc(dl).setChain(Node->getOperand(0))
3009 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3010 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3011 std::move(Args), 0);
3012 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3014 Results.push_back(CallResult.second);
3019 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3020 Node->getValueType(0), dl);
3021 Results.push_back(Tmp1);
3023 case ISD::FP_EXTEND:
3024 Tmp1 = EmitStackConvert(Node->getOperand(0),
3025 Node->getOperand(0).getValueType(),
3026 Node->getValueType(0), dl);
3027 Results.push_back(Tmp1);
3029 case ISD::SIGN_EXTEND_INREG: {
3030 // NOTE: we could fall back on load/store here too for targets without
3031 // SAR. However, it is doubtful that any exist.
3032 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3033 EVT VT = Node->getValueType(0);
3034 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
3037 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3038 ExtraVT.getScalarType().getSizeInBits();
3039 SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
3040 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3041 Node->getOperand(0), ShiftCst);
3042 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3043 Results.push_back(Tmp1);
3046 case ISD::FP_ROUND_INREG: {
3047 // The only way we can lower this is to turn it into a TRUNCSTORE,
3048 // EXTLOAD pair, targeting a temporary location (a stack slot).
3050 // NOTE: there is a choice here between constantly creating new stack
3051 // slots and always reusing the same one. We currently always create
3052 // new ones, as reuse may inhibit scheduling.
3053 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3054 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3055 Node->getValueType(0), dl);
3056 Results.push_back(Tmp1);
3059 case ISD::SINT_TO_FP:
3060 case ISD::UINT_TO_FP:
3061 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3062 Node->getOperand(0), Node->getValueType(0), dl);
3063 Results.push_back(Tmp1);
3065 case ISD::FP_TO_SINT:
3066 if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
3067 Results.push_back(Tmp1);
3069 case ISD::FP_TO_UINT: {
3070 SDValue True, False;
3071 EVT VT = Node->getOperand(0).getValueType();
3072 EVT NVT = Node->getValueType(0);
3073 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3074 APInt::getNullValue(VT.getSizeInBits()));
3075 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3076 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3077 Tmp1 = DAG.getConstantFP(apf, dl, VT);
3078 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3079 Node->getOperand(0),
3081 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3082 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3083 DAG.getNode(ISD::FSUB, dl, VT,
3084 Node->getOperand(0), Tmp1));
3085 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3086 DAG.getConstant(x, dl, NVT));
3087 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3088 Results.push_back(Tmp1);
3092 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3093 EVT VT = Node->getValueType(0);
3094 Tmp1 = Node->getOperand(0);
3095 Tmp2 = Node->getOperand(1);
3096 unsigned Align = Node->getConstantOperandVal(3);
3098 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3099 MachinePointerInfo(V),
3100 false, false, false, 0);
3101 SDValue VAList = VAListLoad;
3103 if (Align > TLI.getMinStackArgumentAlignment()) {
3104 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3106 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3107 DAG.getConstant(Align - 1, dl,
3108 VAList.getValueType()));
3110 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3111 DAG.getConstant(-(int64_t)Align, dl,
3112 VAList.getValueType()));
3115 // Increment the pointer, VAList, to the next vaarg
3116 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3117 DAG.getConstant(TLI.getDataLayout()->
3118 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3120 VAList.getValueType()));
3121 // Store the incremented VAList to the legalized pointer
3122 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3123 MachinePointerInfo(V), false, false, 0);
3124 // Load the actual argument out of the pointer VAList
3125 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3126 false, false, false, 0));
3127 Results.push_back(Results[0].getValue(1));
3131 // This defaults to loading a pointer from the input and storing it to the
3132 // output, returning the chain.
3133 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3134 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3135 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3136 Node->getOperand(2), MachinePointerInfo(VS),
3137 false, false, false, 0);
3138 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3139 MachinePointerInfo(VD), false, false, 0);
3140 Results.push_back(Tmp1);
3143 case ISD::EXTRACT_VECTOR_ELT:
3144 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3145 // This must be an access of the only element. Return it.
3146 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3147 Node->getOperand(0));
3149 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3150 Results.push_back(Tmp1);
3152 case ISD::EXTRACT_SUBVECTOR:
3153 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3155 case ISD::INSERT_SUBVECTOR:
3156 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3158 case ISD::CONCAT_VECTORS: {
3159 Results.push_back(ExpandVectorBuildThroughStack(Node));
3162 case ISD::SCALAR_TO_VECTOR:
3163 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3165 case ISD::INSERT_VECTOR_ELT:
3166 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3167 Node->getOperand(1),
3168 Node->getOperand(2), dl));
3170 case ISD::VECTOR_SHUFFLE: {
3171 SmallVector<int, 32> NewMask;
3172 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3174 EVT VT = Node->getValueType(0);
3175 EVT EltVT = VT.getVectorElementType();
3176 SDValue Op0 = Node->getOperand(0);
3177 SDValue Op1 = Node->getOperand(1);
3178 if (!TLI.isTypeLegal(EltVT)) {
3180 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3182 // BUILD_VECTOR operands are allowed to be wider than the element type.
3183 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3185 if (NewEltVT.bitsLT(EltVT)) {
3187 // Convert shuffle node.
3188 // If original node was v4i64 and the new EltVT is i32,
3189 // cast operands to v8i32 and re-build the mask.
3191 // Calculate new VT, the size of the new VT should be equal to original.
3193 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3194 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3195 assert(NewVT.bitsEq(VT));
3197 // cast operands to new VT
3198 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3199 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3201 // Convert the shuffle mask
3202 unsigned int factor =
3203 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3205 // EltVT gets smaller
3208 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3210 for (unsigned fi = 0; fi < factor; ++fi)
3211 NewMask.push_back(Mask[i]);
3214 for (unsigned fi = 0; fi < factor; ++fi)
3215 NewMask.push_back(Mask[i]*factor+fi);
3223 unsigned NumElems = VT.getVectorNumElements();
3224 SmallVector<SDValue, 16> Ops;
3225 for (unsigned i = 0; i != NumElems; ++i) {
3227 Ops.push_back(DAG.getUNDEF(EltVT));
3230 unsigned Idx = Mask[i];
3232 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3234 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy())));
3236 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3238 DAG.getConstant(Idx - NumElems, dl,
3239 TLI.getVectorIdxTy())));
3242 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3243 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3244 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3245 Results.push_back(Tmp1);
3248 case ISD::EXTRACT_ELEMENT: {
3249 EVT OpTy = Node->getOperand(0).getValueType();
3250 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3252 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3253 DAG.getConstant(OpTy.getSizeInBits()/2, dl,
3254 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3255 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3258 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3259 Node->getOperand(0));
3261 Results.push_back(Tmp1);
3264 case ISD::STACKSAVE:
3265 // Expand to CopyFromReg if the target set
3266 // StackPointerRegisterToSaveRestore.
3267 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3268 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3269 Node->getValueType(0)));
3270 Results.push_back(Results[0].getValue(1));
3272 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3273 Results.push_back(Node->getOperand(0));
3276 case ISD::STACKRESTORE:
3277 // Expand to CopyToReg if the target set
3278 // StackPointerRegisterToSaveRestore.
3279 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3280 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3281 Node->getOperand(1)));
3283 Results.push_back(Node->getOperand(0));
3286 case ISD::FCOPYSIGN:
3287 Results.push_back(ExpandFCOPYSIGN(Node));
3290 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3291 Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3292 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3293 Node->getOperand(0));
3294 Results.push_back(Tmp1);
3297 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3298 EVT VT = Node->getValueType(0);
3299 Tmp1 = Node->getOperand(0);
3300 Tmp2 = DAG.getConstantFP(0.0, dl, VT);
3301 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3302 Tmp1, Tmp2, ISD::SETUGT);
3303 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3304 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3305 Results.push_back(Tmp1);
3309 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
3310 RTLIB::FMIN_F80, RTLIB::FMIN_F128,
3311 RTLIB::FMIN_PPCF128));
3314 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
3315 RTLIB::FMAX_F80, RTLIB::FMAX_F128,
3316 RTLIB::FMAX_PPCF128));
3319 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3320 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3321 RTLIB::SQRT_PPCF128));
3325 EVT VT = Node->getValueType(0);
3326 bool isSIN = Node->getOpcode() == ISD::FSIN;
3327 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3328 // fcos which share the same operand and both are used.
3329 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3330 canCombineSinCosLibcall(Node, TLI, TM))
3331 && useSinCos(Node)) {
3332 SDVTList VTs = DAG.getVTList(VT, VT);
3333 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3335 Tmp1 = Tmp1.getValue(1);
3336 Results.push_back(Tmp1);
3338 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3339 RTLIB::SIN_F80, RTLIB::SIN_F128,
3340 RTLIB::SIN_PPCF128));
3342 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3343 RTLIB::COS_F80, RTLIB::COS_F128,
3344 RTLIB::COS_PPCF128));
3349 // Expand into sincos libcall.
3350 ExpandSinCosLibCall(Node, Results);
3353 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3354 RTLIB::LOG_F80, RTLIB::LOG_F128,
3355 RTLIB::LOG_PPCF128));
3358 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3359 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3360 RTLIB::LOG2_PPCF128));
3363 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3364 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3365 RTLIB::LOG10_PPCF128));
3368 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3369 RTLIB::EXP_F80, RTLIB::EXP_F128,
3370 RTLIB::EXP_PPCF128));
3373 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3374 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3375 RTLIB::EXP2_PPCF128));
3378 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3379 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3380 RTLIB::TRUNC_PPCF128));
3383 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3384 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3385 RTLIB::FLOOR_PPCF128));
3388 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3389 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3390 RTLIB::CEIL_PPCF128));
3393 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3394 RTLIB::RINT_F80, RTLIB::RINT_F128,
3395 RTLIB::RINT_PPCF128));
3397 case ISD::FNEARBYINT:
3398 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3399 RTLIB::NEARBYINT_F64,
3400 RTLIB::NEARBYINT_F80,
3401 RTLIB::NEARBYINT_F128,
3402 RTLIB::NEARBYINT_PPCF128));
3405 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3409 RTLIB::ROUND_PPCF128));
3412 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3413 RTLIB::POWI_F80, RTLIB::POWI_F128,
3414 RTLIB::POWI_PPCF128));
3417 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3418 RTLIB::POW_F80, RTLIB::POW_F128,
3419 RTLIB::POW_PPCF128));
3422 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3423 RTLIB::DIV_F80, RTLIB::DIV_F128,
3424 RTLIB::DIV_PPCF128));
3427 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3428 RTLIB::REM_F80, RTLIB::REM_F128,
3429 RTLIB::REM_PPCF128));
3432 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3433 RTLIB::FMA_F80, RTLIB::FMA_F128,
3434 RTLIB::FMA_PPCF128));
3437 llvm_unreachable("Illegal fmad should never be formed");
3440 Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
3441 RTLIB::ADD_F80, RTLIB::ADD_F128,
3442 RTLIB::ADD_PPCF128));
3445 Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
3446 RTLIB::MUL_F80, RTLIB::MUL_F128,
3447 RTLIB::MUL_PPCF128));
3449 case ISD::FP16_TO_FP: {
3450 if (Node->getValueType(0) == MVT::f32) {
3451 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3455 // We can extend to types bigger than f32 in two steps without changing the
3456 // result. Since "f16 -> f32" is much more commonly available, give CodeGen
3457 // the option of emitting that before resorting to a libcall.
3459 DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3461 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3464 case ISD::FP_TO_FP16: {
3465 if (!TM.Options.UseSoftFloat && TM.Options.UnsafeFPMath) {
3466 SDValue Op = Node->getOperand(0);
3467 MVT SVT = Op.getSimpleValueType();
3468 if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3469 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3470 // Under fastmath, we can expand this node into a fround followed by
3471 // a float-half conversion.
3472 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3473 DAG.getIntPtrConstant(0, dl));
3475 DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, FloatVal));
3481 RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16);
3482 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
3483 Results.push_back(ExpandLibCall(LC, Node, false));
3486 case ISD::ConstantFP: {
3487 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3488 // Check to see if this FP immediate is already legal.
3489 // If this is a legal constant, turn it into a TargetConstantFP node.
3490 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3491 Results.push_back(ExpandConstantFP(CFP, true));
3495 EVT VT = Node->getValueType(0);
3496 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3497 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3498 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3499 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3500 Results.push_back(Tmp1);
3502 Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
3503 RTLIB::SUB_F80, RTLIB::SUB_F128,
3504 RTLIB::SUB_PPCF128));
3509 EVT VT = Node->getValueType(0);
3510 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3511 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3512 "Don't know how to expand this subtraction!");
3513 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3514 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3516 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3517 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3522 EVT VT = Node->getValueType(0);
3523 bool isSigned = Node->getOpcode() == ISD::SREM;
3524 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3525 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3526 Tmp2 = Node->getOperand(0);
3527 Tmp3 = Node->getOperand(1);
3528 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3529 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3530 // If div is legal, it's better to do the normal expansion
3531 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3532 useDivRem(Node, isSigned, false))) {
3533 SDVTList VTs = DAG.getVTList(VT, VT);
3534 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3535 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3537 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3538 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3539 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3540 } else if (isSigned)
3541 Tmp1 = ExpandIntLibCall(Node, true,
3543 RTLIB::SREM_I16, RTLIB::SREM_I32,
3544 RTLIB::SREM_I64, RTLIB::SREM_I128);
3546 Tmp1 = ExpandIntLibCall(Node, false,
3548 RTLIB::UREM_I16, RTLIB::UREM_I32,
3549 RTLIB::UREM_I64, RTLIB::UREM_I128);
3550 Results.push_back(Tmp1);
3555 bool isSigned = Node->getOpcode() == ISD::SDIV;
3556 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3557 EVT VT = Node->getValueType(0);
3558 SDVTList VTs = DAG.getVTList(VT, VT);
3559 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3560 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3561 useDivRem(Node, isSigned, true)))
3562 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3563 Node->getOperand(1));
3565 Tmp1 = ExpandIntLibCall(Node, true,
3567 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3568 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3570 Tmp1 = ExpandIntLibCall(Node, false,
3572 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3573 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3574 Results.push_back(Tmp1);
3579 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3581 EVT VT = Node->getValueType(0);
3582 SDVTList VTs = DAG.getVTList(VT, VT);
3583 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3584 "If this wasn't legal, it shouldn't have been created!");
3585 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3586 Node->getOperand(1));
3587 Results.push_back(Tmp1.getValue(1));
3592 // Expand into divrem libcall
3593 ExpandDivRemLibCall(Node, Results);
3596 EVT VT = Node->getValueType(0);
3597 SDVTList VTs = DAG.getVTList(VT, VT);
3598 // See if multiply or divide can be lowered using two-result operations.
3599 // We just need the low half of the multiply; try both the signed
3600 // and unsigned forms. If the target supports both SMUL_LOHI and
3601 // UMUL_LOHI, form a preference by checking which forms of plain
3602 // MULH it supports.
3603 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3604 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3605 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3606 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3607 unsigned OpToUse = 0;
3608 if (HasSMUL_LOHI && !HasMULHS) {
3609 OpToUse = ISD::SMUL_LOHI;
3610 } else if (HasUMUL_LOHI && !HasMULHU) {
3611 OpToUse = ISD::UMUL_LOHI;
3612 } else if (HasSMUL_LOHI) {
3613 OpToUse = ISD::SMUL_LOHI;
3614 } else if (HasUMUL_LOHI) {
3615 OpToUse = ISD::UMUL_LOHI;
3618 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3619 Node->getOperand(1)));
3624 EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3625 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3626 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3627 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3628 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3629 TLI.expandMUL(Node, Lo, Hi, HalfType, DAG)) {
3630 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3631 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3632 SDValue Shift = DAG.getConstant(HalfType.getSizeInBits(), dl,
3633 TLI.getShiftAmountTy(HalfType));
3634 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3635 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3639 Tmp1 = ExpandIntLibCall(Node, false,
3641 RTLIB::MUL_I16, RTLIB::MUL_I32,
3642 RTLIB::MUL_I64, RTLIB::MUL_I128);
3643 Results.push_back(Tmp1);
3648 SDValue LHS = Node->getOperand(0);
3649 SDValue RHS = Node->getOperand(1);
3650 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3651 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3653 Results.push_back(Sum);
3654 EVT ResultType = Node->getValueType(1);
3655 EVT OType = getSetCCResultType(Node->getValueType(0));
3657 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3659 // LHSSign -> LHS >= 0
3660 // RHSSign -> RHS >= 0
3661 // SumSign -> Sum >= 0
3664 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3666 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3668 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3669 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3670 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3671 Node->getOpcode() == ISD::SADDO ?
3672 ISD::SETEQ : ISD::SETNE);
3674 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3675 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3677 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3678 Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3683 SDValue LHS = Node->getOperand(0);
3684 SDValue RHS = Node->getOperand(1);
3685 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3686 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3688 Results.push_back(Sum);
3690 EVT ResultType = Node->getValueType(1);
3691 EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3693 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
3694 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3696 Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3701 EVT VT = Node->getValueType(0);
3702 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3703 SDValue LHS = Node->getOperand(0);
3704 SDValue RHS = Node->getOperand(1);
3707 static const unsigned Ops[2][3] =
3708 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3709 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3710 bool isSigned = Node->getOpcode() == ISD::SMULO;
3711 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3712 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3713 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3714 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3715 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3717 TopHalf = BottomHalf.getValue(1);
3718 } else if (TLI.isTypeLegal(WideVT)) {
3719 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3720 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3721 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3722 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3723 DAG.getIntPtrConstant(0, dl));
3724 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3725 DAG.getIntPtrConstant(1, dl));
3727 // We can fall back to a libcall with an illegal type for the MUL if we
3728 // have a libcall big enough.
3729 // Also, we can fall back to a division in some cases, but that's a big
3730 // performance hit in the general case.
3731 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3732 if (WideVT == MVT::i16)
3733 LC = RTLIB::MUL_I16;
3734 else if (WideVT == MVT::i32)
3735 LC = RTLIB::MUL_I32;
3736 else if (WideVT == MVT::i64)
3737 LC = RTLIB::MUL_I64;
3738 else if (WideVT == MVT::i128)
3739 LC = RTLIB::MUL_I128;
3740 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3742 // The high part is obtained by SRA'ing all but one of the bits of low
3744 unsigned LoSize = VT.getSizeInBits();
3745 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3746 DAG.getConstant(LoSize - 1, dl,
3747 TLI.getPointerTy()));
3748 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3749 DAG.getConstant(LoSize - 1, dl,
3750 TLI.getPointerTy()));
3752 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3753 // pre-lowered to the correct types. This all depends upon WideVT not
3754 // being a legal type for the architecture and thus has to be split to
3756 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3757 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3758 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3759 DAG.getIntPtrConstant(0, dl));
3760 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3761 DAG.getIntPtrConstant(1, dl));
3762 // Ret is a node with an illegal type. Because such things are not
3763 // generally permitted during this phase of legalization, make sure the
3764 // node has no more uses. The above EXTRACT_ELEMENT nodes should have been
3766 assert(Ret->use_empty() &&
3767 "Unexpected uses of illegally type from expanded lib call.");
3771 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, dl,
3772 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3773 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3774 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3777 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3778 DAG.getConstant(0, dl, VT), ISD::SETNE);
3780 Results.push_back(BottomHalf);
3781 Results.push_back(TopHalf);
3784 case ISD::BUILD_PAIR: {
3785 EVT PairTy = Node->getValueType(0);
3786 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3787 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3788 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3789 DAG.getConstant(PairTy.getSizeInBits()/2, dl,
3790 TLI.getShiftAmountTy(PairTy)));
3791 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3795 Tmp1 = Node->getOperand(0);
3796 Tmp2 = Node->getOperand(1);
3797 Tmp3 = Node->getOperand(2);
3798 if (Tmp1.getOpcode() == ISD::SETCC) {
3799 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3801 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3803 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3804 DAG.getConstant(0, dl, Tmp1.getValueType()),
3805 Tmp2, Tmp3, ISD::SETNE);
3807 Results.push_back(Tmp1);
3810 SDValue Chain = Node->getOperand(0);
3811 SDValue Table = Node->getOperand(1);
3812 SDValue Index = Node->getOperand(2);
3814 EVT PTy = TLI.getPointerTy();
3816 const DataLayout &TD = *TLI.getDataLayout();
3817 unsigned EntrySize =
3818 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3820 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3821 DAG.getConstant(EntrySize, dl, Index.getValueType()));
3822 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3825 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3826 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3827 MachinePointerInfo::getJumpTable(), MemVT,
3828 false, false, false, 0);
3830 if (TM.getRelocationModel() == Reloc::PIC_) {
3831 // For PIC, the sequence is:
3832 // BRIND(load(Jumptable + index) + RelocBase)
3833 // RelocBase can be JumpTable, GOT or some sort of global base.
3834 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3835 TLI.getPICJumpTableRelocBase(Table, DAG));
3837 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3838 Results.push_back(Tmp1);
3842 // Expand brcond's setcc into its constituent parts and create a BR_CC
3844 Tmp1 = Node->getOperand(0);
3845 Tmp2 = Node->getOperand(1);
3846 if (Tmp2.getOpcode() == ISD::SETCC) {
3847 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3848 Tmp1, Tmp2.getOperand(2),
3849 Tmp2.getOperand(0), Tmp2.getOperand(1),
3850 Node->getOperand(2));
3852 // We test only the i1 bit. Skip the AND if UNDEF.
3853 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3854 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3855 DAG.getConstant(1, dl, Tmp2.getValueType()));
3856 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3857 DAG.getCondCode(ISD::SETNE), Tmp3,
3858 DAG.getConstant(0, dl, Tmp3.getValueType()),
3859 Node->getOperand(2));
3861 Results.push_back(Tmp1);
3864 Tmp1 = Node->getOperand(0);
3865 Tmp2 = Node->getOperand(1);
3866 Tmp3 = Node->getOperand(2);
3867 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3868 Tmp3, NeedInvert, dl);
3871 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3872 // condition code, create a new SETCC node.
3874 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3877 // If we expanded the SETCC by inverting the condition code, then wrap
3878 // the existing SETCC in a NOT to restore the intended condition.
3880 Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3882 Results.push_back(Tmp1);
3886 // Otherwise, SETCC for the given comparison type must be completely
3887 // illegal; expand it into a SELECT_CC.
3888 EVT VT = Node->getValueType(0);
3890 switch (TLI.getBooleanContents(Tmp1->getValueType(0))) {
3891 case TargetLowering::ZeroOrOneBooleanContent:
3892 case TargetLowering::UndefinedBooleanContent:
3895 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3899 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3900 DAG.getConstant(TrueValue, dl, VT),
3901 DAG.getConstant(0, dl, VT),
3903 Results.push_back(Tmp1);
3906 case ISD::SELECT_CC: {
3907 Tmp1 = Node->getOperand(0); // LHS
3908 Tmp2 = Node->getOperand(1); // RHS
3909 Tmp3 = Node->getOperand(2); // True
3910 Tmp4 = Node->getOperand(3); // False
3911 EVT VT = Node->getValueType(0);
3912 SDValue CC = Node->getOperand(4);
3913 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3915 if (TLI.isCondCodeLegal(CCOp, Tmp1.getSimpleValueType())) {
3916 // If the condition code is legal, then we need to expand this
3917 // node using SETCC and SELECT.
3918 EVT CmpVT = Tmp1.getValueType();
3919 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3920 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3922 EVT CCVT = TLI.getSetCCResultType(*DAG.getContext(), CmpVT);
3923 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3924 Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3928 // SELECT_CC is legal, so the condition code must not be.
3929 bool Legalized = false;
3930 // Try to legalize by inverting the condition. This is for targets that
3931 // might support an ordered version of a condition, but not the unordered
3932 // version (or vice versa).
3933 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3934 Tmp1.getValueType().isInteger());
3935 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3936 // Use the new condition code and swap true and false
3938 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3940 // If The inverse is not legal, then try to swap the arguments using
3941 // the inverse condition code.
3942 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3943 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3944 // The swapped inverse condition is legal, so swap true and false,
3947 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3952 Legalized = LegalizeSetCCCondCode(
3953 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3956 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3958 // If we expanded the SETCC by inverting the condition code, then swap
3959 // the True/False operands to match.
3961 std::swap(Tmp3, Tmp4);
3963 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3964 // condition code, create a new SELECT_CC node.
3966 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3967 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3969 Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
3970 CC = DAG.getCondCode(ISD::SETNE);
3971 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3972 Tmp2, Tmp3, Tmp4, CC);
3975 Results.push_back(Tmp1);
3979 Tmp1 = Node->getOperand(0); // Chain
3980 Tmp2 = Node->getOperand(2); // LHS
3981 Tmp3 = Node->getOperand(3); // RHS
3982 Tmp4 = Node->getOperand(1); // CC
3984 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3985 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3987 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3989 // If we expanded the SETCC by inverting the condition code, then wrap
3990 // the existing SETCC in a NOT to restore the intended condition.
3992 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
3994 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3996 if (Tmp4.getNode()) {
3997 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3998 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
4000 Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
4001 Tmp4 = DAG.getCondCode(ISD::SETNE);
4002 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
4003 Tmp2, Tmp3, Node->getOperand(4));
4005 Results.push_back(Tmp1);
4008 case ISD::BUILD_VECTOR:
4009 Results.push_back(ExpandBUILD_VECTOR(Node));
4014 // Scalarize vector SRA/SRL/SHL.
4015 EVT VT = Node->getValueType(0);
4016 assert(VT.isVector() && "Unable to legalize non-vector shift");
4017 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
4018 unsigned NumElem = VT.getVectorNumElements();
4020 SmallVector<SDValue, 8> Scalars;
4021 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
4022 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4024 Node->getOperand(0),
4025 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy()));
4026 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4028 Node->getOperand(1),
4029 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy()));
4030 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
4031 VT.getScalarType(), Ex, Sh));
4034 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
4035 ReplaceNode(SDValue(Node, 0), Result);
4038 case ISD::GLOBAL_OFFSET_TABLE:
4039 case ISD::GlobalAddress:
4040 case ISD::GlobalTLSAddress:
4041 case ISD::ExternalSymbol:
4042 case ISD::ConstantPool:
4043 case ISD::JumpTable:
4044 case ISD::INTRINSIC_W_CHAIN:
4045 case ISD::INTRINSIC_WO_CHAIN:
4046 case ISD::INTRINSIC_VOID:
4047 // FIXME: Custom lowering for these operations shouldn't return null!
4051 // Replace the original node with the legalized result.
4052 if (!Results.empty())
4053 ReplaceNode(Node, Results.data());
4056 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4057 SmallVector<SDValue, 8> Results;
4058 MVT OVT = Node->getSimpleValueType(0);
4059 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4060 Node->getOpcode() == ISD::SINT_TO_FP ||
4061 Node->getOpcode() == ISD::SETCC) {
4062 OVT = Node->getOperand(0).getSimpleValueType();
4064 if (Node->getOpcode() == ISD::BR_CC)
4065 OVT = Node->getOperand(2).getSimpleValueType();
4066 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4068 SDValue Tmp1, Tmp2, Tmp3;
4069 switch (Node->getOpcode()) {
4071 case ISD::CTTZ_ZERO_UNDEF:
4073 case ISD::CTLZ_ZERO_UNDEF:
4075 // Zero extend the argument.
4076 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4077 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4078 // already the correct result.
4079 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4080 if (Node->getOpcode() == ISD::CTTZ) {
4081 // FIXME: This should set a bit in the zero extended value instead.
4082 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
4083 Tmp1, DAG.getConstant(NVT.getSizeInBits(), dl, NVT),
4085 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
4086 DAG.getConstant(OVT.getSizeInBits(), dl, NVT), Tmp1);
4087 } else if (Node->getOpcode() == ISD::CTLZ ||
4088 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4089 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4090 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4091 DAG.getConstant(NVT.getSizeInBits() -
4092 OVT.getSizeInBits(), dl, NVT));
4094 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4097 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4098 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4099 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4100 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4101 DAG.getConstant(DiffBits, dl,
4102 TLI.getShiftAmountTy(NVT)));
4103 Results.push_back(Tmp1);
4106 case ISD::FP_TO_UINT:
4107 case ISD::FP_TO_SINT:
4108 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4109 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4110 Results.push_back(Tmp1);
4112 case ISD::UINT_TO_FP:
4113 case ISD::SINT_TO_FP:
4114 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4115 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4116 Results.push_back(Tmp1);
4119 SDValue Chain = Node->getOperand(0); // Get the chain.
4120 SDValue Ptr = Node->getOperand(1); // Get the pointer.
4123 if (OVT.isVector()) {
4124 TruncOp = ISD::BITCAST;
4126 assert(OVT.isInteger()
4127 && "VAARG promotion is supported only for vectors or integer types");
4128 TruncOp = ISD::TRUNCATE;
4131 // Perform the larger operation, then convert back
4132 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4133 Node->getConstantOperandVal(3));
4134 Chain = Tmp1.getValue(1);
4136 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4138 // Modified the chain result - switch anything that used the old chain to
4140 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4141 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4143 UpdatedNodes->insert(Tmp2.getNode());
4144 UpdatedNodes->insert(Chain.getNode());
4152 unsigned ExtOp, TruncOp;
4153 if (OVT.isVector()) {
4154 ExtOp = ISD::BITCAST;
4155 TruncOp = ISD::BITCAST;
4157 assert(OVT.isInteger() && "Cannot promote logic operation");
4158 ExtOp = ISD::ANY_EXTEND;
4159 TruncOp = ISD::TRUNCATE;
4161 // Promote each of the values to the new type.
4162 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4163 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4164 // Perform the larger operation, then convert back
4165 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4166 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4170 unsigned ExtOp, TruncOp;
4171 if (Node->getValueType(0).isVector() ||
4172 Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4173 ExtOp = ISD::BITCAST;
4174 TruncOp = ISD::BITCAST;
4175 } else if (Node->getValueType(0).isInteger()) {
4176 ExtOp = ISD::ANY_EXTEND;
4177 TruncOp = ISD::TRUNCATE;
4179 ExtOp = ISD::FP_EXTEND;
4180 TruncOp = ISD::FP_ROUND;
4182 Tmp1 = Node->getOperand(0);
4183 // Promote each of the values to the new type.
4184 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4185 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4186 // Perform the larger operation, then round down.
4187 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4188 if (TruncOp != ISD::FP_ROUND)
4189 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4191 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4192 DAG.getIntPtrConstant(0, dl));
4193 Results.push_back(Tmp1);
4196 case ISD::VECTOR_SHUFFLE: {
4197 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4199 // Cast the two input vectors.
4200 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4201 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4203 // Convert the shuffle mask to the right # elements.
4204 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4205 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4206 Results.push_back(Tmp1);
4210 unsigned ExtOp = ISD::FP_EXTEND;
4211 if (NVT.isInteger()) {
4212 ISD::CondCode CCCode =
4213 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4214 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4216 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4217 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4218 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4219 Tmp1, Tmp2, Node->getOperand(2)));
4223 unsigned ExtOp = ISD::FP_EXTEND;
4224 if (NVT.isInteger()) {
4225 ISD::CondCode CCCode =
4226 cast<CondCodeSDNode>(Node->getOperand(1))->get();
4227 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4229 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4230 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4231 Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4232 Node->getOperand(0), Node->getOperand(1),
4233 Tmp1, Tmp2, Node->getOperand(4)));
4243 case ISD::FCOPYSIGN:
4245 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4246 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4247 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4248 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4249 Tmp3, DAG.getIntPtrConstant(0, dl)));
4253 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4254 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4255 Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4257 DAG.getNode(ISD::FP_ROUND, dl, OVT,
4258 DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4259 DAG.getIntPtrConstant(0, dl)));
4263 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4264 Tmp2 = Node->getOperand(1);
4265 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4266 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4267 Tmp3, DAG.getIntPtrConstant(0, dl)));
4273 case ISD::FNEARBYINT:
4286 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4287 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4288 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4289 Tmp2, DAG.getIntPtrConstant(0, dl)));
4294 // Replace the original node with the legalized result.
4295 if (!Results.empty())
4296 ReplaceNode(Node, Results.data());
4299 /// This is the entry point for the file.
4300 void SelectionDAG::Legalize() {
4301 AssignTopologicalOrder();
4303 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4304 SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4306 // Visit all the nodes. We start in topological order, so that we see
4307 // nodes with their original operands intact. Legalization can produce
4308 // new nodes which may themselves need to be legalized. Iterate until all
4309 // nodes have been legalized.
4311 bool AnyLegalized = false;
4312 for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4316 if (N->use_empty() && N != getRoot().getNode()) {
4322 if (LegalizedNodes.insert(N).second) {
4323 AnyLegalized = true;
4324 Legalizer.LegalizeOp(N);
4326 if (N->use_empty() && N != getRoot().getNode()) {
4337 // Remove dead nodes now.
4341 bool SelectionDAG::LegalizeOp(SDNode *N,
4342 SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4343 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4344 SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4346 // Directly insert the node in question, and legalize it. This will recurse
4347 // as needed through operands.
4348 LegalizedNodes.insert(N);
4349 Legalizer.LegalizeOp(N);
4351 return LegalizedNodes.count(N);