1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/ADT/DenseSet.h"
28 #include "llvm/ADT/SetOperations.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
31 #include "llvm/CodeGen/LiveStackAnalysis.h"
32 #include "llvm/CodeGen/LiveVariables.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstrBundle.h"
36 #include "llvm/CodeGen/MachineMemOperand.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/IR/BasicBlock.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/raw_ostream.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
51 struct MachineVerifier {
53 MachineVerifier(Pass *pass, const char *b) :
56 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
59 bool runOnMachineFunction(MachineFunction &MF);
63 const char *const OutFileName;
65 const MachineFunction *MF;
66 const TargetMachine *TM;
67 const TargetInstrInfo *TII;
68 const TargetRegisterInfo *TRI;
69 const MachineRegisterInfo *MRI;
73 typedef SmallVector<unsigned, 16> RegVector;
74 typedef SmallVector<const uint32_t*, 4> RegMaskVector;
75 typedef DenseSet<unsigned> RegSet;
76 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
77 typedef SmallPtrSet<const MachineBasicBlock*, 8> BlockSet;
79 const MachineInstr *FirstTerminator;
80 BlockSet FunctionBlocks;
82 BitVector regsReserved;
84 RegVector regsDefined, regsDead, regsKilled;
85 RegMaskVector regMasks;
86 RegSet regsLiveInButUnused;
90 // Add Reg and any sub-registers to RV
91 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
93 if (TargetRegisterInfo::isPhysicalRegister(Reg))
94 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
95 RV.push_back(*SubRegs);
99 // Is this MBB reachable from the MF entry point?
102 // Vregs that must be live in because they are used without being
103 // defined. Map value is the user.
106 // Regs killed in MBB. They may be defined again, and will then be in both
107 // regsKilled and regsLiveOut.
110 // Regs defined in MBB and live out. Note that vregs passing through may
111 // be live out without being mentioned here.
114 // Vregs that pass through MBB untouched. This set is disjoint from
115 // regsKilled and regsLiveOut.
118 // Vregs that must pass through MBB because they are needed by a successor
119 // block. This set is disjoint from regsLiveOut.
120 RegSet vregsRequired;
122 // Set versions of block's predecessor and successor lists.
123 BlockSet Preds, Succs;
125 BBInfo() : reachable(false) {}
127 // Add register to vregsPassed if it belongs there. Return true if
129 bool addPassed(unsigned Reg) {
130 if (!TargetRegisterInfo::isVirtualRegister(Reg))
132 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
134 return vregsPassed.insert(Reg).second;
137 // Same for a full set.
138 bool addPassed(const RegSet &RS) {
139 bool changed = false;
140 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
146 // Add register to vregsRequired if it belongs there. Return true if
148 bool addRequired(unsigned Reg) {
149 if (!TargetRegisterInfo::isVirtualRegister(Reg))
151 if (regsLiveOut.count(Reg))
153 return vregsRequired.insert(Reg).second;
156 // Same for a full set.
157 bool addRequired(const RegSet &RS) {
158 bool changed = false;
159 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
165 // Same for a full map.
166 bool addRequired(const RegMap &RM) {
167 bool changed = false;
168 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
169 if (addRequired(I->first))
174 // Live-out registers are either in regsLiveOut or vregsPassed.
175 bool isLiveOut(unsigned Reg) const {
176 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
180 // Extra register info per MBB.
181 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
183 bool isReserved(unsigned Reg) {
184 return Reg < regsReserved.size() && regsReserved.test(Reg);
187 bool isAllocatable(unsigned Reg) {
188 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg);
191 // Analysis information if available
192 LiveVariables *LiveVars;
193 LiveIntervals *LiveInts;
194 LiveStacks *LiveStks;
195 SlotIndexes *Indexes;
197 void visitMachineFunctionBefore();
198 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
199 void visitMachineBundleBefore(const MachineInstr *MI);
200 void visitMachineInstrBefore(const MachineInstr *MI);
201 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
202 void visitMachineInstrAfter(const MachineInstr *MI);
203 void visitMachineBundleAfter(const MachineInstr *MI);
204 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
205 void visitMachineFunctionAfter();
207 void report(const char *msg, const MachineFunction *MF);
208 void report(const char *msg, const MachineBasicBlock *MBB);
209 void report(const char *msg, const MachineInstr *MI);
210 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
211 void report(const char *msg, const MachineFunction *MF,
212 const LiveInterval &LI);
213 void report(const char *msg, const MachineBasicBlock *MBB,
214 const LiveInterval &LI);
216 void verifyInlineAsm(const MachineInstr *MI);
218 void checkLiveness(const MachineOperand *MO, unsigned MONum);
219 void markReachable(const MachineBasicBlock *MBB);
220 void calcRegsPassed();
221 void checkPHIOps(const MachineBasicBlock *MBB);
223 void calcRegsRequired();
224 void verifyLiveVariables();
225 void verifyLiveIntervals();
226 void verifyLiveInterval(const LiveInterval&);
227 void verifyLiveIntervalValue(const LiveInterval&, VNInfo*);
228 void verifyLiveIntervalSegment(const LiveInterval&,
229 LiveInterval::const_iterator);
232 struct MachineVerifierPass : public MachineFunctionPass {
233 static char ID; // Pass ID, replacement for typeid
234 const char *const Banner;
236 MachineVerifierPass(const char *b = 0)
237 : MachineFunctionPass(ID), Banner(b) {
238 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
241 void getAnalysisUsage(AnalysisUsage &AU) const {
242 AU.setPreservesAll();
243 MachineFunctionPass::getAnalysisUsage(AU);
246 bool runOnMachineFunction(MachineFunction &MF) {
247 MF.verify(this, Banner);
254 char MachineVerifierPass::ID = 0;
255 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
256 "Verify generated machine code", false, false)
258 FunctionPass *llvm::createMachineVerifierPass(const char *Banner) {
259 return new MachineVerifierPass(Banner);
262 void MachineFunction::verify(Pass *p, const char *Banner) const {
263 MachineVerifier(p, Banner)
264 .runOnMachineFunction(const_cast<MachineFunction&>(*this));
267 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
268 raw_ostream *OutFile = 0;
270 std::string ErrorInfo;
271 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
272 raw_fd_ostream::F_Append);
273 if (!ErrorInfo.empty()) {
274 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
286 TM = &MF.getTarget();
287 TII = TM->getInstrInfo();
288 TRI = TM->getRegisterInfo();
289 MRI = &MF.getRegInfo();
296 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
297 // We don't want to verify LiveVariables if LiveIntervals is available.
299 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
300 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
301 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
304 visitMachineFunctionBefore();
305 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
307 visitMachineBasicBlockBefore(MFI);
308 // Keep track of the current bundle header.
309 const MachineInstr *CurBundle = 0;
310 // Do we expect the next instruction to be part of the same bundle?
311 bool InBundle = false;
313 for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
314 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
315 if (MBBI->getParent() != MFI) {
316 report("Bad instruction parent pointer", MFI);
317 *OS << "Instruction: " << *MBBI;
321 // Check for consistent bundle flags.
322 if (InBundle && !MBBI->isBundledWithPred())
323 report("Missing BundledPred flag, "
324 "BundledSucc was set on predecessor", MBBI);
325 if (!InBundle && MBBI->isBundledWithPred())
326 report("BundledPred flag is set, "
327 "but BundledSucc not set on predecessor", MBBI);
329 // Is this a bundle header?
330 if (!MBBI->isInsideBundle()) {
332 visitMachineBundleAfter(CurBundle);
334 visitMachineBundleBefore(CurBundle);
335 } else if (!CurBundle)
336 report("No bundle header", MBBI);
337 visitMachineInstrBefore(MBBI);
338 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
339 visitMachineOperand(&MBBI->getOperand(I), I);
340 visitMachineInstrAfter(MBBI);
342 // Was this the last bundled instruction?
343 InBundle = MBBI->isBundledWithSucc();
346 visitMachineBundleAfter(CurBundle);
348 report("BundledSucc flag set on last instruction in block", &MFI->back());
349 visitMachineBasicBlockAfter(MFI);
351 visitMachineFunctionAfter();
355 else if (foundErrors)
356 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
364 regsLiveInButUnused.clear();
367 return false; // no changes
370 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
373 if (!foundErrors++) {
375 *OS << "# " << Banner << '\n';
376 MF->print(*OS, Indexes);
378 *OS << "*** Bad machine code: " << msg << " ***\n"
379 << "- function: " << MF->getName() << "\n";
382 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
384 report(msg, MBB->getParent());
385 *OS << "- basic block: BB#" << MBB->getNumber()
386 << ' ' << MBB->getName()
387 << " (" << (const void*)MBB << ')';
389 *OS << " [" << Indexes->getMBBStartIdx(MBB)
390 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
394 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
396 report(msg, MI->getParent());
397 *OS << "- instruction: ";
398 if (Indexes && Indexes->hasIndex(MI))
399 *OS << Indexes->getInstructionIndex(MI) << '\t';
403 void MachineVerifier::report(const char *msg,
404 const MachineOperand *MO, unsigned MONum) {
406 report(msg, MO->getParent());
407 *OS << "- operand " << MONum << ": ";
412 void MachineVerifier::report(const char *msg, const MachineFunction *MF,
413 const LiveInterval &LI) {
415 *OS << "- interval: ";
416 if (TargetRegisterInfo::isVirtualRegister(LI.reg))
417 *OS << PrintReg(LI.reg, TRI);
419 *OS << PrintRegUnit(LI.reg, TRI);
420 *OS << ' ' << LI << '\n';
423 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
424 const LiveInterval &LI) {
426 *OS << "- interval: ";
427 if (TargetRegisterInfo::isVirtualRegister(LI.reg))
428 *OS << PrintReg(LI.reg, TRI);
430 *OS << PrintRegUnit(LI.reg, TRI);
431 *OS << ' ' << LI << '\n';
434 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
435 BBInfo &MInfo = MBBInfoMap[MBB];
436 if (!MInfo.reachable) {
437 MInfo.reachable = true;
438 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
439 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
444 void MachineVerifier::visitMachineFunctionBefore() {
445 lastIndex = SlotIndex();
446 regsReserved = MRI->getReservedRegs();
448 // A sub-register of a reserved register is also reserved
449 for (int Reg = regsReserved.find_first(); Reg>=0;
450 Reg = regsReserved.find_next(Reg)) {
451 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
452 // FIXME: This should probably be:
453 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
454 regsReserved.set(*SubRegs);
458 markReachable(&MF->front());
460 // Build a set of the basic blocks in the function.
461 FunctionBlocks.clear();
462 for (MachineFunction::const_iterator
463 I = MF->begin(), E = MF->end(); I != E; ++I) {
464 FunctionBlocks.insert(I);
465 BBInfo &MInfo = MBBInfoMap[I];
467 MInfo.Preds.insert(I->pred_begin(), I->pred_end());
468 if (MInfo.Preds.size() != I->pred_size())
469 report("MBB has duplicate entries in its predecessor list.", I);
471 MInfo.Succs.insert(I->succ_begin(), I->succ_end());
472 if (MInfo.Succs.size() != I->succ_size())
473 report("MBB has duplicate entries in its successor list.", I);
476 // Check that the register use lists are sane.
477 MRI->verifyUseLists();
480 // Does iterator point to a and b as the first two elements?
481 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
482 const MachineBasicBlock *a, const MachineBasicBlock *b) {
491 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
495 // If this block has allocatable physical registers live-in, check that
496 // it is an entry block or landing pad.
497 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
498 LE = MBB->livein_end();
501 if (isAllocatable(reg) && !MBB->isLandingPad() &&
502 MBB != MBB->getParent()->begin()) {
503 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
508 // Count the number of landing pad successors.
509 SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
510 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
511 E = MBB->succ_end(); I != E; ++I) {
512 if ((*I)->isLandingPad())
513 LandingPadSuccs.insert(*I);
514 if (!FunctionBlocks.count(*I))
515 report("MBB has successor that isn't part of the function.", MBB);
516 if (!MBBInfoMap[*I].Preds.count(MBB)) {
517 report("Inconsistent CFG", MBB);
518 *OS << "MBB is not in the predecessor list of the successor BB#"
519 << (*I)->getNumber() << ".\n";
523 // Check the predecessor list.
524 for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
525 E = MBB->pred_end(); I != E; ++I) {
526 if (!FunctionBlocks.count(*I))
527 report("MBB has predecessor that isn't part of the function.", MBB);
528 if (!MBBInfoMap[*I].Succs.count(MBB)) {
529 report("Inconsistent CFG", MBB);
530 *OS << "MBB is not in the successor list of the predecessor BB#"
531 << (*I)->getNumber() << ".\n";
535 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
536 const BasicBlock *BB = MBB->getBasicBlock();
537 if (LandingPadSuccs.size() > 1 &&
539 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
540 BB && isa<SwitchInst>(BB->getTerminator())))
541 report("MBB has more than one landing pad successor", MBB);
543 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
544 MachineBasicBlock *TBB = 0, *FBB = 0;
545 SmallVector<MachineOperand, 4> Cond;
546 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
548 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
549 // check whether its answers match up with reality.
551 // Block falls through to its successor.
552 MachineFunction::const_iterator MBBI = MBB;
554 if (MBBI == MF->end()) {
555 // It's possible that the block legitimately ends with a noreturn
556 // call or an unreachable, in which case it won't actually fall
557 // out the bottom of the function.
558 } else if (MBB->succ_size() == LandingPadSuccs.size()) {
559 // It's possible that the block legitimately ends with a noreturn
560 // call or an unreachable, in which case it won't actuall fall
562 } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
563 report("MBB exits via unconditional fall-through but doesn't have "
564 "exactly one CFG successor!", MBB);
565 } else if (!MBB->isSuccessor(MBBI)) {
566 report("MBB exits via unconditional fall-through but its successor "
567 "differs from its CFG successor!", MBB);
569 if (!MBB->empty() && getBundleStart(&MBB->back())->isBarrier() &&
570 !TII->isPredicated(getBundleStart(&MBB->back()))) {
571 report("MBB exits via unconditional fall-through but ends with a "
572 "barrier instruction!", MBB);
575 report("MBB exits via unconditional fall-through but has a condition!",
578 } else if (TBB && !FBB && Cond.empty()) {
579 // Block unconditionally branches somewhere.
580 if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
581 report("MBB exits via unconditional branch but doesn't have "
582 "exactly one CFG successor!", MBB);
583 } else if (!MBB->isSuccessor(TBB)) {
584 report("MBB exits via unconditional branch but the CFG "
585 "successor doesn't match the actual successor!", MBB);
588 report("MBB exits via unconditional branch but doesn't contain "
589 "any instructions!", MBB);
590 } else if (!getBundleStart(&MBB->back())->isBarrier()) {
591 report("MBB exits via unconditional branch but doesn't end with a "
592 "barrier instruction!", MBB);
593 } else if (!getBundleStart(&MBB->back())->isTerminator()) {
594 report("MBB exits via unconditional branch but the branch isn't a "
595 "terminator instruction!", MBB);
597 } else if (TBB && !FBB && !Cond.empty()) {
598 // Block conditionally branches somewhere, otherwise falls through.
599 MachineFunction::const_iterator MBBI = MBB;
601 if (MBBI == MF->end()) {
602 report("MBB conditionally falls through out of function!", MBB);
603 } else if (MBB->succ_size() == 1) {
604 // A conditional branch with only one successor is weird, but allowed.
606 report("MBB exits via conditional branch/fall-through but only has "
607 "one CFG successor!", MBB);
608 else if (TBB != *MBB->succ_begin())
609 report("MBB exits via conditional branch/fall-through but the CFG "
610 "successor don't match the actual successor!", MBB);
611 } else if (MBB->succ_size() != 2) {
612 report("MBB exits via conditional branch/fall-through but doesn't have "
613 "exactly two CFG successors!", MBB);
614 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
615 report("MBB exits via conditional branch/fall-through but the CFG "
616 "successors don't match the actual successors!", MBB);
619 report("MBB exits via conditional branch/fall-through but doesn't "
620 "contain any instructions!", MBB);
621 } else if (getBundleStart(&MBB->back())->isBarrier()) {
622 report("MBB exits via conditional branch/fall-through but ends with a "
623 "barrier instruction!", MBB);
624 } else if (!getBundleStart(&MBB->back())->isTerminator()) {
625 report("MBB exits via conditional branch/fall-through but the branch "
626 "isn't a terminator instruction!", MBB);
628 } else if (TBB && FBB) {
629 // Block conditionally branches somewhere, otherwise branches
631 if (MBB->succ_size() == 1) {
632 // A conditional branch with only one successor is weird, but allowed.
634 report("MBB exits via conditional branch/branch through but only has "
635 "one CFG successor!", MBB);
636 else if (TBB != *MBB->succ_begin())
637 report("MBB exits via conditional branch/branch through but the CFG "
638 "successor don't match the actual successor!", MBB);
639 } else if (MBB->succ_size() != 2) {
640 report("MBB exits via conditional branch/branch but doesn't have "
641 "exactly two CFG successors!", MBB);
642 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
643 report("MBB exits via conditional branch/branch but the CFG "
644 "successors don't match the actual successors!", MBB);
647 report("MBB exits via conditional branch/branch but doesn't "
648 "contain any instructions!", MBB);
649 } else if (!getBundleStart(&MBB->back())->isBarrier()) {
650 report("MBB exits via conditional branch/branch but doesn't end with a "
651 "barrier instruction!", MBB);
652 } else if (!getBundleStart(&MBB->back())->isTerminator()) {
653 report("MBB exits via conditional branch/branch but the branch "
654 "isn't a terminator instruction!", MBB);
657 report("MBB exits via conditinal branch/branch but there's no "
661 report("AnalyzeBranch returned invalid data!", MBB);
666 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
667 E = MBB->livein_end(); I != E; ++I) {
668 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
669 report("MBB live-in list contains non-physical register", MBB);
672 for (MCSubRegIterator SubRegs(*I, TRI, /*IncludeSelf=*/true);
673 SubRegs.isValid(); ++SubRegs)
674 regsLive.insert(*SubRegs);
676 regsLiveInButUnused = regsLive;
678 const MachineFrameInfo *MFI = MF->getFrameInfo();
679 assert(MFI && "Function has no frame info");
680 BitVector PR = MFI->getPristineRegs(MBB);
681 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
682 for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
683 SubRegs.isValid(); ++SubRegs)
684 regsLive.insert(*SubRegs);
691 lastIndex = Indexes->getMBBStartIdx(MBB);
694 // This function gets called for all bundle headers, including normal
695 // stand-alone unbundled instructions.
696 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
697 if (Indexes && Indexes->hasIndex(MI)) {
698 SlotIndex idx = Indexes->getInstructionIndex(MI);
699 if (!(idx > lastIndex)) {
700 report("Instruction index out of order", MI);
701 *OS << "Last instruction was at " << lastIndex << '\n';
706 // Ensure non-terminators don't follow terminators.
707 // Ignore predicated terminators formed by if conversion.
708 // FIXME: If conversion shouldn't need to violate this rule.
709 if (MI->isTerminator() && !TII->isPredicated(MI)) {
710 if (!FirstTerminator)
711 FirstTerminator = MI;
712 } else if (FirstTerminator) {
713 report("Non-terminator instruction after the first terminator", MI);
714 *OS << "First terminator was:\t" << *FirstTerminator;
718 // The operands on an INLINEASM instruction must follow a template.
719 // Verify that the flag operands make sense.
720 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
721 // The first two operands on INLINEASM are the asm string and global flags.
722 if (MI->getNumOperands() < 2) {
723 report("Too few operands on inline asm", MI);
726 if (!MI->getOperand(0).isSymbol())
727 report("Asm string must be an external symbol", MI);
728 if (!MI->getOperand(1).isImm())
729 report("Asm flags must be an immediate", MI);
730 // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
731 // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16.
732 if (!isUInt<5>(MI->getOperand(1).getImm()))
733 report("Unknown asm flags", &MI->getOperand(1), 1);
735 assert(InlineAsm::MIOp_FirstOperand == 2 && "Asm format changed");
737 unsigned OpNo = InlineAsm::MIOp_FirstOperand;
739 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
740 const MachineOperand &MO = MI->getOperand(OpNo);
741 // There may be implicit ops after the fixed operands.
744 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
747 if (OpNo > MI->getNumOperands())
748 report("Missing operands in last group", MI);
750 // An optional MDNode follows the groups.
751 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
754 // All trailing operands must be implicit registers.
755 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
756 const MachineOperand &MO = MI->getOperand(OpNo);
757 if (!MO.isReg() || !MO.isImplicit())
758 report("Expected implicit register after groups", &MO, OpNo);
762 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
763 const MCInstrDesc &MCID = MI->getDesc();
764 if (MI->getNumOperands() < MCID.getNumOperands()) {
765 report("Too few operands", MI);
766 *OS << MCID.getNumOperands() << " operands expected, but "
767 << MI->getNumExplicitOperands() << " given.\n";
770 // Check the tied operands.
771 if (MI->isInlineAsm())
774 // Check the MachineMemOperands for basic consistency.
775 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
776 E = MI->memoperands_end(); I != E; ++I) {
777 if ((*I)->isLoad() && !MI->mayLoad())
778 report("Missing mayLoad flag", MI);
779 if ((*I)->isStore() && !MI->mayStore())
780 report("Missing mayStore flag", MI);
783 // Debug values must not have a slot index.
784 // Other instructions must have one, unless they are inside a bundle.
786 bool mapped = !LiveInts->isNotInMIMap(MI);
787 if (MI->isDebugValue()) {
789 report("Debug instruction has a slot index", MI);
790 } else if (MI->isInsideBundle()) {
792 report("Instruction inside bundle has a slot index", MI);
795 report("Missing slot index", MI);
800 if (!TII->verifyInstruction(MI, ErrorInfo))
801 report(ErrorInfo.data(), MI);
805 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
806 const MachineInstr *MI = MO->getParent();
807 const MCInstrDesc &MCID = MI->getDesc();
809 // The first MCID.NumDefs operands must be explicit register defines
810 if (MONum < MCID.getNumDefs()) {
811 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
813 report("Explicit definition must be a register", MO, MONum);
814 else if (!MO->isDef() && !MCOI.isOptionalDef())
815 report("Explicit definition marked as use", MO, MONum);
816 else if (MO->isImplicit())
817 report("Explicit definition marked as implicit", MO, MONum);
818 } else if (MONum < MCID.getNumOperands()) {
819 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
820 // Don't check if it's the last operand in a variadic instruction. See,
821 // e.g., LDM_RET in the arm back end.
823 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
824 if (MO->isDef() && !MCOI.isOptionalDef())
825 report("Explicit operand marked as def", MO, MONum);
826 if (MO->isImplicit())
827 report("Explicit operand marked as implicit", MO, MONum);
830 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
833 report("Tied use must be a register", MO, MONum);
834 else if (!MO->isTied())
835 report("Operand should be tied", MO, MONum);
836 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
837 report("Tied def doesn't match MCInstrDesc", MO, MONum);
838 } else if (MO->isReg() && MO->isTied())
839 report("Explicit operand should not be tied", MO, MONum);
841 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
842 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
843 report("Extra explicit operand on non-variadic instruction", MO, MONum);
846 switch (MO->getType()) {
847 case MachineOperand::MO_Register: {
848 const unsigned Reg = MO->getReg();
851 if (MRI->tracksLiveness() && !MI->isDebugValue())
852 checkLiveness(MO, MONum);
854 // Verify the consistency of tied operands.
856 unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
857 const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
858 if (!OtherMO.isReg())
859 report("Must be tied to a register", MO, MONum);
860 if (!OtherMO.isTied())
861 report("Missing tie flags on tied operand", MO, MONum);
862 if (MI->findTiedOperandIdx(OtherIdx) != MONum)
863 report("Inconsistent tie links", MO, MONum);
864 if (MONum < MCID.getNumDefs()) {
865 if (OtherIdx < MCID.getNumOperands()) {
866 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
867 report("Explicit def tied to explicit use without tie constraint",
870 if (!OtherMO.isImplicit())
871 report("Explicit def should be tied to implicit use", MO, MONum);
876 // Verify two-address constraints after leaving SSA form.
878 if (!MRI->isSSA() && MO->isUse() &&
879 MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
880 Reg != MI->getOperand(DefIdx).getReg())
881 report("Two-address instruction operands must be identical", MO, MONum);
883 // Check register classes.
884 if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
885 unsigned SubIdx = MO->getSubReg();
887 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
889 report("Illegal subregister index for physical register", MO, MONum);
892 if (const TargetRegisterClass *DRC =
893 TII->getRegClass(MCID, MONum, TRI, *MF)) {
894 if (!DRC->contains(Reg)) {
895 report("Illegal physical register for instruction", MO, MONum);
896 *OS << TRI->getName(Reg) << " is not a "
897 << DRC->getName() << " register.\n";
902 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
904 const TargetRegisterClass *SRC =
905 TRI->getSubClassWithSubReg(RC, SubIdx);
907 report("Invalid subregister index for virtual register", MO, MONum);
908 *OS << "Register class " << RC->getName()
909 << " does not support subreg index " << SubIdx << "\n";
913 report("Invalid register class for subregister index", MO, MONum);
914 *OS << "Register class " << RC->getName()
915 << " does not fully support subreg index " << SubIdx << "\n";
919 if (const TargetRegisterClass *DRC =
920 TII->getRegClass(MCID, MONum, TRI, *MF)) {
922 const TargetRegisterClass *SuperRC =
923 TRI->getLargestLegalSuperClass(RC);
925 report("No largest legal super class exists.", MO, MONum);
928 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
930 report("No matching super-reg register class.", MO, MONum);
934 if (!RC->hasSuperClassEq(DRC)) {
935 report("Illegal virtual register for instruction", MO, MONum);
936 *OS << "Expected a " << DRC->getName() << " register, but got a "
937 << RC->getName() << " register\n";
945 case MachineOperand::MO_RegisterMask:
946 regMasks.push_back(MO->getRegMask());
949 case MachineOperand::MO_MachineBasicBlock:
950 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
951 report("PHI operand is not in the CFG", MO, MONum);
954 case MachineOperand::MO_FrameIndex:
955 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
956 LiveInts && !LiveInts->isNotInMIMap(MI)) {
957 LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
958 SlotIndex Idx = LiveInts->getInstructionIndex(MI);
959 if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
960 report("Instruction loads from dead spill slot", MO, MONum);
961 *OS << "Live stack: " << LI << '\n';
963 if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) {
964 report("Instruction stores to dead spill slot", MO, MONum);
965 *OS << "Live stack: " << LI << '\n';
975 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
976 const MachineInstr *MI = MO->getParent();
977 const unsigned Reg = MO->getReg();
979 // Both use and def operands can read a register.
980 if (MO->readsReg()) {
981 regsLiveInButUnused.erase(Reg);
984 addRegWithSubRegs(regsKilled, Reg);
986 // Check that LiveVars knows this kill.
987 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
989 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
990 if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end())
991 report("Kill missing from LiveVariables", MO, MONum);
994 // Check LiveInts liveness and kill.
995 if (LiveInts && !LiveInts->isNotInMIMap(MI)) {
996 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI);
997 // Check the cached regunit intervals.
998 if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
999 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1000 if (const LiveInterval *LI = LiveInts->getCachedRegUnit(*Units)) {
1001 LiveRangeQuery LRQ(*LI, UseIdx);
1002 if (!LRQ.valueIn()) {
1003 report("No live range at use", MO, MONum);
1004 *OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
1005 << ' ' << *LI << '\n';
1007 if (MO->isKill() && !LRQ.isKill()) {
1008 report("Live range continues after kill flag", MO, MONum);
1009 *OS << PrintRegUnit(*Units, TRI) << ' ' << *LI << '\n';
1015 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1016 if (LiveInts->hasInterval(Reg)) {
1017 // This is a virtual register interval.
1018 const LiveInterval &LI = LiveInts->getInterval(Reg);
1019 LiveRangeQuery LRQ(LI, UseIdx);
1020 if (!LRQ.valueIn()) {
1021 report("No live range at use", MO, MONum);
1022 *OS << UseIdx << " is not live in " << LI << '\n';
1024 // Check for extra kill flags.
1025 // Note that we allow missing kill flags for now.
1026 if (MO->isKill() && !LRQ.isKill()) {
1027 report("Live range continues after kill flag", MO, MONum);
1028 *OS << "Live range: " << LI << '\n';
1031 report("Virtual register has no live interval", MO, MONum);
1036 // Use of a dead register.
1037 if (!regsLive.count(Reg)) {
1038 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1039 // Reserved registers may be used even when 'dead'.
1040 if (!isReserved(Reg))
1041 report("Using an undefined physical register", MO, MONum);
1042 } else if (MRI->def_empty(Reg)) {
1043 report("Reading virtual register without a def", MO, MONum);
1045 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1046 // We don't know which virtual registers are live in, so only complain
1047 // if vreg was killed in this MBB. Otherwise keep track of vregs that
1048 // must be live in. PHI instructions are handled separately.
1049 if (MInfo.regsKilled.count(Reg))
1050 report("Using a killed virtual register", MO, MONum);
1051 else if (!MI->isPHI())
1052 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
1058 // Register defined.
1059 // TODO: verify that earlyclobber ops are not used.
1061 addRegWithSubRegs(regsDead, Reg);
1063 addRegWithSubRegs(regsDefined, Reg);
1066 if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
1067 llvm::next(MRI->def_begin(Reg)) != MRI->def_end())
1068 report("Multiple virtual register defs in SSA form", MO, MONum);
1070 // Check LiveInts for a live range, but only for virtual registers.
1071 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
1072 !LiveInts->isNotInMIMap(MI)) {
1073 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI);
1074 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
1075 if (LiveInts->hasInterval(Reg)) {
1076 const LiveInterval &LI = LiveInts->getInterval(Reg);
1077 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
1078 assert(VNI && "NULL valno is not allowed");
1079 if (VNI->def != DefIdx) {
1080 report("Inconsistent valno->def", MO, MONum);
1081 *OS << "Valno " << VNI->id << " is not defined at "
1082 << DefIdx << " in " << LI << '\n';
1085 report("No live range at def", MO, MONum);
1086 *OS << DefIdx << " is not live in " << LI << '\n';
1089 report("Virtual register has no Live interval", MO, MONum);
1095 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
1098 // This function gets called after visiting all instructions in a bundle. The
1099 // argument points to the bundle header.
1100 // Normal stand-alone instructions are also considered 'bundles', and this
1101 // function is called for all of them.
1102 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
1103 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1104 set_union(MInfo.regsKilled, regsKilled);
1105 set_subtract(regsLive, regsKilled); regsKilled.clear();
1106 // Kill any masked registers.
1107 while (!regMasks.empty()) {
1108 const uint32_t *Mask = regMasks.pop_back_val();
1109 for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
1110 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
1111 MachineOperand::clobbersPhysReg(Mask, *I))
1112 regsDead.push_back(*I);
1114 set_subtract(regsLive, regsDead); regsDead.clear();
1115 set_union(regsLive, regsDefined); regsDefined.clear();
1119 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
1120 MBBInfoMap[MBB].regsLiveOut = regsLive;
1124 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
1125 if (!(stop > lastIndex)) {
1126 report("Block ends before last instruction index", MBB);
1127 *OS << "Block ends at " << stop
1128 << " last instruction was at " << lastIndex << '\n';
1134 // Calculate the largest possible vregsPassed sets. These are the registers that
1135 // can pass through an MBB live, but may not be live every time. It is assumed
1136 // that all vregsPassed sets are empty before the call.
1137 void MachineVerifier::calcRegsPassed() {
1138 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
1139 // have any vregsPassed.
1140 SmallPtrSet<const MachineBasicBlock*, 8> todo;
1141 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1142 MFI != MFE; ++MFI) {
1143 const MachineBasicBlock &MBB(*MFI);
1144 BBInfo &MInfo = MBBInfoMap[&MBB];
1145 if (!MInfo.reachable)
1147 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
1148 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
1149 BBInfo &SInfo = MBBInfoMap[*SuI];
1150 if (SInfo.addPassed(MInfo.regsLiveOut))
1155 // Iteratively push vregsPassed to successors. This will converge to the same
1156 // final state regardless of DenseSet iteration order.
1157 while (!todo.empty()) {
1158 const MachineBasicBlock *MBB = *todo.begin();
1160 BBInfo &MInfo = MBBInfoMap[MBB];
1161 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
1162 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
1165 BBInfo &SInfo = MBBInfoMap[*SuI];
1166 if (SInfo.addPassed(MInfo.vregsPassed))
1172 // Calculate the set of virtual registers that must be passed through each basic
1173 // block in order to satisfy the requirements of successor blocks. This is very
1174 // similar to calcRegsPassed, only backwards.
1175 void MachineVerifier::calcRegsRequired() {
1176 // First push live-in regs to predecessors' vregsRequired.
1177 SmallPtrSet<const MachineBasicBlock*, 8> todo;
1178 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1179 MFI != MFE; ++MFI) {
1180 const MachineBasicBlock &MBB(*MFI);
1181 BBInfo &MInfo = MBBInfoMap[&MBB];
1182 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
1183 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
1184 BBInfo &PInfo = MBBInfoMap[*PrI];
1185 if (PInfo.addRequired(MInfo.vregsLiveIn))
1190 // Iteratively push vregsRequired to predecessors. This will converge to the
1191 // same final state regardless of DenseSet iteration order.
1192 while (!todo.empty()) {
1193 const MachineBasicBlock *MBB = *todo.begin();
1195 BBInfo &MInfo = MBBInfoMap[MBB];
1196 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1197 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1200 BBInfo &SInfo = MBBInfoMap[*PrI];
1201 if (SInfo.addRequired(MInfo.vregsRequired))
1207 // Check PHI instructions at the beginning of MBB. It is assumed that
1208 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
1209 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
1210 SmallPtrSet<const MachineBasicBlock*, 8> seen;
1211 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
1212 BBI != BBE && BBI->isPHI(); ++BBI) {
1215 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
1216 unsigned Reg = BBI->getOperand(i).getReg();
1217 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
1218 if (!Pre->isSuccessor(MBB))
1221 BBInfo &PrInfo = MBBInfoMap[Pre];
1222 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
1223 report("PHI operand is not live-out from predecessor",
1224 &BBI->getOperand(i), i);
1227 // Did we see all predecessors?
1228 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1229 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1230 if (!seen.count(*PrI)) {
1231 report("Missing PHI operand", BBI);
1232 *OS << "BB#" << (*PrI)->getNumber()
1233 << " is a predecessor according to the CFG.\n";
1239 void MachineVerifier::visitMachineFunctionAfter() {
1242 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1243 MFI != MFE; ++MFI) {
1244 BBInfo &MInfo = MBBInfoMap[MFI];
1246 // Skip unreachable MBBs.
1247 if (!MInfo.reachable)
1253 // Now check liveness info if available
1256 // Check for killed virtual registers that should be live out.
1257 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1258 MFI != MFE; ++MFI) {
1259 BBInfo &MInfo = MBBInfoMap[MFI];
1260 for (RegSet::iterator
1261 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1263 if (MInfo.regsKilled.count(*I)) {
1264 report("Virtual register killed in block, but needed live out.", MFI);
1265 *OS << "Virtual register " << PrintReg(*I)
1266 << " is used after the block.\n";
1271 BBInfo &MInfo = MBBInfoMap[&MF->front()];
1272 for (RegSet::iterator
1273 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1275 report("Virtual register def doesn't dominate all uses.",
1276 MRI->getVRegDef(*I));
1280 verifyLiveVariables();
1282 verifyLiveIntervals();
1285 void MachineVerifier::verifyLiveVariables() {
1286 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
1287 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1288 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1289 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1290 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1291 MFI != MFE; ++MFI) {
1292 BBInfo &MInfo = MBBInfoMap[MFI];
1294 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
1295 if (MInfo.vregsRequired.count(Reg)) {
1296 if (!VI.AliveBlocks.test(MFI->getNumber())) {
1297 report("LiveVariables: Block missing from AliveBlocks", MFI);
1298 *OS << "Virtual register " << PrintReg(Reg)
1299 << " must be live through the block.\n";
1302 if (VI.AliveBlocks.test(MFI->getNumber())) {
1303 report("LiveVariables: Block should not be in AliveBlocks", MFI);
1304 *OS << "Virtual register " << PrintReg(Reg)
1305 << " is not needed live through the block.\n";
1312 void MachineVerifier::verifyLiveIntervals() {
1313 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
1314 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1315 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1317 // Spilling and splitting may leave unused registers around. Skip them.
1318 if (MRI->reg_nodbg_empty(Reg))
1321 if (!LiveInts->hasInterval(Reg)) {
1322 report("Missing live interval for virtual register", MF);
1323 *OS << PrintReg(Reg, TRI) << " still has defs or uses\n";
1327 const LiveInterval &LI = LiveInts->getInterval(Reg);
1328 assert(Reg == LI.reg && "Invalid reg to interval mapping");
1329 verifyLiveInterval(LI);
1332 // Verify all the cached regunit intervals.
1333 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
1334 if (const LiveInterval *LI = LiveInts->getCachedRegUnit(i))
1335 verifyLiveInterval(*LI);
1338 void MachineVerifier::verifyLiveIntervalValue(const LiveInterval &LI,
1340 if (VNI->isUnused())
1343 const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
1346 report("Valno not live at def and not marked unused", MF, LI);
1347 *OS << "Valno #" << VNI->id << '\n';
1351 if (DefVNI != VNI) {
1352 report("Live range at def has different valno", MF, LI);
1353 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1354 << " where valno #" << DefVNI->id << " is live\n";
1358 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
1360 report("Invalid definition index", MF, LI);
1361 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1362 << " in " << LI << '\n';
1366 if (VNI->isPHIDef()) {
1367 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
1368 report("PHIDef value is not defined at MBB start", MBB, LI);
1369 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1370 << ", not at the beginning of BB#" << MBB->getNumber() << '\n';
1376 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
1378 report("No instruction at def index", MBB, LI);
1379 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1383 bool hasDef = false;
1384 bool isEarlyClobber = false;
1385 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1386 if (!MOI->isReg() || !MOI->isDef())
1388 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1389 if (MOI->getReg() != LI.reg)
1392 if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
1393 !TRI->hasRegUnit(MOI->getReg(), LI.reg))
1397 if (MOI->isEarlyClobber())
1398 isEarlyClobber = true;
1402 report("Defining instruction does not modify register", MI);
1403 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
1406 // Early clobber defs begin at USE slots, but other defs must begin at
1408 if (isEarlyClobber) {
1409 if (!VNI->def.isEarlyClobber()) {
1410 report("Early clobber def must be at an early-clobber slot", MBB, LI);
1411 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1413 } else if (!VNI->def.isRegister()) {
1414 report("Non-PHI, non-early clobber def must be at a register slot",
1416 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1421 MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI,
1422 LiveInterval::const_iterator I) {
1423 const VNInfo *VNI = I->valno;
1424 assert(VNI && "Live range has no valno");
1426 if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
1427 report("Foreign valno in live range", MF, LI);
1428 *OS << *I << " has a bad valno\n";
1431 if (VNI->isUnused()) {
1432 report("Live range valno is marked unused", MF, LI);
1436 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start);
1438 report("Bad start of live segment, no basic block", MF, LI);
1442 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1443 if (I->start != MBBStartIdx && I->start != VNI->def) {
1444 report("Live segment must begin at MBB entry or valno def", MBB, LI);
1448 const MachineBasicBlock *EndMBB =
1449 LiveInts->getMBBFromIndex(I->end.getPrevSlot());
1451 report("Bad end of live segment, no basic block", MF, LI);
1456 // No more checks for live-out segments.
1457 if (I->end == LiveInts->getMBBEndIdx(EndMBB))
1460 // RegUnit intervals are allowed dead phis.
1461 if (!TargetRegisterInfo::isVirtualRegister(LI.reg) && VNI->isPHIDef() &&
1462 I->start == VNI->def && I->end == VNI->def.getDeadSlot())
1465 // The live segment is ending inside EndMBB
1466 const MachineInstr *MI =
1467 LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
1469 report("Live segment doesn't end at a valid instruction", EndMBB, LI);
1474 // The block slot must refer to a basic block boundary.
1475 if (I->end.isBlock()) {
1476 report("Live segment ends at B slot of an instruction", EndMBB, LI);
1480 if (I->end.isDead()) {
1481 // Segment ends on the dead slot.
1482 // That means there must be a dead def.
1483 if (!SlotIndex::isSameInstr(I->start, I->end)) {
1484 report("Live segment ending at dead slot spans instructions", EndMBB, LI);
1489 // A live segment can only end at an early-clobber slot if it is being
1490 // redefined by an early-clobber def.
1491 if (I->end.isEarlyClobber()) {
1492 if (I+1 == LI.end() || (I+1)->start != I->end) {
1493 report("Live segment ending at early clobber slot must be "
1494 "redefined by an EC def in the same instruction", EndMBB, LI);
1499 // The following checks only apply to virtual registers. Physreg liveness
1500 // is too weird to check.
1501 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1502 // A live range can end with either a redefinition, a kill flag on a
1503 // use, or a dead flag on a def.
1504 bool hasRead = false;
1505 bool hasDeadDef = false;
1506 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1507 if (!MOI->isReg() || MOI->getReg() != LI.reg)
1509 if (MOI->readsReg())
1511 if (MOI->isDef() && MOI->isDead())
1515 if (I->end.isDead()) {
1517 report("Instruction doesn't have a dead def operand", MI);
1519 *OS << " in " << LI << '\n';
1523 report("Instruction ending live range doesn't read the register", MI);
1524 *OS << *I << " in " << LI << '\n';
1529 // Now check all the basic blocks in this live segment.
1530 MachineFunction::const_iterator MFI = MBB;
1531 // Is this live range the beginning of a non-PHIDef VN?
1532 if (I->start == VNI->def && !VNI->isPHIDef()) {
1533 // Not live-in to any blocks.
1540 assert(LiveInts->isLiveInToMBB(LI, MFI));
1541 // We don't know how to track physregs into a landing pad.
1542 if (!TargetRegisterInfo::isVirtualRegister(LI.reg) &&
1543 MFI->isLandingPad()) {
1544 if (&*MFI == EndMBB)
1550 // Is VNI a PHI-def in the current block?
1551 bool IsPHI = VNI->isPHIDef() &&
1552 VNI->def == LiveInts->getMBBStartIdx(MFI);
1554 // Check that VNI is live-out of all predecessors.
1555 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1556 PE = MFI->pred_end(); PI != PE; ++PI) {
1557 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
1558 const VNInfo *PVNI = LI.getVNInfoBefore(PEnd);
1560 // All predecessors must have a live-out value.
1562 report("Register not marked live out of predecessor", *PI, LI);
1563 *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1564 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
1569 // Only PHI-defs can take different predecessor values.
1570 if (!IsPHI && PVNI != VNI) {
1571 report("Different value live out of predecessor", *PI, LI);
1572 *OS << "Valno #" << PVNI->id << " live out of BB#"
1573 << (*PI)->getNumber() << '@' << PEnd
1574 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1575 << '@' << LiveInts->getMBBStartIdx(MFI) << '\n';
1578 if (&*MFI == EndMBB)
1584 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
1585 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
1587 verifyLiveIntervalValue(LI, *I);
1589 for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I)
1590 verifyLiveIntervalSegment(LI, I);
1592 // Check the LI only has one connected component.
1593 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1594 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1595 unsigned NumComp = ConEQ.Classify(&LI);
1597 report("Multiple connected components in live interval", MF, LI);
1598 for (unsigned comp = 0; comp != NumComp; ++comp) {
1599 *OS << comp << ": valnos";
1600 for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
1601 E = LI.vni_end(); I!=E; ++I)
1602 if (comp == ConEQ.getEqClass(*I))
1603 *OS << ' ' << (*I)->id;