class MachineConstantPoolValue;
class MachineFunction;
class MDNode;
-class SDNodeOrdering;
class SDDbgValue;
class TargetLowering;
class TargetSelectionDAGInfo;
/// SelectionDAG.
BumpPtrAllocator Allocator;
- /// SDNodeOrdering - The ordering of the SDNodes. It roughly corresponds to
- /// the ordering of the original LLVM instructions.
- SDNodeOrdering *Ordering;
-
/// DbgInfo - Tracks dbg_value information through SDISel.
SDDbgInfo *DbgInfo;
}
}
- /// AssignOrdering - Assign an order to the SDNode.
- void AssignOrdering(const SDNode *SD, unsigned Order);
-
- /// GetOrdering - Get the order for the SDNode.
- unsigned GetOrdering(const SDNode *SD) const;
-
/// AddDbgValue - Add a dbg_value SDNode. If SD is non-null that means the
/// value is produced by SD.
void AddDbgValue(SDDbgValue *DB, SDNode *SD, bool isParameter);
SDValue &OpEntry = PromotedIntegers[Op];
assert(OpEntry.getNode() == 0 && "Node is already promoted!");
OpEntry = Result;
-
- // Propagate node ordering
- DAG.AssignOrdering(Result.getNode(), DAG.GetOrdering(Op.getNode()));
}
void DAGTypeLegalizer::SetSoftenedFloat(SDValue Op, SDValue Result) {
SDValue &OpEntry = SoftenedFloats[Op];
assert(OpEntry.getNode() == 0 && "Node is already converted to integer!");
OpEntry = Result;
-
- // Propagate node ordering
- DAG.AssignOrdering(Result.getNode(), DAG.GetOrdering(Op.getNode()));
}
void DAGTypeLegalizer::SetScalarizedVector(SDValue Op, SDValue Result) {
SDValue &OpEntry = ScalarizedVectors[Op];
assert(OpEntry.getNode() == 0 && "Node is already scalarized!");
OpEntry = Result;
-
- // Propagate node ordering
- DAG.AssignOrdering(Result.getNode(), DAG.GetOrdering(Op.getNode()));
}
void DAGTypeLegalizer::GetExpandedInteger(SDValue Op, SDValue &Lo,
assert(Entry.first.getNode() == 0 && "Node already expanded");
Entry.first = Lo;
Entry.second = Hi;
-
- // Propagate ordering
- DAG.AssignOrdering(Lo.getNode(), DAG.GetOrdering(Op.getNode()));
- DAG.AssignOrdering(Hi.getNode(), DAG.GetOrdering(Op.getNode()));
}
void DAGTypeLegalizer::GetExpandedFloat(SDValue Op, SDValue &Lo,
assert(Entry.first.getNode() == 0 && "Node already expanded");
Entry.first = Lo;
Entry.second = Hi;
-
- // Propagate ordering
- DAG.AssignOrdering(Lo.getNode(), DAG.GetOrdering(Op.getNode()));
- DAG.AssignOrdering(Hi.getNode(), DAG.GetOrdering(Op.getNode()));
}
void DAGTypeLegalizer::GetSplitVector(SDValue Op, SDValue &Lo,
assert(Entry.first.getNode() == 0 && "Node already split");
Entry.first = Lo;
Entry.second = Hi;
-
- // Propagate ordering
- DAG.AssignOrdering(Lo.getNode(), DAG.GetOrdering(Op.getNode()));
- DAG.AssignOrdering(Hi.getNode(), DAG.GetOrdering(Op.getNode()));
}
void DAGTypeLegalizer::SetWidenedVector(SDValue Op, SDValue Result) {
SDValue &OpEntry = WidenedVectors[Op];
assert(OpEntry.getNode() == 0 && "Node already widened!");
OpEntry = Result;
-
- // Propagate node ordering
- DAG.AssignOrdering(Result.getNode(), DAG.GetOrdering(Op.getNode()));
}
"Custom lowering returned the wrong number of results!");
for (unsigned i = 0, e = Results.size(); i != e; ++i) {
ReplaceValueWith(SDValue(N, i), Results[i]);
- // Propagate node ordering
- DAG.AssignOrdering(Results[i].getNode(), DAG.GetOrdering(N));
}
return true;
}
+++ /dev/null
-//===-- llvm/CodeGen/SDNodeOrdering.h - SDNode Ordering ---------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file declares the SDNodeOrdering class.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_CODEGEN_SDNODEORDERING_H
-#define LLVM_CODEGEN_SDNODEORDERING_H
-
-#include "llvm/ADT/DenseMap.h"
-
-namespace llvm {
-
-class SDNode;
-
-/// SDNodeOrdering - Maps a unique (monotonically increasing) value to each
-/// SDNode that roughly corresponds to the ordering of the original LLVM
-/// instruction. This is used for turning off scheduling, because we'll forgo
-/// the normal scheduling algorithms and output the instructions according to
-/// this ordering.
-class SDNodeOrdering {
- DenseMap<const SDNode*, unsigned> OrderMap;
-
- void operator=(const SDNodeOrdering&) LLVM_DELETED_FUNCTION;
- SDNodeOrdering(const SDNodeOrdering&) LLVM_DELETED_FUNCTION;
-public:
- SDNodeOrdering() {}
-
- void add(const SDNode *Node, unsigned NewOrder) {
- unsigned &OldOrder = OrderMap[Node];
- if (OldOrder == 0 || (OldOrder > 0 && NewOrder < OldOrder))
- OldOrder = NewOrder;
- }
- void remove(const SDNode *Node) {
- DenseMap<const SDNode*, unsigned>::iterator Itr = OrderMap.find(Node);
- if (Itr != OrderMap.end())
- OrderMap.erase(Itr);
- }
- void clear() {
- OrderMap.clear();
- }
- unsigned getOrder(const SDNode *Node) {
- return OrderMap[Node];
- }
-};
-
-} // end llvm namespace
-
-#endif
unsigned getNodeOrdering(const SUnit *SU) const {
if (!SU->getNode()) return 0;
- return scheduleDAG->DAG->GetOrdering(SU->getNode());
+ return SU->getNode()->getIROrder();
}
bool empty() const { return Queue.empty(); }
DenseMap<SDValue, unsigned> &VRBaseMap,
SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
SmallSet<unsigned, 8> &Seen) {
- unsigned Order = DAG->GetOrdering(N);
+ unsigned Order = N->getIROrder();
if (!Order || !Seen.insert(Order)) {
// Process any valid SDDbgValues even if node does not have any order
// assigned.
#include "llvm/CodeGen/SelectionDAG.h"
#include "SDNodeDbgValue.h"
-#include "SDNodeOrdering.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
NodeAllocator.Deallocate(AllNodes.remove(N));
- // Remove the ordering of this node.
- Ordering->remove(N);
-
// If any of the SDDbgValue nodes refer to this SDNode, invalidate them.
ArrayRef<SDDbgValue*> DbgVals = DbgInfo->getSDDbgValues(N);
for (unsigned i = 0, e = DbgVals.size(); i != e; ++i)
: TM(tm), TLI(*tm.getTargetLowering()), TSI(*tm.getSelectionDAGInfo()),
TTI(0), OptLevel(OL), EntryNode(ISD::EntryToken, 0, DebugLoc(),
getVTList(MVT::Other)),
- Root(getEntryNode()), Ordering(0), UpdateListeners(0) {
+ Root(getEntryNode()), UpdateListeners(0) {
AllNodes.push_back(&EntryNode);
- Ordering = new SDNodeOrdering();
DbgInfo = new SDDbgInfo();
}
SelectionDAG::~SelectionDAG() {
assert(!UpdateListeners && "Dangling registered DAGUpdateListeners");
allnodes_clear();
- delete Ordering;
delete DbgInfo;
}
EntryNode.UseList = 0;
AllNodes.push_back(&EntryNode);
Root = getEntryNode();
- Ordering->clear();
DbgInfo->clear();
}
/// getMemBasePlusOffset - Returns base and offset node for the
///
-static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset,
+static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, SDLoc dl,
SelectionDAG &DAG) {
EVT VT = Base.getValueType();
- return DAG.getNode(ISD::ADD, SDLoc(Base),
+ return DAG.getNode(ISD::ADD, dl,
VT, Base, DAG.getConstant(Offset, VT));
}
Value = getMemsetStringVal(VT, dl, DAG, TLI, Str.substr(SrcOff));
if (Value.getNode())
Store = DAG.getStore(Chain, dl, Value,
- getMemBasePlusOffset(Dst, DstOff, DAG),
+ getMemBasePlusOffset(Dst, DstOff, dl, DAG),
DstPtrInfo.getWithOffset(DstOff), isVol,
false, Align);
}
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
assert(NVT.bitsGE(VT));
Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain,
- getMemBasePlusOffset(Src, SrcOff, DAG),
+ getMemBasePlusOffset(Src, SrcOff, dl, DAG),
SrcPtrInfo.getWithOffset(SrcOff), VT, isVol, false,
MinAlign(SrcAlign, SrcOff));
Store = DAG.getTruncStore(Chain, dl, Value,
- getMemBasePlusOffset(Dst, DstOff, DAG),
+ getMemBasePlusOffset(Dst, DstOff, dl, DAG),
DstPtrInfo.getWithOffset(DstOff), VT, isVol,
false, Align);
}
SDValue Value, Store;
Value = DAG.getLoad(VT, dl, Chain,
- getMemBasePlusOffset(Src, SrcOff, DAG),
+ getMemBasePlusOffset(Src, SrcOff, dl, DAG),
SrcPtrInfo.getWithOffset(SrcOff), isVol,
false, false, SrcAlign);
LoadValues.push_back(Value);
SDValue Value, Store;
Store = DAG.getStore(Chain, dl, LoadValues[i],
- getMemBasePlusOffset(Dst, DstOff, DAG),
+ getMemBasePlusOffset(Dst, DstOff, dl, DAG),
DstPtrInfo.getWithOffset(DstOff), isVol, false, Align);
OutChains.push_back(Store);
DstOff += VTSize;
}
assert(Value.getValueType() == VT && "Value with wrong type.");
SDValue Store = DAG.getStore(Chain, dl, Value,
- getMemBasePlusOffset(Dst, DstOff, DAG),
+ getMemBasePlusOffset(Dst, DstOff, dl, DAG),
DstPtrInfo.getWithOffset(DstOff),
isVol, false, Align);
OutChains.push_back(Store);
return DAGSize;
}
-/// AssignOrdering - Assign an order to the SDNode.
-void SelectionDAG::AssignOrdering(const SDNode *SD, unsigned Order) {
- assert(SD && "Trying to assign an order to a null node!");
- Ordering->add(SD, Order);
-}
-
-/// GetOrdering - Get the order for the SDNode.
-unsigned SelectionDAG::GetOrdering(const SDNode *SD) const {
- assert(SD && "Trying to get the order of a null node!");
- return Ordering->getOrder(SD);
-}
-
/// AddDbgValue - Add a dbg_value SDNode. If SD is non-null that means the
/// value is produced by SD.
void SelectionDAG::AddDbgValue(SDDbgValue *DB, SDNode *SD, bool isParameter) {
return Root;
}
-void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
- if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
- DAG.AssignOrdering(Node, SDNodeOrder);
-
- for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
- AssignOrderingToNode(Node->getOperand(I).getNode());
-}
-
void SelectionDAGBuilder::visit(const Instruction &I) {
// Set up outgoing PHI node register values before emitting the terminator.
if (isa<TerminatorInst>(&I))
HandlePHINodesInSuccessorBlocks(I.getParent());
+ ++SDNodeOrder;
+
CurInst = &I;
visit(I.getOpcode(), I);
case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
#include "llvm/IR/Instruction.def"
}
-
- // Assign the ordering to the freshly created DAG nodes.
- if (NodeMap.count(&I)) {
- ++SDNodeOrder;
- AssignOrderingToNode(getValue(&I).getNode());
- }
}
// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
MVT::Other, &Chains[0], ChainI);
- ++SDNodeOrder;
- AssignOrderingToNode(StoreNode.getNode());
DAG.setRoot(StoreNode);
}
}
setValue(&I, Result);
- } else {
- // Assign order to result here. If the intrinsic does not produce a result,
- // it won't be mapped to a SDNode and visit() will not assign it an order
- // number.
- ++SDNodeOrder;
- AssignOrderingToNode(Result.getNode());
}
}
return 0;
}
- // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
- // but do not always have a corresponding SDNode built. The SDNodeOrder
- // absolute, but not relative, values are different depending on whether
- // debug info exists.
- ++SDNodeOrder;
-
// Check if address has undef value.
if (isa<UndefValue>(Address) ||
(Address->use_empty() && !isa<Argument>(Address))) {
if (!V)
return 0;
- // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
- // but do not always have a corresponding SDNode built. The SDNodeOrder
- // absolute, but not relative, values are different depending on whether
- // debug info exists.
- ++SDNodeOrder;
SDDbgValue *SDV;
if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
&Values[0], Values.size()));
}
- // Assign order to nodes here. If the call does not produce a result, it won't
- // be mapped to a SDNode and visit() will not assign it an order number.
if (!Result.second.getNode()) {
// As a special case, a null chain means that a tail call has been emitted and
// the DAG root is already updated.
HasTailCall = true;
- ++SDNodeOrder;
- AssignOrderingToNode(DAG.getRoot().getNode());
} else {
DAG.setRoot(Result.second);
- ++SDNodeOrder;
- AssignOrderingToNode(Result.second.getNode());
}
if (LandingPad) {
void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
- /// AssignOrderingToNode - Assign an ordering to the node. The order is gotten
- /// from how the code appeared in the source. The ordering is used by the
- /// scheduler to effectively turn off scheduling.
- void AssignOrderingToNode(const SDNode *Node);
-
void visit(const Instruction &I);
void visit(unsigned Opcode, const User &I);
DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
<< " '" << BlockName << "'\n"; CurDAG->dump());
+
}
{
continue;
// Replace node.
if (ResNode) {
- // Propagate ordering
- CurDAG->AssignOrdering(ResNode, CurDAG->GetOrdering(Node));
-
ReplaceUses(Node, ResNode);
}
false,
TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
if (p.getNode())
- DAG.AssignOrdering(p.getNode(), idx + 1);
+ p.getNode()->setIROrder(idx + 1);
InVals.push_back(p);
} else {
// If no ABI, just move the param symbol
SDValue Arg = getParamSymbol(DAG, idx, ObjectVT);
SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
if (p.getNode())
- DAG.AssignOrdering(p.getNode(), idx + 1);
+ p.getNode()->setIROrder(idx + 1);
InVals.push_back(p);
}
continue;
SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
if (p.getNode())
- DAG.AssignOrdering(p.getNode(), idx + 1);
+ p.getNode()->setIROrder(idx + 1);
if (isKernel)
InVals.push_back(p);
else {
DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
}
- // Propagate ordering to the last node, for now.
- CurDAG->AssignOrdering(InFlag.getNode(), CurDAG->GetOrdering(Node));
-
return NULL;
}
define float @test_sincos_f32(float %f) {
%sin = call float @sinf(float %f) readnone
%cos = call float @cosf(float %f) readnone
-; CHECK: bl cosf
; CHECK: bl sinf
+; CHECK: bl cosf
%val = fadd float %sin, %cos
ret float %val
}
%sin = call double @sin(double %f) readnone
%cos = call double @cos(double %f) readnone
%val = fadd double %sin, %cos
-; CHECK: bl cos
; CHECK: bl sin
+; CHECK: bl cos
ret double %val
}
%sin = call fp128 @sinl(fp128 %f) readnone
%cos = call fp128 @cosl(fp128 %f) readnone
%val = fadd fp128 %sin, %cos
-; CHECK: bl cosl
; CHECK: bl sinl
+; CHECK: bl cosl
ret fp128 %val
}
; If-convert the return
; CHECK: it ne
; Fold the CSR+return into a pop
-; CHECK: popne {r4, r5, r7, pc}
+; CHECK: pop {r4, r5, r6, r7, pc}
sw.bb18:
%call20 = tail call i32 @bar(i32 %in2) nounwind
switch i32 %call20, label %sw.default56 [
; THUMB-ELF: LoadGV
; THUMB-ELF: ldr.n r[[reg0:[0-9]+]],
; THUMB-ELF: ldr.n r[[reg1:[0-9]+]],
-; THUMB-ELF: ldr r[[reg0]], [r[[reg1]], r[[reg0]]]
+; THUMB-ELF: ldr r[[reg0]], [r[[reg0]], r[[reg1]]]
; ARM: LoadGV
; ARM: ldr [[reg1:r[0-9]+]],
; ARM: add [[reg1]], pc, [[reg1]]
; ARMv7-ELF: LoadGV
; ARMv7-ELF: ldr r[[reg2:[0-9]+]],
; ARMv7-ELF: ldr r[[reg3:[0-9]+]],
-; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]
+; ARMv7-ELF: ldr r[[reg2]], [r[[reg2]], r[[reg3]]]
%tmp = load i32* @g
ret i32 %tmp
}
; THUMB-ELF: LoadIndirectSymbol
; THUMB-ELF: ldr.n r[[reg3:[0-9]+]],
; THUMB-ELF: ldr.n r[[reg4:[0-9]+]],
-; THUMB-ELF: ldr r[[reg3]], [r[[reg4]], r[[reg3]]]
+; THUMB-ELF: ldr r[[reg3]], [r[[reg3]], r[[reg4]]]
; ARM: LoadIndirectSymbol
; ARM: ldr [[reg4:r[0-9]+]],
; ARM: ldr [[reg4]], [pc, [[reg4]]]
; ARMv7-ELF: LoadIndirectSymbol
; ARMv7-ELF: ldr r[[reg5:[0-9]+]],
; ARMv7-ELF: ldr r[[reg6:[0-9]+]],
-; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]]
+; ARMv7-ELF: ldr r[[reg5]], [r[[reg5]], r[[reg6]]]
%tmp = load i32* @i
ret i32 %tmp
}
; OSX_SINCOS: addss %xmm0, %xmm1
; OSX_NOOPT: test1
-; OSX_NOOPT: callq _cosf
; OSX_NOOPT: callq _sinf
+; OSX_NOOPT: callq _cosf
%call = tail call float @sinf(float %x) nounwind readnone
%call1 = tail call float @cosf(float %x) nounwind readnone
%add = fadd float %call, %call1
; OSX_SINCOS: addsd %xmm1, %xmm0
; OSX_NOOPT: test2
-; OSX_NOOPT: callq _cos
; OSX_NOOPT: callq _sin
+; OSX_NOOPT: callq _cos
%call = tail call double @sin(double %x) nounwind readnone
%call1 = tail call double @cos(double %x) nounwind readnone
%add = fadd double %call, %call1
; Load the address of the result and put it onto stack
; (through %ecx in the -O0 build).
-; WIN32: leal {{[0-9]+}}(%esp), %eax
-; WIN32: movl %eax, (%e{{[sc][px]}})
+; WIN32: leal {{[0-9]+}}(%esp), %e{{[a-d]}}x
+; WIN32: movl %e{{[a-d]}}x, (%e{{([a-d]x)|(sp)}})
; The this pointer goes to ECX.
; WIN32-NEXT: leal {{[0-9]+}}(%esp), %ecx
; Check that LSR did something close to the behavior at the time of the bug.
; CHECK: @sqlite3DropTriggerPtr
-; CHECK: incq %rax
+; CHECK: incq %r{{[a-d]}}x
; CHECK: jne
-; CHECK: decq %rax
+; CHECK: decq %r{{[a-d]}}x
; CHECK: ret
define i64 @sqlite3DropTriggerPtr() nounwind {
bb:
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