1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "machine-cse"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/ScopedHashTable.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/RecyclingAllocator.h"
28 #include "llvm/Target/TargetInstrInfo.h"
31 STATISTIC(NumCoalesces, "Number of copies coalesced");
32 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
33 STATISTIC(NumPhysCSEs,
34 "Number of physreg referencing common subexpr eliminated");
35 STATISTIC(NumCrossBBCSEs,
36 "Number of cross-MBB physreg referencing CS eliminated");
37 STATISTIC(NumCommutes, "Number of copies coalesced after commuting");
40 class MachineCSE : public MachineFunctionPass {
41 const TargetInstrInfo *TII;
42 const TargetRegisterInfo *TRI;
44 MachineDominatorTree *DT;
45 MachineRegisterInfo *MRI;
47 static char ID; // Pass identification
48 MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(5), CurrVN(0) {
49 initializeMachineCSEPass(*PassRegistry::getPassRegistry());
52 virtual bool runOnMachineFunction(MachineFunction &MF);
54 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
56 MachineFunctionPass::getAnalysisUsage(AU);
57 AU.addRequired<AliasAnalysis>();
58 AU.addPreservedID(MachineLoopInfoID);
59 AU.addRequired<MachineDominatorTree>();
60 AU.addPreserved<MachineDominatorTree>();
63 virtual void releaseMemory() {
69 const unsigned LookAheadLimit;
70 typedef RecyclingAllocator<BumpPtrAllocator,
71 ScopedHashTableVal<MachineInstr*, unsigned> > AllocatorTy;
72 typedef ScopedHashTable<MachineInstr*, unsigned,
73 MachineInstrExpressionTrait, AllocatorTy> ScopedHTType;
74 typedef ScopedHTType::ScopeTy ScopeType;
75 DenseMap<MachineBasicBlock*, ScopeType*> ScopeMap;
77 SmallVector<MachineInstr*, 64> Exps;
80 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
81 bool isPhysDefTriviallyDead(unsigned Reg,
82 MachineBasicBlock::const_iterator I,
83 MachineBasicBlock::const_iterator E) const;
84 bool hasLivePhysRegDefUses(const MachineInstr *MI,
85 const MachineBasicBlock *MBB,
86 SmallSet<unsigned,8> &PhysRefs,
87 SmallVectorImpl<unsigned> &PhysDefs,
88 bool &PhysUseDef) const;
89 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
90 SmallSet<unsigned,8> &PhysRefs,
91 SmallVectorImpl<unsigned> &PhysDefs,
92 bool &NonLocal) const;
93 bool isCSECandidate(MachineInstr *MI);
94 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
95 MachineInstr *CSMI, MachineInstr *MI);
96 void EnterScope(MachineBasicBlock *MBB);
97 void ExitScope(MachineBasicBlock *MBB);
98 bool ProcessBlock(MachineBasicBlock *MBB);
99 void ExitScopeIfDone(MachineDomTreeNode *Node,
100 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren);
101 bool PerformCSE(MachineDomTreeNode *Node);
103 } // end anonymous namespace
105 char MachineCSE::ID = 0;
106 char &llvm::MachineCSEID = MachineCSE::ID;
107 INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
108 "Machine Common Subexpression Elimination", false, false)
109 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
110 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
111 INITIALIZE_PASS_END(MachineCSE, "machine-cse",
112 "Machine Common Subexpression Elimination", false, false)
114 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
115 MachineBasicBlock *MBB) {
116 bool Changed = false;
117 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
118 MachineOperand &MO = MI->getOperand(i);
119 if (!MO.isReg() || !MO.isUse())
121 unsigned Reg = MO.getReg();
122 if (!TargetRegisterInfo::isVirtualRegister(Reg))
124 if (!MRI->hasOneNonDBGUse(Reg))
125 // Only coalesce single use copies. This ensure the copy will be
128 MachineInstr *DefMI = MRI->getVRegDef(Reg);
129 if (!DefMI->isCopy())
131 unsigned SrcReg = DefMI->getOperand(1).getReg();
132 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
134 if (DefMI->getOperand(0).getSubReg())
136 unsigned SrcSubReg = DefMI->getOperand(1).getSubReg();
137 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
139 RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
141 if (!MRI->constrainRegClass(SrcReg, RC))
143 DEBUG(dbgs() << "Coalescing: " << *DefMI);
144 DEBUG(dbgs() << "*** to: " << *MI);
145 MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
146 MRI->clearKillFlags(SrcReg);
147 DefMI->eraseFromParent();
156 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
157 MachineBasicBlock::const_iterator I,
158 MachineBasicBlock::const_iterator E) const {
159 unsigned LookAheadLeft = LookAheadLimit;
160 while (LookAheadLeft) {
161 // Skip over dbg_value's.
162 while (I != E && I->isDebugValue())
166 // Reached end of block, register is obviously dead.
169 bool SeenDef = false;
170 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
171 const MachineOperand &MO = I->getOperand(i);
172 if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
174 if (!MO.isReg() || !MO.getReg())
176 if (!TRI->regsOverlap(MO.getReg(), Reg))
184 // See a def of Reg (or an alias) before encountering any use, it's
194 /// hasLivePhysRegDefUses - Return true if the specified instruction read/write
195 /// physical registers (except for dead defs of physical registers). It also
196 /// returns the physical register def by reference if it's the only one and the
197 /// instruction does not uses a physical register.
198 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
199 const MachineBasicBlock *MBB,
200 SmallSet<unsigned,8> &PhysRefs,
201 SmallVectorImpl<unsigned> &PhysDefs,
202 bool &PhysUseDef) const{
203 // First, add all uses to PhysRefs.
204 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
205 const MachineOperand &MO = MI->getOperand(i);
206 if (!MO.isReg() || MO.isDef())
208 unsigned Reg = MO.getReg();
211 if (TargetRegisterInfo::isVirtualRegister(Reg))
213 // Reading constant physregs is ok.
214 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
215 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
216 PhysRefs.insert(*AI);
219 // Next, collect all defs into PhysDefs. If any is already in PhysRefs
220 // (which currently contains only uses), set the PhysUseDef flag.
222 MachineBasicBlock::const_iterator I = MI; I = llvm::next(I);
223 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
224 const MachineOperand &MO = MI->getOperand(i);
225 if (!MO.isReg() || !MO.isDef())
227 unsigned Reg = MO.getReg();
230 if (TargetRegisterInfo::isVirtualRegister(Reg))
232 // Check against PhysRefs even if the def is "dead".
233 if (PhysRefs.count(Reg))
235 // If the def is dead, it's ok. But the def may not marked "dead". That's
236 // common since this pass is run before livevariables. We can scan
237 // forward a few instructions and check if it is obviously dead.
238 if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end()))
239 PhysDefs.push_back(Reg);
242 // Finally, add all defs to PhysRefs as well.
243 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
244 for (MCRegAliasIterator AI(PhysDefs[i], TRI, true); AI.isValid(); ++AI)
245 PhysRefs.insert(*AI);
247 return !PhysRefs.empty();
250 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
251 SmallSet<unsigned,8> &PhysRefs,
252 SmallVectorImpl<unsigned> &PhysDefs,
253 bool &NonLocal) const {
254 // For now conservatively returns false if the common subexpression is
255 // not in the same basic block as the given instruction. The only exception
256 // is if the common subexpression is in the sole predecessor block.
257 const MachineBasicBlock *MBB = MI->getParent();
258 const MachineBasicBlock *CSMBB = CSMI->getParent();
260 bool CrossMBB = false;
262 if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
265 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
266 if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i]))
267 // Avoid extending live range of physical registers if they are
268 //allocatable or reserved.
273 MachineBasicBlock::const_iterator I = CSMI; I = llvm::next(I);
274 MachineBasicBlock::const_iterator E = MI;
275 MachineBasicBlock::const_iterator EE = CSMBB->end();
276 unsigned LookAheadLeft = LookAheadLimit;
277 while (LookAheadLeft) {
278 // Skip over dbg_value's.
279 while (I != E && I != EE && I->isDebugValue())
283 assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
295 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
296 const MachineOperand &MO = I->getOperand(i);
297 // RegMasks go on instructions like calls that clobber lots of physregs.
298 // Don't attempt to CSE across such an instruction.
301 if (!MO.isReg() || !MO.isDef())
303 unsigned MOReg = MO.getReg();
304 if (TargetRegisterInfo::isVirtualRegister(MOReg))
306 if (PhysRefs.count(MOReg))
317 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
318 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
319 MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
323 if (MI->isCopyLike())
326 // Ignore stuff that we obviously can't move.
327 if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
328 MI->hasUnmodeledSideEffects())
332 // Okay, this instruction does a load. As a refinement, we allow the target
333 // to decide whether the loaded value is actually a constant. If so, we can
334 // actually use it as a load.
335 if (!MI->isInvariantLoad(AA))
336 // FIXME: we should be able to hoist loads with no other side effects if
337 // there are no other instructions which can change memory in this loop.
338 // This is a trivial form of alias analysis.
344 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
345 /// common expression that defines Reg.
346 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
347 MachineInstr *CSMI, MachineInstr *MI) {
348 // FIXME: Heuristics that works around the lack the live range splitting.
350 // If CSReg is used at all uses of Reg, CSE should not increase register
351 // pressure of CSReg.
352 bool MayIncreasePressure = true;
353 if (TargetRegisterInfo::isVirtualRegister(CSReg) &&
354 TargetRegisterInfo::isVirtualRegister(Reg)) {
355 MayIncreasePressure = false;
356 SmallPtrSet<MachineInstr*, 8> CSUses;
357 for (MachineRegisterInfo::use_nodbg_iterator I =MRI->use_nodbg_begin(CSReg),
358 E = MRI->use_nodbg_end(); I != E; ++I) {
359 MachineInstr *Use = &*I;
362 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
363 E = MRI->use_nodbg_end(); I != E; ++I) {
364 MachineInstr *Use = &*I;
365 if (!CSUses.count(Use)) {
366 MayIncreasePressure = true;
371 if (!MayIncreasePressure) return true;
373 // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
374 // an immediate predecessor. We don't want to increase register pressure and
375 // end up causing other computation to be spilled.
376 if (MI->isAsCheapAsAMove()) {
377 MachineBasicBlock *CSBB = CSMI->getParent();
378 MachineBasicBlock *BB = MI->getParent();
379 if (CSBB != BB && !CSBB->isSuccessor(BB))
383 // Heuristics #2: If the expression doesn't not use a vr and the only use
384 // of the redundant computation are copies, do not cse.
385 bool HasVRegUse = false;
386 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
387 const MachineOperand &MO = MI->getOperand(i);
388 if (MO.isReg() && MO.isUse() &&
389 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
395 bool HasNonCopyUse = false;
396 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
397 E = MRI->use_nodbg_end(); I != E; ++I) {
398 MachineInstr *Use = &*I;
400 if (!Use->isCopyLike()) {
401 HasNonCopyUse = true;
409 // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
410 // it unless the defined value is already used in the BB of the new use.
412 SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
413 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg),
414 E = MRI->use_nodbg_end(); I != E; ++I) {
415 MachineInstr *Use = &*I;
416 HasPHI |= Use->isPHI();
417 CSBBs.insert(Use->getParent());
422 return CSBBs.count(MI->getParent());
425 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
426 DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
427 ScopeType *Scope = new ScopeType(VNT);
428 ScopeMap[MBB] = Scope;
431 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
432 DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
433 DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
434 assert(SI != ScopeMap.end());
439 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
440 bool Changed = false;
442 SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
443 SmallVector<unsigned, 2> ImplicitDefsToUpdate;
444 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
445 MachineInstr *MI = &*I;
448 if (!isCSECandidate(MI))
451 bool FoundCSE = VNT.count(MI);
453 // Look for trivial copy coalescing opportunities.
454 if (PerformTrivialCoalescing(MI, MBB)) {
457 // After coalescing MI itself may become a copy.
458 if (MI->isCopyLike())
460 FoundCSE = VNT.count(MI);
464 // Commute commutable instructions.
465 bool Commuted = false;
466 if (!FoundCSE && MI->isCommutable()) {
467 MachineInstr *NewMI = TII->commuteInstruction(MI);
470 FoundCSE = VNT.count(NewMI);
472 // New instruction. It doesn't need to be kept.
473 NewMI->eraseFromParent();
475 } else if (!FoundCSE)
476 // MI was changed but it didn't help, commute it back!
477 (void)TII->commuteInstruction(MI);
481 // If the instruction defines physical registers and the values *may* be
482 // used, then it's not safe to replace it with a common subexpression.
483 // It's also not safe if the instruction uses physical registers.
484 bool CrossMBBPhysDef = false;
485 SmallSet<unsigned, 8> PhysRefs;
486 SmallVector<unsigned, 2> PhysDefs;
487 bool PhysUseDef = false;
488 if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs,
489 PhysDefs, PhysUseDef)) {
492 // ... Unless the CS is local or is in the sole predecessor block
493 // and it also defines the physical register which is not clobbered
494 // in between and the physical register uses were not clobbered.
495 // This can never be the case if the instruction both uses and
496 // defines the same physical register, which was detected above.
498 unsigned CSVN = VNT.lookup(MI);
499 MachineInstr *CSMI = Exps[CSVN];
500 if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
506 VNT.insert(MI, CurrVN++);
511 // Found a common subexpression, eliminate it.
512 unsigned CSVN = VNT.lookup(MI);
513 MachineInstr *CSMI = Exps[CSVN];
514 DEBUG(dbgs() << "Examining: " << *MI);
515 DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
517 // Check if it's profitable to perform this CSE.
519 unsigned NumDefs = MI->getDesc().getNumDefs() +
520 MI->getDesc().getNumImplicitDefs();
522 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
523 MachineOperand &MO = MI->getOperand(i);
524 if (!MO.isReg() || !MO.isDef())
526 unsigned OldReg = MO.getReg();
527 unsigned NewReg = CSMI->getOperand(i).getReg();
529 // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
530 // we should make sure it is not dead at CSMI.
531 if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
532 ImplicitDefsToUpdate.push_back(i);
533 if (OldReg == NewReg) {
538 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
539 TargetRegisterInfo::isVirtualRegister(NewReg) &&
540 "Do not CSE physical register defs!");
542 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
543 DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
548 // Don't perform CSE if the result of the old instruction cannot exist
549 // within the register class of the new instruction.
550 const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
551 if (!MRI->constrainRegClass(NewReg, OldRC)) {
552 DEBUG(dbgs() << "*** Not the same register class, avoid CSE!\n");
557 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
561 // Actually perform the elimination.
563 for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
564 MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
565 MRI->clearKillFlags(CSEPairs[i].second);
568 // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
569 // we should make sure it is not dead at CSMI.
570 for (unsigned i = 0, e = ImplicitDefsToUpdate.size(); i != e; ++i)
571 CSMI->getOperand(ImplicitDefsToUpdate[i]).setIsDead(false);
573 if (CrossMBBPhysDef) {
574 // Add physical register defs now coming in from a predecessor to MBB
576 while (!PhysDefs.empty()) {
577 unsigned LiveIn = PhysDefs.pop_back_val();
578 if (!MBB->isLiveIn(LiveIn))
579 MBB->addLiveIn(LiveIn);
584 MI->eraseFromParent();
586 if (!PhysRefs.empty())
592 VNT.insert(MI, CurrVN++);
596 ImplicitDefsToUpdate.clear();
602 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
603 /// dominator tree node if its a leaf or all of its children are done. Walk
604 /// up the dominator tree to destroy ancestors which are now done.
606 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
607 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren) {
608 if (OpenChildren[Node])
612 ExitScope(Node->getBlock());
614 // Now traverse upwards to pop ancestors whose offsprings are all done.
615 while (MachineDomTreeNode *Parent = Node->getIDom()) {
616 unsigned Left = --OpenChildren[Parent];
619 ExitScope(Parent->getBlock());
624 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
625 SmallVector<MachineDomTreeNode*, 32> Scopes;
626 SmallVector<MachineDomTreeNode*, 8> WorkList;
627 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
631 // Perform a DFS walk to determine the order of visit.
632 WorkList.push_back(Node);
634 Node = WorkList.pop_back_val();
635 Scopes.push_back(Node);
636 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
637 unsigned NumChildren = Children.size();
638 OpenChildren[Node] = NumChildren;
639 for (unsigned i = 0; i != NumChildren; ++i) {
640 MachineDomTreeNode *Child = Children[i];
641 WorkList.push_back(Child);
643 } while (!WorkList.empty());
646 bool Changed = false;
647 for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
648 MachineDomTreeNode *Node = Scopes[i];
649 MachineBasicBlock *MBB = Node->getBlock();
651 Changed |= ProcessBlock(MBB);
652 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
653 ExitScopeIfDone(Node, OpenChildren);
659 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
660 TII = MF.getTarget().getInstrInfo();
661 TRI = MF.getTarget().getRegisterInfo();
662 MRI = &MF.getRegInfo();
663 AA = &getAnalysis<AliasAnalysis>();
664 DT = &getAnalysis<MachineDominatorTree>();
665 return PerformCSE(DT->getRootNode());