1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "machine-cse"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/MachineDominators.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/ScopedHashTable.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/RecyclingAllocator.h"
31 STATISTIC(NumCoalesces, "Number of copies coalesced");
32 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
33 STATISTIC(NumPhysCSEs,
34 "Number of physreg referencing common subexpr eliminated");
35 STATISTIC(NumCrossBBCSEs,
36 "Number of cross-MBB physreg referencing CS eliminated");
37 STATISTIC(NumCommutes, "Number of copies coalesced after commuting");
40 class MachineCSE : public MachineFunctionPass {
41 const TargetInstrInfo *TII;
42 const TargetRegisterInfo *TRI;
44 MachineDominatorTree *DT;
45 MachineRegisterInfo *MRI;
47 static char ID; // Pass identification
48 MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(5), CurrVN(0) {
49 initializeMachineCSEPass(*PassRegistry::getPassRegistry());
52 virtual bool runOnMachineFunction(MachineFunction &MF);
54 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
56 MachineFunctionPass::getAnalysisUsage(AU);
57 AU.addRequired<AliasAnalysis>();
58 AU.addPreservedID(MachineLoopInfoID);
59 AU.addRequired<MachineDominatorTree>();
60 AU.addPreserved<MachineDominatorTree>();
63 virtual void releaseMemory() {
66 AllocatableRegs.clear();
71 const unsigned LookAheadLimit;
72 typedef RecyclingAllocator<BumpPtrAllocator,
73 ScopedHashTableVal<MachineInstr*, unsigned> > AllocatorTy;
74 typedef ScopedHashTable<MachineInstr*, unsigned,
75 MachineInstrExpressionTrait, AllocatorTy> ScopedHTType;
76 typedef ScopedHTType::ScopeTy ScopeType;
77 DenseMap<MachineBasicBlock*, ScopeType*> ScopeMap;
79 SmallVector<MachineInstr*, 64> Exps;
81 BitVector AllocatableRegs;
82 BitVector ReservedRegs;
84 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
85 bool isPhysDefTriviallyDead(unsigned Reg,
86 MachineBasicBlock::const_iterator I,
87 MachineBasicBlock::const_iterator E) const ;
88 bool hasLivePhysRegDefUses(const MachineInstr *MI,
89 const MachineBasicBlock *MBB,
90 SmallSet<unsigned,8> &PhysRefs,
91 SmallVector<unsigned,2> &PhysDefs) const;
92 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
93 SmallSet<unsigned,8> &PhysRefs,
94 SmallVector<unsigned,2> &PhysDefs,
95 bool &NonLocal) const;
96 bool isCSECandidate(MachineInstr *MI);
97 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
98 MachineInstr *CSMI, MachineInstr *MI);
99 void EnterScope(MachineBasicBlock *MBB);
100 void ExitScope(MachineBasicBlock *MBB);
101 bool ProcessBlock(MachineBasicBlock *MBB);
102 void ExitScopeIfDone(MachineDomTreeNode *Node,
103 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
104 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap);
105 bool PerformCSE(MachineDomTreeNode *Node);
107 } // end anonymous namespace
109 char MachineCSE::ID = 0;
110 char &llvm::MachineCSEID = MachineCSE::ID;
111 INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
112 "Machine Common Subexpression Elimination", false, false)
113 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
114 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
115 INITIALIZE_PASS_END(MachineCSE, "machine-cse",
116 "Machine Common Subexpression Elimination", false, false)
118 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
119 MachineBasicBlock *MBB) {
120 bool Changed = false;
121 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
122 MachineOperand &MO = MI->getOperand(i);
123 if (!MO.isReg() || !MO.isUse())
125 unsigned Reg = MO.getReg();
126 if (!TargetRegisterInfo::isVirtualRegister(Reg))
128 if (!MRI->hasOneNonDBGUse(Reg))
129 // Only coalesce single use copies. This ensure the copy will be
132 MachineInstr *DefMI = MRI->getVRegDef(Reg);
133 if (DefMI->getParent() != MBB)
135 if (!DefMI->isCopy())
137 unsigned SrcReg = DefMI->getOperand(1).getReg();
138 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
140 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
142 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg)))
144 DEBUG(dbgs() << "Coalescing: " << *DefMI);
145 DEBUG(dbgs() << "*** to: " << *MI);
147 MRI->clearKillFlags(SrcReg);
148 DefMI->eraseFromParent();
157 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
158 MachineBasicBlock::const_iterator I,
159 MachineBasicBlock::const_iterator E) const {
160 unsigned LookAheadLeft = LookAheadLimit;
161 while (LookAheadLeft) {
162 // Skip over dbg_value's.
163 while (I != E && I->isDebugValue())
167 // Reached end of block, register is obviously dead.
170 bool SeenDef = false;
171 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
172 const MachineOperand &MO = I->getOperand(i);
173 if (!MO.isReg() || !MO.getReg())
175 if (!TRI->regsOverlap(MO.getReg(), Reg))
183 // See a def of Reg (or an alias) before encountering any use, it's
193 /// hasLivePhysRegDefUses - Return true if the specified instruction read/write
194 /// physical registers (except for dead defs of physical registers). It also
195 /// returns the physical register def by reference if it's the only one and the
196 /// instruction does not uses a physical register.
197 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
198 const MachineBasicBlock *MBB,
199 SmallSet<unsigned,8> &PhysRefs,
200 SmallVector<unsigned,2> &PhysDefs) const{
201 MachineBasicBlock::const_iterator I = MI; I = llvm::next(I);
202 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
203 const MachineOperand &MO = MI->getOperand(i);
206 unsigned Reg = MO.getReg();
209 if (TargetRegisterInfo::isVirtualRegister(Reg))
211 // If the def is dead, it's ok. But the def may not marked "dead". That's
212 // common since this pass is run before livevariables. We can scan
213 // forward a few instructions and check if it is obviously dead.
215 (MO.isDead() || isPhysDefTriviallyDead(Reg, I, MBB->end())))
217 PhysRefs.insert(Reg);
219 PhysDefs.push_back(Reg);
220 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
221 PhysRefs.insert(*Alias);
224 return !PhysRefs.empty();
227 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
228 SmallSet<unsigned,8> &PhysRefs,
229 SmallVector<unsigned,2> &PhysDefs,
230 bool &NonLocal) const {
231 // For now conservatively returns false if the common subexpression is
232 // not in the same basic block as the given instruction. The only exception
233 // is if the common subexpression is in the sole predecessor block.
234 const MachineBasicBlock *MBB = MI->getParent();
235 const MachineBasicBlock *CSMBB = CSMI->getParent();
237 bool CrossMBB = false;
239 if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
242 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
243 if (AllocatableRegs.test(PhysDefs[i]) || ReservedRegs.test(PhysDefs[i]))
244 // Avoid extending live range of physical registers if they are
245 //allocatable or reserved.
250 MachineBasicBlock::const_iterator I = CSMI; I = llvm::next(I);
251 MachineBasicBlock::const_iterator E = MI;
252 MachineBasicBlock::const_iterator EE = CSMBB->end();
253 unsigned LookAheadLeft = LookAheadLimit;
254 while (LookAheadLeft) {
255 // Skip over dbg_value's.
256 while (I != E && I != EE && I->isDebugValue())
260 assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
272 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
273 const MachineOperand &MO = I->getOperand(i);
274 if (!MO.isReg() || !MO.isDef())
276 unsigned MOReg = MO.getReg();
277 if (TargetRegisterInfo::isVirtualRegister(MOReg))
279 if (PhysRefs.count(MOReg))
290 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
291 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
292 MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
296 if (MI->isCopyLike())
299 // Ignore stuff that we obviously can't move.
300 if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
301 MI->hasUnmodeledSideEffects())
305 // Okay, this instruction does a load. As a refinement, we allow the target
306 // to decide whether the loaded value is actually a constant. If so, we can
307 // actually use it as a load.
308 if (!MI->isInvariantLoad(AA))
309 // FIXME: we should be able to hoist loads with no other side effects if
310 // there are no other instructions which can change memory in this loop.
311 // This is a trivial form of alias analysis.
317 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
318 /// common expression that defines Reg.
319 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
320 MachineInstr *CSMI, MachineInstr *MI) {
321 // FIXME: Heuristics that works around the lack the live range splitting.
323 // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
324 // an immediate predecessor. We don't want to increase register pressure and
325 // end up causing other computation to be spilled.
326 if (MI->isAsCheapAsAMove()) {
327 MachineBasicBlock *CSBB = CSMI->getParent();
328 MachineBasicBlock *BB = MI->getParent();
329 if (CSBB != BB && !CSBB->isSuccessor(BB))
333 // Heuristics #2: If the expression doesn't not use a vr and the only use
334 // of the redundant computation are copies, do not cse.
335 bool HasVRegUse = false;
336 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
337 const MachineOperand &MO = MI->getOperand(i);
338 if (MO.isReg() && MO.isUse() &&
339 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
345 bool HasNonCopyUse = false;
346 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
347 E = MRI->use_nodbg_end(); I != E; ++I) {
348 MachineInstr *Use = &*I;
350 if (!Use->isCopyLike()) {
351 HasNonCopyUse = true;
359 // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
360 // it unless the defined value is already used in the BB of the new use.
362 SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
363 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg),
364 E = MRI->use_nodbg_end(); I != E; ++I) {
365 MachineInstr *Use = &*I;
366 HasPHI |= Use->isPHI();
367 CSBBs.insert(Use->getParent());
372 return CSBBs.count(MI->getParent());
375 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
376 DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
377 ScopeType *Scope = new ScopeType(VNT);
378 ScopeMap[MBB] = Scope;
381 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
382 DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
383 DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
384 assert(SI != ScopeMap.end());
389 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
390 bool Changed = false;
392 SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
393 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
394 MachineInstr *MI = &*I;
397 if (!isCSECandidate(MI))
400 bool FoundCSE = VNT.count(MI);
402 // Look for trivial copy coalescing opportunities.
403 if (PerformTrivialCoalescing(MI, MBB)) {
406 // After coalescing MI itself may become a copy.
407 if (MI->isCopyLike())
409 FoundCSE = VNT.count(MI);
413 // Commute commutable instructions.
414 bool Commuted = false;
415 if (!FoundCSE && MI->isCommutable()) {
416 MachineInstr *NewMI = TII->commuteInstruction(MI);
419 FoundCSE = VNT.count(NewMI);
421 // New instruction. It doesn't need to be kept.
422 NewMI->eraseFromParent();
424 } else if (!FoundCSE)
425 // MI was changed but it didn't help, commute it back!
426 (void)TII->commuteInstruction(MI);
430 // If the instruction defines physical registers and the values *may* be
431 // used, then it's not safe to replace it with a common subexpression.
432 // It's also not safe if the instruction uses physical registers.
433 bool CrossMBBPhysDef = false;
434 SmallSet<unsigned,8> PhysRefs;
435 SmallVector<unsigned, 2> PhysDefs;
436 if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs, PhysDefs)) {
439 // ... Unless the CS is local or is in the sole predecessor block
440 // and it also defines the physical register which is not clobbered
441 // in between and the physical register uses were not clobbered.
442 unsigned CSVN = VNT.lookup(MI);
443 MachineInstr *CSMI = Exps[CSVN];
444 if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
449 VNT.insert(MI, CurrVN++);
454 // Found a common subexpression, eliminate it.
455 unsigned CSVN = VNT.lookup(MI);
456 MachineInstr *CSMI = Exps[CSVN];
457 DEBUG(dbgs() << "Examining: " << *MI);
458 DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
460 // Check if it's profitable to perform this CSE.
462 unsigned NumDefs = MI->getDesc().getNumDefs();
463 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
464 MachineOperand &MO = MI->getOperand(i);
465 if (!MO.isReg() || !MO.isDef())
467 unsigned OldReg = MO.getReg();
468 unsigned NewReg = CSMI->getOperand(i).getReg();
469 if (OldReg == NewReg)
472 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
473 TargetRegisterInfo::isVirtualRegister(NewReg) &&
474 "Do not CSE physical register defs!");
476 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
481 // Don't perform CSE if the result of the old instruction cannot exist
482 // within the register class of the new instruction.
483 const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
484 if (!MRI->constrainRegClass(NewReg, OldRC)) {
489 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
493 // Actually perform the elimination.
495 for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
496 MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
497 MRI->clearKillFlags(CSEPairs[i].second);
500 if (CrossMBBPhysDef) {
501 // Add physical register defs now coming in from a predecessor to MBB
503 while (!PhysDefs.empty()) {
504 unsigned LiveIn = PhysDefs.pop_back_val();
505 if (!MBB->isLiveIn(LiveIn))
506 MBB->addLiveIn(LiveIn);
511 MI->eraseFromParent();
513 if (!PhysRefs.empty())
519 DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
520 VNT.insert(MI, CurrVN++);
529 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
530 /// dominator tree node if its a leaf or all of its children are done. Walk
531 /// up the dominator tree to destroy ancestors which are now done.
533 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
534 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
535 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap) {
536 if (OpenChildren[Node])
540 ExitScope(Node->getBlock());
542 // Now traverse upwards to pop ancestors whose offsprings are all done.
543 while (MachineDomTreeNode *Parent = ParentMap[Node]) {
544 unsigned Left = --OpenChildren[Parent];
547 ExitScope(Parent->getBlock());
552 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
553 SmallVector<MachineDomTreeNode*, 32> Scopes;
554 SmallVector<MachineDomTreeNode*, 8> WorkList;
555 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> ParentMap;
556 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
560 // Perform a DFS walk to determine the order of visit.
561 WorkList.push_back(Node);
563 Node = WorkList.pop_back_val();
564 Scopes.push_back(Node);
565 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
566 unsigned NumChildren = Children.size();
567 OpenChildren[Node] = NumChildren;
568 for (unsigned i = 0; i != NumChildren; ++i) {
569 MachineDomTreeNode *Child = Children[i];
570 ParentMap[Child] = Node;
571 WorkList.push_back(Child);
573 } while (!WorkList.empty());
576 bool Changed = false;
577 for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
578 MachineDomTreeNode *Node = Scopes[i];
579 MachineBasicBlock *MBB = Node->getBlock();
581 Changed |= ProcessBlock(MBB);
582 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
583 ExitScopeIfDone(Node, OpenChildren, ParentMap);
589 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
590 TII = MF.getTarget().getInstrInfo();
591 TRI = MF.getTarget().getRegisterInfo();
592 MRI = &MF.getRegInfo();
593 AA = &getAnalysis<AliasAnalysis>();
594 DT = &getAnalysis<MachineDominatorTree>();
595 AllocatableRegs = TRI->getAllocatableSet(MF);
596 ReservedRegs = TRI->getReservedRegs(MF);
597 return PerformCSE(DT->getRootNode());