1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "machine-cse"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/MachineDominators.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/ScopedHashTable.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/RecyclingAllocator.h"
31 STATISTIC(NumCoalesces, "Number of copies coalesced");
32 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
33 STATISTIC(NumPhysCSEs,
34 "Number of physreg referencing common subexpr eliminated");
35 STATISTIC(NumCrossBBCSEs,
36 "Number of cross-MBB physreg referencing CS eliminated");
37 STATISTIC(NumCommutes, "Number of copies coalesced after commuting");
40 class MachineCSE : public MachineFunctionPass {
41 const TargetInstrInfo *TII;
42 const TargetRegisterInfo *TRI;
44 MachineDominatorTree *DT;
45 MachineRegisterInfo *MRI;
47 static char ID; // Pass identification
48 MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(5), CurrVN(0) {
49 initializeMachineCSEPass(*PassRegistry::getPassRegistry());
52 virtual bool runOnMachineFunction(MachineFunction &MF);
54 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
56 MachineFunctionPass::getAnalysisUsage(AU);
57 AU.addRequired<AliasAnalysis>();
58 AU.addPreservedID(MachineLoopInfoID);
59 AU.addRequired<MachineDominatorTree>();
60 AU.addPreserved<MachineDominatorTree>();
63 virtual void releaseMemory() {
66 AllocatableRegs.clear();
71 const unsigned LookAheadLimit;
72 typedef RecyclingAllocator<BumpPtrAllocator,
73 ScopedHashTableVal<MachineInstr*, unsigned> > AllocatorTy;
74 typedef ScopedHashTable<MachineInstr*, unsigned,
75 MachineInstrExpressionTrait, AllocatorTy> ScopedHTType;
76 typedef ScopedHTType::ScopeTy ScopeType;
77 DenseMap<MachineBasicBlock*, ScopeType*> ScopeMap;
79 SmallVector<MachineInstr*, 64> Exps;
81 BitVector AllocatableRegs;
82 BitVector ReservedRegs;
84 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
85 bool isPhysDefTriviallyDead(unsigned Reg,
86 MachineBasicBlock::const_iterator I,
87 MachineBasicBlock::const_iterator E) const;
88 bool hasLivePhysRegDefUses(const MachineInstr *MI,
89 const MachineBasicBlock *MBB,
90 SmallSet<unsigned,8> &PhysRefs,
91 SmallVector<unsigned,2> &PhysDefs) const;
92 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
93 SmallSet<unsigned,8> &PhysRefs,
94 SmallVector<unsigned,2> &PhysDefs,
95 bool &NonLocal) const;
96 bool isCSECandidate(MachineInstr *MI);
97 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
98 MachineInstr *CSMI, MachineInstr *MI);
99 void EnterScope(MachineBasicBlock *MBB);
100 void ExitScope(MachineBasicBlock *MBB);
101 bool ProcessBlock(MachineBasicBlock *MBB);
102 void ExitScopeIfDone(MachineDomTreeNode *Node,
103 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren);
104 bool PerformCSE(MachineDomTreeNode *Node);
106 } // end anonymous namespace
108 char MachineCSE::ID = 0;
109 char &llvm::MachineCSEID = MachineCSE::ID;
110 INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
111 "Machine Common Subexpression Elimination", false, false)
112 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
113 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
114 INITIALIZE_PASS_END(MachineCSE, "machine-cse",
115 "Machine Common Subexpression Elimination", false, false)
117 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
118 MachineBasicBlock *MBB) {
119 bool Changed = false;
120 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
121 MachineOperand &MO = MI->getOperand(i);
122 if (!MO.isReg() || !MO.isUse())
124 unsigned Reg = MO.getReg();
125 if (!TargetRegisterInfo::isVirtualRegister(Reg))
127 if (!MRI->hasOneNonDBGUse(Reg))
128 // Only coalesce single use copies. This ensure the copy will be
131 MachineInstr *DefMI = MRI->getVRegDef(Reg);
132 if (DefMI->getParent() != MBB)
134 if (!DefMI->isCopy())
136 unsigned SrcReg = DefMI->getOperand(1).getReg();
137 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
139 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
141 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg)))
143 DEBUG(dbgs() << "Coalescing: " << *DefMI);
144 DEBUG(dbgs() << "*** to: " << *MI);
146 MRI->clearKillFlags(SrcReg);
147 DefMI->eraseFromParent();
156 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
157 MachineBasicBlock::const_iterator I,
158 MachineBasicBlock::const_iterator E) const {
159 unsigned LookAheadLeft = LookAheadLimit;
160 while (LookAheadLeft) {
161 // Skip over dbg_value's.
162 while (I != E && I->isDebugValue())
166 // Reached end of block, register is obviously dead.
169 bool SeenDef = false;
170 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
171 const MachineOperand &MO = I->getOperand(i);
172 if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
174 if (!MO.isReg() || !MO.getReg())
176 if (!TRI->regsOverlap(MO.getReg(), Reg))
184 // See a def of Reg (or an alias) before encountering any use, it's
194 /// hasLivePhysRegDefUses - Return true if the specified instruction read/write
195 /// physical registers (except for dead defs of physical registers). It also
196 /// returns the physical register def by reference if it's the only one and the
197 /// instruction does not uses a physical register.
198 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
199 const MachineBasicBlock *MBB,
200 SmallSet<unsigned,8> &PhysRefs,
201 SmallVector<unsigned,2> &PhysDefs) const{
202 MachineBasicBlock::const_iterator I = MI; I = llvm::next(I);
203 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
204 const MachineOperand &MO = MI->getOperand(i);
207 unsigned Reg = MO.getReg();
210 if (TargetRegisterInfo::isVirtualRegister(Reg))
212 // If the def is dead, it's ok. But the def may not marked "dead". That's
213 // common since this pass is run before livevariables. We can scan
214 // forward a few instructions and check if it is obviously dead.
216 (MO.isDead() || isPhysDefTriviallyDead(Reg, I, MBB->end())))
218 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
219 PhysRefs.insert(*AI);
221 PhysDefs.push_back(Reg);
224 return !PhysRefs.empty();
227 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
228 SmallSet<unsigned,8> &PhysRefs,
229 SmallVector<unsigned,2> &PhysDefs,
230 bool &NonLocal) const {
231 // For now conservatively returns false if the common subexpression is
232 // not in the same basic block as the given instruction. The only exception
233 // is if the common subexpression is in the sole predecessor block.
234 const MachineBasicBlock *MBB = MI->getParent();
235 const MachineBasicBlock *CSMBB = CSMI->getParent();
237 bool CrossMBB = false;
239 if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
242 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
243 if (AllocatableRegs.test(PhysDefs[i]) || ReservedRegs.test(PhysDefs[i]))
244 // Avoid extending live range of physical registers if they are
245 //allocatable or reserved.
250 MachineBasicBlock::const_iterator I = CSMI; I = llvm::next(I);
251 MachineBasicBlock::const_iterator E = MI;
252 MachineBasicBlock::const_iterator EE = CSMBB->end();
253 unsigned LookAheadLeft = LookAheadLimit;
254 while (LookAheadLeft) {
255 // Skip over dbg_value's.
256 while (I != E && I != EE && I->isDebugValue())
260 assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
272 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
273 const MachineOperand &MO = I->getOperand(i);
274 // RegMasks go on instructions like calls that clobber lots of physregs.
275 // Don't attempt to CSE across such an instruction.
278 if (!MO.isReg() || !MO.isDef())
280 unsigned MOReg = MO.getReg();
281 if (TargetRegisterInfo::isVirtualRegister(MOReg))
283 if (PhysRefs.count(MOReg))
294 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
295 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
296 MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
300 if (MI->isCopyLike())
303 // Ignore stuff that we obviously can't move.
304 if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
305 MI->hasUnmodeledSideEffects())
309 // Okay, this instruction does a load. As a refinement, we allow the target
310 // to decide whether the loaded value is actually a constant. If so, we can
311 // actually use it as a load.
312 if (!MI->isInvariantLoad(AA))
313 // FIXME: we should be able to hoist loads with no other side effects if
314 // there are no other instructions which can change memory in this loop.
315 // This is a trivial form of alias analysis.
321 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
322 /// common expression that defines Reg.
323 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
324 MachineInstr *CSMI, MachineInstr *MI) {
325 // FIXME: Heuristics that works around the lack the live range splitting.
327 // If CSReg is used at all uses of Reg, CSE should not increase register
328 // pressure of CSReg.
329 bool MayIncreasePressure = true;
330 if (TargetRegisterInfo::isVirtualRegister(CSReg) &&
331 TargetRegisterInfo::isVirtualRegister(Reg)) {
332 MayIncreasePressure = false;
333 SmallPtrSet<MachineInstr*, 8> CSUses;
334 for (MachineRegisterInfo::use_nodbg_iterator I =MRI->use_nodbg_begin(CSReg),
335 E = MRI->use_nodbg_end(); I != E; ++I) {
336 MachineInstr *Use = &*I;
339 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
340 E = MRI->use_nodbg_end(); I != E; ++I) {
341 MachineInstr *Use = &*I;
342 if (!CSUses.count(Use)) {
343 MayIncreasePressure = true;
348 if (!MayIncreasePressure) return true;
350 // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
351 // an immediate predecessor. We don't want to increase register pressure and
352 // end up causing other computation to be spilled.
353 if (MI->isAsCheapAsAMove()) {
354 MachineBasicBlock *CSBB = CSMI->getParent();
355 MachineBasicBlock *BB = MI->getParent();
356 if (CSBB != BB && !CSBB->isSuccessor(BB))
360 // Heuristics #2: If the expression doesn't not use a vr and the only use
361 // of the redundant computation are copies, do not cse.
362 bool HasVRegUse = false;
363 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
364 const MachineOperand &MO = MI->getOperand(i);
365 if (MO.isReg() && MO.isUse() &&
366 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
372 bool HasNonCopyUse = false;
373 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
374 E = MRI->use_nodbg_end(); I != E; ++I) {
375 MachineInstr *Use = &*I;
377 if (!Use->isCopyLike()) {
378 HasNonCopyUse = true;
386 // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
387 // it unless the defined value is already used in the BB of the new use.
389 SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
390 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg),
391 E = MRI->use_nodbg_end(); I != E; ++I) {
392 MachineInstr *Use = &*I;
393 HasPHI |= Use->isPHI();
394 CSBBs.insert(Use->getParent());
399 return CSBBs.count(MI->getParent());
402 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
403 DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
404 ScopeType *Scope = new ScopeType(VNT);
405 ScopeMap[MBB] = Scope;
408 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
409 DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
410 DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
411 assert(SI != ScopeMap.end());
416 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
417 bool Changed = false;
419 SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
420 SmallVector<unsigned, 2> ImplicitDefsToUpdate;
421 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
422 MachineInstr *MI = &*I;
425 if (!isCSECandidate(MI))
428 bool FoundCSE = VNT.count(MI);
430 // Look for trivial copy coalescing opportunities.
431 if (PerformTrivialCoalescing(MI, MBB)) {
434 // After coalescing MI itself may become a copy.
435 if (MI->isCopyLike())
437 FoundCSE = VNT.count(MI);
441 // Commute commutable instructions.
442 bool Commuted = false;
443 if (!FoundCSE && MI->isCommutable()) {
444 MachineInstr *NewMI = TII->commuteInstruction(MI);
447 FoundCSE = VNT.count(NewMI);
449 // New instruction. It doesn't need to be kept.
450 NewMI->eraseFromParent();
452 } else if (!FoundCSE)
453 // MI was changed but it didn't help, commute it back!
454 (void)TII->commuteInstruction(MI);
458 // If the instruction defines physical registers and the values *may* be
459 // used, then it's not safe to replace it with a common subexpression.
460 // It's also not safe if the instruction uses physical registers.
461 bool CrossMBBPhysDef = false;
462 SmallSet<unsigned, 8> PhysRefs;
463 SmallVector<unsigned, 2> PhysDefs;
464 if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs, PhysDefs)) {
467 // ... Unless the CS is local or is in the sole predecessor block
468 // and it also defines the physical register which is not clobbered
469 // in between and the physical register uses were not clobbered.
470 unsigned CSVN = VNT.lookup(MI);
471 MachineInstr *CSMI = Exps[CSVN];
472 if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
477 VNT.insert(MI, CurrVN++);
482 // Found a common subexpression, eliminate it.
483 unsigned CSVN = VNT.lookup(MI);
484 MachineInstr *CSMI = Exps[CSVN];
485 DEBUG(dbgs() << "Examining: " << *MI);
486 DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
488 // Check if it's profitable to perform this CSE.
490 unsigned NumDefs = MI->getDesc().getNumDefs() +
491 MI->getDesc().getNumImplicitDefs();
493 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
494 MachineOperand &MO = MI->getOperand(i);
495 if (!MO.isReg() || !MO.isDef())
497 unsigned OldReg = MO.getReg();
498 unsigned NewReg = CSMI->getOperand(i).getReg();
500 // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
501 // we should make sure it is not dead at CSMI.
502 if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
503 ImplicitDefsToUpdate.push_back(i);
504 if (OldReg == NewReg) {
509 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
510 TargetRegisterInfo::isVirtualRegister(NewReg) &&
511 "Do not CSE physical register defs!");
513 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
514 DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
519 // Don't perform CSE if the result of the old instruction cannot exist
520 // within the register class of the new instruction.
521 const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
522 if (!MRI->constrainRegClass(NewReg, OldRC)) {
523 DEBUG(dbgs() << "*** Not the same register class, avoid CSE!\n");
528 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
532 // Actually perform the elimination.
534 for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
535 MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
536 MRI->clearKillFlags(CSEPairs[i].second);
539 // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
540 // we should make sure it is not dead at CSMI.
541 for (unsigned i = 0, e = ImplicitDefsToUpdate.size(); i != e; ++i)
542 CSMI->getOperand(ImplicitDefsToUpdate[i]).setIsDead(false);
544 if (CrossMBBPhysDef) {
545 // Add physical register defs now coming in from a predecessor to MBB
547 while (!PhysDefs.empty()) {
548 unsigned LiveIn = PhysDefs.pop_back_val();
549 if (!MBB->isLiveIn(LiveIn))
550 MBB->addLiveIn(LiveIn);
555 MI->eraseFromParent();
557 if (!PhysRefs.empty())
563 VNT.insert(MI, CurrVN++);
567 ImplicitDefsToUpdate.clear();
573 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
574 /// dominator tree node if its a leaf or all of its children are done. Walk
575 /// up the dominator tree to destroy ancestors which are now done.
577 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
578 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren) {
579 if (OpenChildren[Node])
583 ExitScope(Node->getBlock());
585 // Now traverse upwards to pop ancestors whose offsprings are all done.
586 while (MachineDomTreeNode *Parent = Node->getIDom()) {
587 unsigned Left = --OpenChildren[Parent];
590 ExitScope(Parent->getBlock());
595 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
596 SmallVector<MachineDomTreeNode*, 32> Scopes;
597 SmallVector<MachineDomTreeNode*, 8> WorkList;
598 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
602 // Perform a DFS walk to determine the order of visit.
603 WorkList.push_back(Node);
605 Node = WorkList.pop_back_val();
606 Scopes.push_back(Node);
607 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
608 unsigned NumChildren = Children.size();
609 OpenChildren[Node] = NumChildren;
610 for (unsigned i = 0; i != NumChildren; ++i) {
611 MachineDomTreeNode *Child = Children[i];
612 WorkList.push_back(Child);
614 } while (!WorkList.empty());
617 bool Changed = false;
618 for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
619 MachineDomTreeNode *Node = Scopes[i];
620 MachineBasicBlock *MBB = Node->getBlock();
622 Changed |= ProcessBlock(MBB);
623 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
624 ExitScopeIfDone(Node, OpenChildren);
630 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
631 TII = MF.getTarget().getInstrInfo();
632 TRI = MF.getTarget().getRegisterInfo();
633 MRI = &MF.getRegInfo();
634 AA = &getAnalysis<AliasAnalysis>();
635 DT = &getAnalysis<MachineDominatorTree>();
636 AllocatableRegs = TRI->getAllocatableSet(MF);
637 ReservedRegs = TRI->getReservedRegs(MF);
638 return PerformCSE(DT->getRootNode());