1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/MC/MCRegisterInfo.h"
30 class MachineFunction;
32 template<class T> class SmallVectorImpl;
36 class TargetRegisterClass {
38 typedef const MCPhysReg* iterator;
39 typedef const MCPhysReg* const_iterator;
40 typedef const MVT::SimpleValueType* vt_iterator;
41 typedef const TargetRegisterClass* const * sc_iterator;
43 // Instance variables filled by tablegen, do not use!
44 const MCRegisterClass *MC;
45 const vt_iterator VTs;
46 const uint32_t *SubClassMask;
47 const uint16_t *SuperRegIndices;
48 const sc_iterator SuperClasses;
49 ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
51 /// getID() - Return the register class ID number.
53 unsigned getID() const { return MC->getID(); }
55 /// getName() - Return the register class name for debugging.
57 const char *getName() const { return MC->getName(); }
59 /// begin/end - Return all of the registers in this class.
61 iterator begin() const { return MC->begin(); }
62 iterator end() const { return MC->end(); }
64 /// getNumRegs - Return the number of registers in this class.
66 unsigned getNumRegs() const { return MC->getNumRegs(); }
68 /// getRegister - Return the specified register in the class.
70 unsigned getRegister(unsigned i) const {
71 return MC->getRegister(i);
74 /// contains - Return true if the specified register is included in this
75 /// register class. This does not include virtual registers.
76 bool contains(unsigned Reg) const {
77 return MC->contains(Reg);
80 /// contains - Return true if both registers are in this class.
81 bool contains(unsigned Reg1, unsigned Reg2) const {
82 return MC->contains(Reg1, Reg2);
85 /// getSize - Return the size of the register in bytes, which is also the size
86 /// of a stack slot allocated to hold a spilled copy of this register.
87 unsigned getSize() const { return MC->getSize(); }
89 /// getAlignment - Return the minimum required alignment for a register of
91 unsigned getAlignment() const { return MC->getAlignment(); }
93 /// getCopyCost - Return the cost of copying a value between two registers in
94 /// this class. A negative number means the register class is very expensive
95 /// to copy e.g. status flag register classes.
96 int getCopyCost() const { return MC->getCopyCost(); }
98 /// isAllocatable - Return true if this register class may be used to create
99 /// virtual registers.
100 bool isAllocatable() const { return MC->isAllocatable(); }
102 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
104 bool hasType(EVT vt) const {
105 for(int i = 0; VTs[i] != MVT::Other; ++i)
106 if (EVT(VTs[i]) == vt)
111 /// vt_begin / vt_end - Loop over all of the value types that can be
112 /// represented by values in this register class.
113 vt_iterator vt_begin() const {
117 vt_iterator vt_end() const {
119 while (*I != MVT::Other) ++I;
123 /// hasSubClass - return true if the specified TargetRegisterClass
124 /// is a proper sub-class of this TargetRegisterClass.
125 bool hasSubClass(const TargetRegisterClass *RC) const {
126 return RC != this && hasSubClassEq(RC);
129 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
131 bool hasSubClassEq(const TargetRegisterClass *RC) const {
132 unsigned ID = RC->getID();
133 return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
136 /// hasSuperClass - return true if the specified TargetRegisterClass is a
137 /// proper super-class of this TargetRegisterClass.
138 bool hasSuperClass(const TargetRegisterClass *RC) const {
139 return RC->hasSubClass(this);
142 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
144 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
145 return RC->hasSubClassEq(this);
148 /// getSubClassMask - Returns a bit vector of subclasses, including this one.
149 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
151 const uint32_t *getSubClassMask() const {
155 /// getSuperRegIndices - Returns a 0-terminated list of sub-register indices
156 /// that project some super-register class into this register class. The list
157 /// has an entry for each Idx such that:
159 /// There exists SuperRC where:
160 /// For all Reg in SuperRC:
161 /// this->contains(Reg:Idx)
163 const uint16_t *getSuperRegIndices() const {
164 return SuperRegIndices;
167 /// getSuperClasses - Returns a NULL terminated list of super-classes. The
168 /// classes are ordered by ID which is also a topological ordering from large
169 /// to small classes. The list does NOT include the current class.
170 sc_iterator getSuperClasses() const {
174 /// isASubClass - return true if this TargetRegisterClass is a subset
175 /// class of at least one other TargetRegisterClass.
176 bool isASubClass() const {
177 return SuperClasses[0] != 0;
180 /// getRawAllocationOrder - Returns the preferred order for allocating
181 /// registers from this register class in MF. The raw order comes directly
182 /// from the .td file and may include reserved registers that are not
183 /// allocatable. Register allocators should also make sure to allocate
184 /// callee-saved registers only after all the volatiles are used. The
185 /// RegisterClassInfo class provides filtered allocation orders with
186 /// callee-saved registers moved to the end.
188 /// The MachineFunction argument can be used to tune the allocatable
189 /// registers based on the characteristics of the function, subtarget, or
192 /// By default, this method returns all registers in the class.
194 ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
195 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
199 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
200 /// registers. These are used by codegen, not by MC.
201 struct TargetRegisterInfoDesc {
202 unsigned CostPerUse; // Extra cost of instructions using register.
203 bool inAllocatableClass; // Register belongs to an allocatable regclass.
206 /// Each TargetRegisterClass has a per register weight, and weight
207 /// limit which must be less than the limits of its pressure sets.
208 struct RegClassWeight {
210 unsigned WeightLimit;
213 /// TargetRegisterInfo base class - We assume that the target defines a static
214 /// array of TargetRegisterDesc objects that represent all of the machine
215 /// registers that the target has. As such, we simply have to track a pointer
216 /// to this array so that we can turn register number into a register
219 class TargetRegisterInfo : public MCRegisterInfo {
221 typedef const TargetRegisterClass * const * regclass_iterator;
223 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
224 const char *const *SubRegIndexNames; // Names of subreg indexes.
225 // Pointer to array of lane masks, one per sub-reg index.
226 const unsigned *SubRegIndexLaneMasks;
228 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
231 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
232 regclass_iterator RegClassBegin,
233 regclass_iterator RegClassEnd,
234 const char *const *SRINames,
235 const unsigned *SRILaneMasks);
236 virtual ~TargetRegisterInfo();
239 // Register numbers can represent physical registers, virtual registers, and
240 // sometimes stack slots. The unsigned values are divided into these ranges:
242 // 0 Not a register, can be used as a sentinel.
243 // [1;2^30) Physical registers assigned by TableGen.
244 // [2^30;2^31) Stack slots. (Rarely used.)
245 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
247 // Further sentinels can be allocated from the small negative integers.
248 // DenseMapInfo<unsigned> uses -1u and -2u.
250 /// isStackSlot - Sometimes it is useful the be able to store a non-negative
251 /// frame index in a variable that normally holds a register. isStackSlot()
252 /// returns true if Reg is in the range used for stack slots.
254 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
255 /// slots, so if a variable may contains a stack slot, always check
256 /// isStackSlot() first.
258 static bool isStackSlot(unsigned Reg) {
259 return int(Reg) >= (1 << 30);
262 /// stackSlot2Index - Compute the frame index from a register value
263 /// representing a stack slot.
264 static int stackSlot2Index(unsigned Reg) {
265 assert(isStackSlot(Reg) && "Not a stack slot");
266 return int(Reg - (1u << 30));
269 /// index2StackSlot - Convert a non-negative frame index to a stack slot
271 static unsigned index2StackSlot(int FI) {
272 assert(FI >= 0 && "Cannot hold a negative frame index.");
273 return FI + (1u << 30);
276 /// isPhysicalRegister - Return true if the specified register number is in
277 /// the physical register namespace.
278 static bool isPhysicalRegister(unsigned Reg) {
279 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
283 /// isVirtualRegister - Return true if the specified register number is in
284 /// the virtual register namespace.
285 static bool isVirtualRegister(unsigned Reg) {
286 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
290 /// virtReg2Index - Convert a virtual register number to a 0-based index.
291 /// The first virtual register in a function will get the index 0.
292 static unsigned virtReg2Index(unsigned Reg) {
293 assert(isVirtualRegister(Reg) && "Not a virtual register");
294 return Reg & ~(1u << 31);
297 /// index2VirtReg - Convert a 0-based index to a virtual register number.
298 /// This is the inverse operation of VirtReg2IndexFunctor below.
299 static unsigned index2VirtReg(unsigned Index) {
300 return Index | (1u << 31);
303 /// getMinimalPhysRegClass - Returns the Register Class of a physical
304 /// register of the given type, picking the most sub register class of
305 /// the right type that contains this physreg.
306 const TargetRegisterClass *
307 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
309 /// getAllocatableClass - Return the maximal subclass of the given register
310 /// class that is alloctable, or NULL.
311 const TargetRegisterClass *
312 getAllocatableClass(const TargetRegisterClass *RC) const;
314 /// getAllocatableSet - Returns a bitset indexed by register number
315 /// indicating if a register is allocatable or not. If a register class is
316 /// specified, returns the subset for the class.
317 BitVector getAllocatableSet(const MachineFunction &MF,
318 const TargetRegisterClass *RC = NULL) const;
320 /// getCostPerUse - Return the additional cost of using this register instead
321 /// of other registers in its class.
322 unsigned getCostPerUse(unsigned RegNo) const {
323 return InfoDesc[RegNo].CostPerUse;
326 /// isInAllocatableClass - Return true if the register is in the allocation
327 /// of any register class.
328 bool isInAllocatableClass(unsigned RegNo) const {
329 return InfoDesc[RegNo].inAllocatableClass;
332 /// getSubRegIndexName - Return the human-readable symbolic target-specific
333 /// name for the specified SubRegIndex.
334 const char *getSubRegIndexName(unsigned SubIdx) const {
335 assert(SubIdx && SubIdx < getNumSubRegIndices() &&
336 "This is not a subregister index");
337 return SubRegIndexNames[SubIdx-1];
340 /// getSubRegIndexLaneMask - Return a bitmask representing the parts of a
341 /// register that are covered by SubIdx.
343 /// Lane masks for sub-register indices are similar to register units for
344 /// physical registers. The individual bits in a lane mask can't be assigned
345 /// any specific meaning. They can be used to check if two sub-register
348 /// If the target has a register such that:
350 /// getSubReg(Reg, A) overlaps getSubReg(Reg, B)
354 /// getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B) != 0
356 /// The converse is not necessarily true. If two lane masks have a common
357 /// bit, the corresponding sub-registers may not overlap, but it can be
358 /// assumed that they usually will.
359 unsigned getSubRegIndexLaneMask(unsigned SubIdx) const {
360 // SubIdx == 0 is allowed, it has the lane mask ~0u.
361 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
362 return SubRegIndexLaneMasks[SubIdx];
365 /// regsOverlap - Returns true if the two registers are equal or alias each
366 /// other. The registers may be virtual register.
367 bool regsOverlap(unsigned regA, unsigned regB) const {
368 if (regA == regB) return true;
369 if (isVirtualRegister(regA) || isVirtualRegister(regB))
372 // Regunits are numerically ordered. Find a common unit.
373 MCRegUnitIterator RUA(regA, this);
374 MCRegUnitIterator RUB(regB, this);
376 if (*RUA == *RUB) return true;
377 if (*RUA < *RUB) ++RUA;
379 } while (RUA.isValid() && RUB.isValid());
383 /// hasRegUnit - Returns true if Reg contains RegUnit.
384 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
385 for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
386 if (*Units == RegUnit)
391 /// getCalleeSavedRegs - Return a null-terminated list of all of the
392 /// callee saved registers on this target. The register should be in the
393 /// order of desired callee-save stack frame offset. The first register is
394 /// closest to the incoming stack pointer if stack grows down, and vice versa.
396 virtual const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF = 0)
399 /// getCallPreservedMask - Return a mask of call-preserved registers for the
400 /// given calling convention on the current sub-target. The mask should
401 /// include all call-preserved aliases. This is used by the register
402 /// allocator to determine which registers can be live across a call.
404 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
405 /// A set bit indicates that all bits of the corresponding register are
406 /// preserved across the function call. The bit mask is expected to be
407 /// sub-register complete, i.e. if A is preserved, so are all its
410 /// Bits are numbered from the LSB, so the bit for physical register Reg can
411 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
413 /// A NULL pointer means that no register mask will be used, and call
414 /// instructions should use implicit-def operands to indicate call clobbered
417 virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const {
418 // The default mask clobbers everything. All targets should override.
422 /// getReservedRegs - Returns a bitset indexed by physical register number
423 /// indicating if a register is a special register that has particular uses
424 /// and should be considered unavailable at all times, e.g. SP, RA. This is
425 /// used by register scavenger to determine what registers are free.
426 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
428 /// getMatchingSuperReg - Return a super-register of the specified register
429 /// Reg so its sub-register of index SubIdx is Reg.
430 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
431 const TargetRegisterClass *RC) const {
432 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
435 /// getMatchingSuperRegClass - Return a subclass of the specified register
436 /// class A so that each register in it has a sub-register of the
437 /// specified sub-register index which is in the specified register class B.
439 /// TableGen will synthesize missing A sub-classes.
440 virtual const TargetRegisterClass *
441 getMatchingSuperRegClass(const TargetRegisterClass *A,
442 const TargetRegisterClass *B, unsigned Idx) const;
444 /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that
445 /// supports the sub-register index Idx.
446 /// If no such sub-class exists, return NULL.
447 /// If all registers in RC already have an Idx sub-register, return RC.
449 /// TableGen generates a version of this function that is good enough in most
450 /// cases. Targets can override if they have constraints that TableGen
451 /// doesn't understand. For example, the x86 sub_8bit sub-register index is
452 /// supported by the full GR32 register class in 64-bit mode, but only by the
453 /// GR32_ABCD regiister class in 32-bit mode.
455 /// TableGen will synthesize missing RC sub-classes.
456 virtual const TargetRegisterClass *
457 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
458 assert(Idx == 0 && "Target has no sub-registers");
462 /// composeSubRegIndices - Return the subregister index you get from composing
463 /// two subregister indices.
465 /// The special null sub-register index composes as the identity.
467 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
468 /// returns c. Note that composeSubRegIndices does not tell you about illegal
469 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
470 /// b, composeSubRegIndices doesn't tell you.
472 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
473 /// ssub_0:S0 - ssub_3:S3 subregs.
474 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
476 unsigned composeSubRegIndices(unsigned a, unsigned b) const {
479 return composeSubRegIndicesImpl(a, b);
483 /// Overridden by TableGen in targets that have sub-registers.
484 virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
485 llvm_unreachable("Target has no sub-registers");
489 /// getCommonSuperRegClass - Find a common super-register class if it exists.
491 /// Find a register class, SuperRC and two sub-register indices, PreA and
494 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
496 /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
498 /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
500 /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
501 /// requirements, and there is no register class with a smaller spill size
502 /// that satisfies the requirements.
504 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
506 /// Either of the PreA and PreB sub-register indices may be returned as 0. In
507 /// that case, the returned register class will be a sub-class of the
508 /// corresponding argument register class.
510 /// The function returns NULL if no register class can be found.
512 const TargetRegisterClass*
513 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
514 const TargetRegisterClass *RCB, unsigned SubB,
515 unsigned &PreA, unsigned &PreB) const;
517 //===--------------------------------------------------------------------===//
518 // Register Class Information
521 /// Register class iterators
523 regclass_iterator regclass_begin() const { return RegClassBegin; }
524 regclass_iterator regclass_end() const { return RegClassEnd; }
526 unsigned getNumRegClasses() const {
527 return (unsigned)(regclass_end()-regclass_begin());
530 /// getRegClass - Returns the register class associated with the enumeration
531 /// value. See class MCOperandInfo.
532 const TargetRegisterClass *getRegClass(unsigned i) const {
533 assert(i < getNumRegClasses() && "Register Class ID out of range");
534 return RegClassBegin[i];
537 /// getCommonSubClass - find the largest common subclass of A and B. Return
538 /// NULL if there is no common subclass.
539 const TargetRegisterClass *
540 getCommonSubClass(const TargetRegisterClass *A,
541 const TargetRegisterClass *B) const;
543 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
544 /// values. If a target supports multiple different pointer register classes,
545 /// kind specifies which one is indicated.
546 virtual const TargetRegisterClass *
547 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
548 llvm_unreachable("Target didn't implement getPointerRegClass!");
551 /// getCrossCopyRegClass - Returns a legal register class to copy a register
552 /// in the specified class to or from. If it is possible to copy the register
553 /// directly without using a cross register class copy, return the specified
554 /// RC. Returns NULL if it is not possible to copy between a two registers of
555 /// the specified class.
556 virtual const TargetRegisterClass *
557 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
561 /// getLargestLegalSuperClass - Returns the largest super class of RC that is
562 /// legal to use in the current sub-target and has the same spill size.
563 /// The returned register class can be used to create virtual registers which
564 /// means that all its registers can be copied and spilled.
565 virtual const TargetRegisterClass*
566 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
567 /// The default implementation is very conservative and doesn't allow the
568 /// register allocator to inflate register classes.
572 /// getRegPressureLimit - Return the register pressure "high water mark" for
573 /// the specific register class. The scheduler is in high register pressure
574 /// mode (for the specific register class) if it goes over the limit.
576 /// Note: this is the old register pressure model that relies on a manually
577 /// specified representative register class per value type.
578 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
579 MachineFunction &MF) const {
583 /// Get the weight in units of pressure for this register class.
584 virtual const RegClassWeight &getRegClassWeight(
585 const TargetRegisterClass *RC) const = 0;
587 /// Get the weight in units of pressure for this register unit.
588 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
590 /// Get the number of dimensions of register pressure.
591 virtual unsigned getNumRegPressureSets() const = 0;
593 /// Get the name of this register unit pressure set.
594 virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
596 /// Get the register unit pressure limit for this dimension.
597 /// This limit must be adjusted dynamically for reserved registers.
598 virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0;
600 /// Get the dimensions of register pressure impacted by this register class.
601 /// Returns a -1 terminated array of pressure set IDs.
602 virtual const int *getRegClassPressureSets(
603 const TargetRegisterClass *RC) const = 0;
605 /// Get the dimensions of register pressure impacted by this register unit.
606 /// Returns a -1 terminated array of pressure set IDs.
607 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
609 /// Get a list of 'hint' registers that the register allocator should try
610 /// first when allocating a physical register for the virtual register
611 /// VirtReg. These registers are effectively moved to the front of the
612 /// allocation order.
614 /// The Order argument is the allocation order for VirtReg's register class
615 /// as returned from RegisterClassInfo::getOrder(). The hint registers must
616 /// come from Order, and they must not be reserved.
618 /// The default implementation of this function can resolve
619 /// target-independent hints provided to MRI::setRegAllocationHint with
620 /// HintType == 0. Targets that override this function should defer to the
621 /// default implementation if they have no reason to change the allocation
622 /// order for VirtReg. There may be target-independent hints.
623 virtual void getRegAllocationHints(unsigned VirtReg,
624 ArrayRef<MCPhysReg> Order,
625 SmallVectorImpl<MCPhysReg> &Hints,
626 const MachineFunction &MF,
627 const VirtRegMap *VRM = 0) const;
629 /// avoidWriteAfterWrite - Return true if the register allocator should avoid
630 /// writing a register from RC in two consecutive instructions.
631 /// This can avoid pipeline stalls on certain architectures.
632 /// It does cause increased register pressure, though.
633 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
637 /// UpdateRegAllocHint - A callback to allow target a chance to update
638 /// register allocation hints when a register is "changed" (e.g. coalesced)
639 /// to another register. e.g. On ARM, some virtual registers should target
640 /// register pairs, if one of pair is coalesced to another register, the
641 /// allocation hint of the other half of the pair should be changed to point
642 /// to the new register.
643 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
644 MachineFunction &MF) const {
648 /// requiresRegisterScavenging - returns true if the target requires (and can
649 /// make use of) the register scavenger.
650 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
654 /// useFPForScavengingIndex - returns true if the target wants to use
655 /// frame pointer based accesses to spill to the scavenger emergency spill
657 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
661 /// requiresFrameIndexScavenging - returns true if the target requires post
662 /// PEI scavenging of registers for materializing frame index constants.
663 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
667 /// requiresVirtualBaseRegisters - Returns true if the target wants the
668 /// LocalStackAllocation pass to be run and virtual base registers
669 /// used for more efficient stack access.
670 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
674 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
675 /// the stack frame of the given function for the specified register. e.g. On
676 /// x86, if the frame register is required, the first fixed stack object is
677 /// reserved as its spill slot. This tells PEI not to create a new stack frame
678 /// object for the given register. It should be called only after
679 /// processFunctionBeforeCalleeSavedScan().
680 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
681 int &FrameIdx) const {
685 /// trackLivenessAfterRegAlloc - returns true if the live-ins should be tracked
686 /// after register allocation.
687 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
691 /// needsStackRealignment - true if storage within the function requires the
692 /// stack pointer to be aligned more than the normal calling convention calls
694 virtual bool needsStackRealignment(const MachineFunction &MF) const {
698 /// getFrameIndexInstrOffset - Get the offset from the referenced frame
699 /// index in the instruction, if there is one.
700 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
705 /// needsFrameBaseReg - Returns true if the instruction's frame index
706 /// reference would be better served by a base register other than FP
707 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
708 /// references it should create new base registers for.
709 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
713 /// materializeFrameBaseRegister - Insert defining instruction(s) for
714 /// BaseReg to be a pointer to FrameIdx before insertion point I.
715 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
716 unsigned BaseReg, int FrameIdx,
717 int64_t Offset) const {
718 llvm_unreachable("materializeFrameBaseRegister does not exist on this "
722 /// resolveFrameIndex - Resolve a frame index operand of an instruction
723 /// to reference the indicated base register plus offset instead.
724 virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
725 unsigned BaseReg, int64_t Offset) const {
726 llvm_unreachable("resolveFrameIndex does not exist on this target");
729 /// isFrameOffsetLegal - Determine whether a given offset immediate is
730 /// encodable to resolve a frame index.
731 virtual bool isFrameOffsetLegal(const MachineInstr *MI,
732 int64_t Offset) const {
733 llvm_unreachable("isFrameOffsetLegal does not exist on this target");
736 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
737 /// code insertion to eliminate call frame setup and destroy pseudo
738 /// instructions (but only if the Target is using them). It is responsible
739 /// for eliminating these instructions, replacing them with concrete
740 /// instructions. This method need only be implemented if using call frame
741 /// setup/destroy pseudo instructions.
744 eliminateCallFramePseudoInstr(MachineFunction &MF,
745 MachineBasicBlock &MBB,
746 MachineBasicBlock::iterator MI) const {
747 llvm_unreachable("Call Frame Pseudo Instructions do not exist on this "
752 /// saveScavengerRegister - Spill the register so it can be used by the
753 /// register scavenger. Return true if the register was spilled, false
754 /// otherwise. If this function does not spill the register, the scavenger
755 /// will instead spill it to the emergency spill slot.
757 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
758 MachineBasicBlock::iterator I,
759 MachineBasicBlock::iterator &UseMI,
760 const TargetRegisterClass *RC,
761 unsigned Reg) const {
765 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
766 /// frame indices from instructions which may use them. The instruction
767 /// referenced by the iterator contains an MO_FrameIndex operand which must be
768 /// eliminated by this method. This method may modify or replace the
769 /// specified instruction, as long as it keeps the iterator pointing at the
770 /// finished product. SPAdj is the SP adjustment due to call frame setup
772 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
773 int SPAdj, RegScavenger *RS=NULL) const = 0;
775 //===--------------------------------------------------------------------===//
776 /// Debug information queries.
778 /// getFrameRegister - This method should return the register used as a base
779 /// for values allocated in the current stack frame.
780 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
782 /// getCompactUnwindRegNum - This function maps the register to the number for
783 /// compact unwind encoding. Return -1 if the register isn't valid.
784 virtual int getCompactUnwindRegNum(unsigned, bool) const {
790 //===----------------------------------------------------------------------===//
791 // SuperRegClassIterator
792 //===----------------------------------------------------------------------===//
794 // Iterate over the possible super-registers for a given register class. The
795 // iterator will visit a list of pairs (Idx, Mask) corresponding to the
796 // possible classes of super-registers.
798 // Each bit mask will have at least one set bit, and each set bit in Mask
799 // corresponds to a SuperRC such that:
801 // For all Reg in SuperRC: Reg:Idx is in RC.
803 // The iterator can include (O, RC->getSubClassMask()) as the first entry which
804 // also satisfies the above requirement, assuming Reg:0 == Reg.
806 class SuperRegClassIterator {
807 const unsigned RCMaskWords;
810 const uint32_t *Mask;
813 /// Create a SuperRegClassIterator that visits all the super-register classes
814 /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
815 SuperRegClassIterator(const TargetRegisterClass *RC,
816 const TargetRegisterInfo *TRI,
817 bool IncludeSelf = false)
818 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
820 Idx(RC->getSuperRegIndices()),
821 Mask(RC->getSubClassMask()) {
826 /// Returns true if this iterator is still pointing at a valid entry.
827 bool isValid() const { return Idx; }
829 /// Returns the current sub-register index.
830 unsigned getSubReg() const { return SubReg; }
832 /// Returns the bit mask if register classes that getSubReg() projects into
834 const uint32_t *getMask() const { return Mask; }
836 /// Advance iterator to the next entry.
838 assert(isValid() && "Cannot move iterator past end.");
846 // This is useful when building IndexedMaps keyed on virtual registers
847 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
848 unsigned operator()(unsigned Reg) const {
849 return TargetRegisterInfo::virtReg2Index(Reg);
853 /// PrintReg - Helper class for printing registers on a raw_ostream.
854 /// Prints virtual and physical registers with or without a TRI instance.
857 /// %noreg - NoRegister
858 /// %vreg5 - a virtual register.
859 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
860 /// %EAX - a physical register
861 /// %physreg17 - a physical register when no TRI instance given.
863 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
866 const TargetRegisterInfo *TRI;
870 explicit PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0,
872 : TRI(tri), Reg(reg), SubIdx(subidx) {}
873 void print(raw_ostream&) const;
876 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
881 /// PrintRegUnit - Helper class for printing register units on a raw_ostream.
883 /// Register units are named after their root registers:
885 /// AL - Single root.
886 /// FP0~ST7 - Dual roots.
888 /// Usage: OS << PrintRegUnit(Unit, TRI) << '\n';
891 const TargetRegisterInfo *TRI;
894 PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri)
895 : TRI(tri), Unit(unit) {}
896 void print(raw_ostream&) const;
899 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintRegUnit &PR) {
904 } // End llvm namespace