1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CallingConv.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Attributes.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/Support/CallSite.h"
30 #include "llvm/CodeGen/SelectionDAGNodes.h"
31 #include "llvm/CodeGen/RuntimeLibcalls.h"
32 #include "llvm/Support/DebugLoc.h"
33 #include "llvm/Target/TargetCallingConv.h"
34 #include "llvm/Target/TargetMachine.h"
43 class FunctionLoweringInfo;
44 class ImmutableCallSite;
46 class MachineBasicBlock;
47 class MachineFunction;
49 class MachineJumpTableInfo;
52 template<typename T> class SmallVectorImpl;
54 class TargetRegisterClass;
55 class TargetLibraryInfo;
56 class TargetLoweringObjectFile;
61 None, // No preference
62 Source, // Follow source order.
63 RegPressure, // Scheduling for lowest register pressure.
64 Hybrid, // Scheduling for both latency and register pressure.
65 ILP, // Scheduling for ILP in low register pressure mode.
66 VLIW // Scheduling for VLIW targets.
71 //===----------------------------------------------------------------------===//
72 /// TargetLowering - This class defines information used to lower LLVM code to
73 /// legal SelectionDAG operators that the target instruction selector can accept
76 /// This class also defines callbacks that targets must implement to lower
77 /// target-specific constructs to SelectionDAG operators.
79 class TargetLowering {
80 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
81 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
83 /// LegalizeAction - This enum indicates whether operations are valid for a
84 /// target, and if not, what action should be used to make them valid.
86 Legal, // The target natively supports this operation.
87 Promote, // This operation should be executed in a larger type.
88 Expand, // Try to expand this to other ops, otherwise use a libcall.
89 Custom // Use the LowerOperation hook to implement custom lowering.
92 /// LegalizeTypeAction - This enum indicates whether a types are legal for a
93 /// target, and if not, what action should be used to make them valid.
94 enum LegalizeTypeAction {
95 TypeLegal, // The target natively supports this type.
96 TypePromoteInteger, // Replace this integer with a larger one.
97 TypeExpandInteger, // Split this integer into two of half the size.
98 TypeSoftenFloat, // Convert this float to a same size integer type.
99 TypeExpandFloat, // Split this float into two of half the size.
100 TypeScalarizeVector, // Replace this one-element vector with its element.
101 TypeSplitVector, // Split this vector into two of half the size.
102 TypeWidenVector // This vector should be widened into a larger vector.
105 enum BooleanContent { // How the target represents true/false values.
106 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
107 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
108 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
111 enum SelectSupportKind {
112 ScalarValSelect, // The target supports scalar selects (ex: cmov).
113 ScalarCondVectorVal, // The target supports selects with a scalar condition
114 // and vector values (ex: cmov).
115 VectorMaskSelect // The target supports vector selects with a vector
116 // mask (ex: x86 blends).
119 static ISD::NodeType getExtendForContent(BooleanContent Content) {
121 case UndefinedBooleanContent:
122 // Extend by adding rubbish bits.
123 return ISD::ANY_EXTEND;
124 case ZeroOrOneBooleanContent:
125 // Extend by adding zero bits.
126 return ISD::ZERO_EXTEND;
127 case ZeroOrNegativeOneBooleanContent:
128 // Extend by copying the sign bit.
129 return ISD::SIGN_EXTEND;
131 llvm_unreachable("Invalid content kind");
134 /// NOTE: The constructor takes ownership of TLOF.
135 explicit TargetLowering(const TargetMachine &TM,
136 const TargetLoweringObjectFile *TLOF);
137 virtual ~TargetLowering();
139 const TargetMachine &getTargetMachine() const { return TM; }
140 const DataLayout *getDataLayout() const { return TD; }
141 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
143 bool isBigEndian() const { return !IsLittleEndian; }
144 bool isLittleEndian() const { return IsLittleEndian; }
145 MVT getPointerTy() const { return PointerTy; }
146 virtual MVT getShiftAmountTy(EVT LHSTy) const;
148 /// isSelectExpensive - Return true if the select operation is expensive for
150 bool isSelectExpensive() const { return SelectIsExpensive; }
152 virtual bool isSelectSupported(SelectSupportKind kind) const { return true; }
154 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
155 /// a sequence of several shifts, adds, and multiplies for this target.
156 bool isIntDivCheap() const { return IntDivIsCheap; }
158 /// isSlowDivBypassed - Returns true if target has indicated at least one
159 /// type should be bypassed.
160 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
162 /// getBypassSlowDivTypes - Returns map of slow types for division or
163 /// remainder with corresponding fast types
164 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
165 return BypassSlowDivWidths;
168 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
170 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
172 /// isJumpExpensive() - Return true if Flow Control is an expensive operation
173 /// that should be avoided.
174 bool isJumpExpensive() const { return JumpIsExpensive; }
176 /// isPredictableSelectExpensive - Return true if selects are only cheaper
177 /// than branches if the branch is unlikely to be predicted right.
178 bool isPredictableSelectExpensive() const {
179 return predictableSelectIsExpensive;
182 /// getSetCCResultType - Return the ValueType of the result of SETCC
183 /// operations. Also used to obtain the target's preferred type for
184 /// the condition operand of SELECT and BRCOND nodes. In the case of
185 /// BRCOND the argument passed is MVT::Other since there are no other
186 /// operands to get a type hint from.
187 virtual EVT getSetCCResultType(EVT VT) const;
189 /// getCmpLibcallReturnType - Return the ValueType for comparison
190 /// libcalls. Comparions libcalls include floating point comparion calls,
191 /// and Ordered/Unordered check calls on floating point numbers.
193 MVT::SimpleValueType getCmpLibcallReturnType() const;
195 /// getBooleanContents - For targets without i1 registers, this gives the
196 /// nature of the high-bits of boolean values held in types wider than i1.
197 /// "Boolean values" are special true/false values produced by nodes like
198 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
199 /// Not to be confused with general values promoted from i1.
200 /// Some cpus distinguish between vectors of boolean and scalars; the isVec
201 /// parameter selects between the two kinds. For example on X86 a scalar
202 /// boolean should be zero extended from i1, while the elements of a vector
203 /// of booleans should be sign extended from i1.
204 BooleanContent getBooleanContents(bool isVec) const {
205 return isVec ? BooleanVectorContents : BooleanContents;
208 /// getSchedulingPreference - Return target scheduling preference.
209 Sched::Preference getSchedulingPreference() const {
210 return SchedPreferenceInfo;
213 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to
214 /// different scheduling heuristics for different nodes. This function returns
215 /// the preference (or none) for the given node.
216 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
220 /// getRegClassFor - Return the register class that should be used for the
221 /// specified value type.
222 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const {
223 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
224 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
225 assert(RC && "This value type is not natively supported!");
229 /// getRepRegClassFor - Return the 'representative' register class for the
230 /// specified value type. The 'representative' register class is the largest
231 /// legal super-reg register class for the register class of the value type.
232 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32;
233 /// while the rep register class is GR64 on x86_64.
234 virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const {
235 assert(VT.isSimple() && "getRepRegClassFor called on illegal type!");
236 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy];
240 /// getRepRegClassCostFor - Return the cost of the 'representative' register
241 /// class for the specified value type.
242 virtual uint8_t getRepRegClassCostFor(EVT VT) const {
243 assert(VT.isSimple() && "getRepRegClassCostFor called on illegal type!");
244 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy];
247 /// isTypeLegal - Return true if the target has native support for the
248 /// specified value type. This means that it has a register that directly
249 /// holds it without promotions or expansions.
250 bool isTypeLegal(EVT VT) const {
251 assert(!VT.isSimple() ||
252 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
253 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
256 class ValueTypeActionImpl {
257 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
258 /// that indicates how instruction selection should deal with the type.
259 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
262 ValueTypeActionImpl() {
263 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
266 LegalizeTypeAction getTypeAction(MVT VT) const {
267 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
270 void setTypeAction(EVT VT, LegalizeTypeAction Action) {
271 unsigned I = VT.getSimpleVT().SimpleTy;
272 ValueTypeActions[I] = Action;
276 const ValueTypeActionImpl &getValueTypeActions() const {
277 return ValueTypeActions;
280 /// getTypeAction - Return how we should legalize values of this type, either
281 /// it is already legal (return 'Legal') or we need to promote it to a larger
282 /// type (return 'Promote'), or we need to expand it into multiple registers
283 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
284 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
285 return getTypeConversion(Context, VT).first;
287 LegalizeTypeAction getTypeAction(MVT VT) const {
288 return ValueTypeActions.getTypeAction(VT);
291 /// getTypeToTransformTo - For types supported by the target, this is an
292 /// identity function. For types that must be promoted to larger types, this
293 /// returns the larger type to promote to. For integer types that are larger
294 /// than the largest integer register, this contains one step in the expansion
295 /// to get to the smaller register. For illegal floating point types, this
296 /// returns the integer type to transform to.
297 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
298 return getTypeConversion(Context, VT).second;
301 /// getTypeToExpandTo - For types supported by the target, this is an
302 /// identity function. For types that must be expanded (i.e. integer types
303 /// that are larger than the largest integer register or illegal floating
304 /// point types), this returns the largest legal type it will be expanded to.
305 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
306 assert(!VT.isVector());
308 switch (getTypeAction(Context, VT)) {
311 case TypeExpandInteger:
312 VT = getTypeToTransformTo(Context, VT);
315 llvm_unreachable("Type is not legal nor is it to be expanded!");
320 /// getVectorTypeBreakdown - Vector types are broken down into some number of
321 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
322 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
323 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
325 /// This method returns the number of registers needed, and the VT for each
326 /// register. It also returns the VT and quantity of the intermediate values
327 /// before they are promoted/expanded.
329 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
331 unsigned &NumIntermediates,
332 EVT &RegisterVT) const;
334 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
335 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
336 /// this is the case, it returns true and store the intrinsic
337 /// information into the IntrinsicInfo that was passed to the function.
338 struct IntrinsicInfo {
339 unsigned opc; // target opcode
340 EVT memVT; // memory VT
341 const Value* ptrVal; // value representing memory location
342 int offset; // offset off of ptrVal
343 unsigned align; // alignment
344 bool vol; // is volatile?
345 bool readMem; // reads memory?
346 bool writeMem; // writes memory?
349 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
350 unsigned /*Intrinsic*/) const {
354 /// isFPImmLegal - Returns true if the target can instruction select the
355 /// specified FP immediate natively. If false, the legalizer will materialize
356 /// the FP immediate as a load from a constant pool.
357 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
361 /// isShuffleMaskLegal - Targets can use this to indicate that they only
362 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
363 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
364 /// are assumed to be legal.
365 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
370 /// canOpTrap - Returns true if the operation can trap for the value type.
371 /// VT must be a legal type. By default, we optimistically assume most
372 /// operations don't trap except for divide and remainder.
373 virtual bool canOpTrap(unsigned Op, EVT VT) const;
375 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
376 /// used by Targets can use this to indicate if there is a suitable
377 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
379 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
384 /// getOperationAction - Return how this operation should be treated: either
385 /// it is legal, needs to be promoted to a larger size, needs to be
386 /// expanded to some other code sequence, or the target has a custom expander
388 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
389 if (VT.isExtended()) return Expand;
390 // If a target-specific SDNode requires legalization, require the target
391 // to provide custom legalization for it.
392 if (Op > array_lengthof(OpActions[0])) return Custom;
393 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
394 return (LegalizeAction)OpActions[I][Op];
397 /// isOperationLegalOrCustom - Return true if the specified operation is
398 /// legal on this target or can be made legal with custom lowering. This
399 /// is used to help guide high-level lowering decisions.
400 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
401 return (VT == MVT::Other || isTypeLegal(VT)) &&
402 (getOperationAction(Op, VT) == Legal ||
403 getOperationAction(Op, VT) == Custom);
406 /// isOperationLegal - Return true if the specified operation is legal on this
408 bool isOperationLegal(unsigned Op, EVT VT) const {
409 return (VT == MVT::Other || isTypeLegal(VT)) &&
410 getOperationAction(Op, VT) == Legal;
413 /// getLoadExtAction - Return how this load with extension should be treated:
414 /// either it is legal, needs to be promoted to a larger size, needs to be
415 /// expanded to some other code sequence, or the target has a custom expander
417 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const {
418 assert(ExtType < ISD::LAST_LOADEXT_TYPE &&
419 VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
420 "Table isn't big enough!");
421 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType];
424 /// isLoadExtLegal - Return true if the specified load with extension is legal
426 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
427 return VT.isSimple() && getLoadExtAction(ExtType, VT) == Legal;
430 /// getTruncStoreAction - Return how this store with truncation should be
431 /// treated: either it is legal, needs to be promoted to a larger size, needs
432 /// to be expanded to some other code sequence, or the target has a custom
434 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
435 assert(ValVT.getSimpleVT() < MVT::LAST_VALUETYPE &&
436 MemVT.getSimpleVT() < MVT::LAST_VALUETYPE &&
437 "Table isn't big enough!");
438 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy]
439 [MemVT.getSimpleVT().SimpleTy];
442 /// isTruncStoreLegal - Return true if the specified store with truncation is
443 /// legal on this target.
444 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
445 return isTypeLegal(ValVT) && MemVT.isSimple() &&
446 getTruncStoreAction(ValVT, MemVT) == Legal;
449 /// getIndexedLoadAction - Return how the indexed load should be treated:
450 /// either it is legal, needs to be promoted to a larger size, needs to be
451 /// expanded to some other code sequence, or the target has a custom expander
454 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
455 assert(IdxMode < ISD::LAST_INDEXED_MODE &&
456 VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
457 "Table isn't big enough!");
458 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
459 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
462 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
464 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
465 return VT.isSimple() &&
466 (getIndexedLoadAction(IdxMode, VT) == Legal ||
467 getIndexedLoadAction(IdxMode, VT) == Custom);
470 /// getIndexedStoreAction - Return how the indexed store should be treated:
471 /// either it is legal, needs to be promoted to a larger size, needs to be
472 /// expanded to some other code sequence, or the target has a custom expander
475 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
476 assert(IdxMode < ISD::LAST_INDEXED_MODE &&
477 VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
478 "Table isn't big enough!");
479 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
480 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
483 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
485 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
486 return VT.isSimple() &&
487 (getIndexedStoreAction(IdxMode, VT) == Legal ||
488 getIndexedStoreAction(IdxMode, VT) == Custom);
491 /// getCondCodeAction - Return how the condition code should be treated:
492 /// either it is legal, needs to be expanded to some other code sequence,
493 /// or the target has a custom expander for it.
495 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
496 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
497 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
498 "Table isn't big enough!");
499 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit
500 /// value and the upper 27 bits index into the second dimension of the
501 /// array to select what 64bit value to use.
502 LegalizeAction Action = (LegalizeAction)
503 ((CondCodeActions[CC][VT.getSimpleVT().SimpleTy >> 5]
504 >> (2*(VT.getSimpleVT().SimpleTy & 0x1F))) & 3);
505 assert(Action != Promote && "Can't promote condition code!");
509 /// isCondCodeLegal - Return true if the specified condition code is legal
511 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
512 return getCondCodeAction(CC, VT) == Legal ||
513 getCondCodeAction(CC, VT) == Custom;
517 /// getTypeToPromoteTo - If the action for this operation is to promote, this
518 /// method returns the ValueType to promote to.
519 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
520 assert(getOperationAction(Op, VT) == Promote &&
521 "This operation isn't promoted!");
523 // See if this has an explicit type specified.
524 std::map<std::pair<unsigned, MVT::SimpleValueType>,
525 MVT::SimpleValueType>::const_iterator PTTI =
526 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
527 if (PTTI != PromoteToType.end()) return PTTI->second;
529 assert((VT.isInteger() || VT.isFloatingPoint()) &&
530 "Cannot autopromote this type, add it with AddPromotedToType.");
534 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
535 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
536 "Didn't find type to promote to!");
537 } while (!isTypeLegal(NVT) ||
538 getOperationAction(Op, NVT) == Promote);
542 /// getValueType - Return the EVT corresponding to this LLVM type.
543 /// This is fixed by the LLVM operations except for the pointer size. If
544 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
545 /// counterpart (e.g. structs), otherwise it will assert.
546 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
547 // Lower scalar pointers to native pointer types.
548 if (Ty->isPointerTy()) return PointerTy;
550 if (Ty->isVectorTy()) {
551 VectorType *VTy = cast<VectorType>(Ty);
552 Type *Elm = VTy->getElementType();
553 // Lower vectors of pointers to native pointer types.
554 if (Elm->isPointerTy())
555 Elm = EVT(PointerTy).getTypeForEVT(Ty->getContext());
556 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
557 VTy->getNumElements());
559 return EVT::getEVT(Ty, AllowUnknown);
563 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
564 /// function arguments in the caller parameter area. This is the actual
565 /// alignment, not its logarithm.
566 virtual unsigned getByValTypeAlignment(Type *Ty) const;
568 /// getRegisterType - Return the type of registers that this ValueType will
569 /// eventually require.
570 EVT getRegisterType(MVT VT) const {
571 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
572 return RegisterTypeForVT[VT.SimpleTy];
575 /// getRegisterType - Return the type of registers that this ValueType will
576 /// eventually require.
577 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
579 assert((unsigned)VT.getSimpleVT().SimpleTy <
580 array_lengthof(RegisterTypeForVT));
581 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
585 unsigned NumIntermediates;
586 (void)getVectorTypeBreakdown(Context, VT, VT1,
587 NumIntermediates, RegisterVT);
590 if (VT.isInteger()) {
591 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
593 llvm_unreachable("Unsupported extended type!");
596 /// getNumRegisters - Return the number of registers that this ValueType will
597 /// eventually require. This is one for any types promoted to live in larger
598 /// registers, but may be more than one for types (like i64) that are split
599 /// into pieces. For types like i140, which are first promoted then expanded,
600 /// it is the number of registers needed to hold all the bits of the original
601 /// type. For an i140 on a 32 bit machine this means 5 registers.
602 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
604 assert((unsigned)VT.getSimpleVT().SimpleTy <
605 array_lengthof(NumRegistersForVT));
606 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
610 unsigned NumIntermediates;
611 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
613 if (VT.isInteger()) {
614 unsigned BitWidth = VT.getSizeInBits();
615 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
616 return (BitWidth + RegWidth - 1) / RegWidth;
618 llvm_unreachable("Unsupported extended type!");
621 /// ShouldShrinkFPConstant - If true, then instruction selection should
622 /// seek to shrink the FP constant of the specified type to a smaller type
623 /// in order to save space and / or reduce runtime.
624 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
626 /// hasTargetDAGCombine - If true, the target has custom DAG combine
627 /// transformations that it can perform for the specified node.
628 bool hasTargetDAGCombine(ISD::NodeType NT) const {
629 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
630 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
633 /// This function returns the maximum number of store operations permitted
634 /// to replace a call to llvm.memset. The value is set by the target at the
635 /// performance threshold for such a replacement. If OptSize is true,
636 /// return the limit for functions that have OptSize attribute.
637 /// @brief Get maximum # of store operations permitted for llvm.memset
638 unsigned getMaxStoresPerMemset(bool OptSize) const {
639 return OptSize ? maxStoresPerMemsetOptSize : maxStoresPerMemset;
642 /// This function returns the maximum number of store operations permitted
643 /// to replace a call to llvm.memcpy. The value is set by the target at the
644 /// performance threshold for such a replacement. If OptSize is true,
645 /// return the limit for functions that have OptSize attribute.
646 /// @brief Get maximum # of store operations permitted for llvm.memcpy
647 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
648 return OptSize ? maxStoresPerMemcpyOptSize : maxStoresPerMemcpy;
651 /// This function returns the maximum number of store operations permitted
652 /// to replace a call to llvm.memmove. The value is set by the target at the
653 /// performance threshold for such a replacement. If OptSize is true,
654 /// return the limit for functions that have OptSize attribute.
655 /// @brief Get maximum # of store operations permitted for llvm.memmove
656 unsigned getMaxStoresPerMemmove(bool OptSize) const {
657 return OptSize ? maxStoresPerMemmoveOptSize : maxStoresPerMemmove;
660 /// This function returns true if the target allows unaligned memory accesses.
661 /// of the specified type. This is used, for example, in situations where an
662 /// array copy/move/set is converted to a sequence of store operations. It's
663 /// use helps to ensure that such replacements don't generate code that causes
664 /// an alignment error (trap) on the target machine.
665 /// @brief Determine if the target supports unaligned memory accesses.
666 virtual bool allowsUnalignedMemoryAccesses(EVT) const {
670 /// This function returns true if the target would benefit from code placement
672 /// @brief Determine if the target should perform code placement optimization.
673 bool shouldOptimizeCodePlacement() const {
674 return benefitFromCodePlacementOpt;
677 /// getOptimalMemOpType - Returns the target specific optimal type for load
678 /// and store operations as a result of memset, memcpy, and memmove
679 /// lowering. If DstAlign is zero that means it's safe to destination
680 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
681 /// means there isn't a need to check it against alignment requirement,
682 /// probably because the source does not need to be loaded. If
683 /// 'IsZeroVal' is true, that means it's safe to return a
684 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
685 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
686 /// constant so it does not need to be loaded.
687 /// It returns EVT::Other if the type should be determined using generic
688 /// target-independent logic.
689 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
690 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
692 bool /*MemcpyStrSrc*/,
693 MachineFunction &/*MF*/) const {
697 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
698 /// to implement llvm.setjmp.
699 bool usesUnderscoreSetJmp() const {
700 return UseUnderscoreSetJmp;
703 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
704 /// to implement llvm.longjmp.
705 bool usesUnderscoreLongJmp() const {
706 return UseUnderscoreLongJmp;
709 /// supportJumpTables - return whether the target can generate code for
711 bool supportJumpTables() const {
712 return SupportJumpTables;
715 /// getMinimumJumpTableEntries - return integer threshold on number of
716 /// blocks to use jump tables rather than if sequence.
717 int getMinimumJumpTableEntries() const {
718 return MinimumJumpTableEntries;
721 /// getStackPointerRegisterToSaveRestore - If a physical register, this
722 /// specifies the register that llvm.savestack/llvm.restorestack should save
724 unsigned getStackPointerRegisterToSaveRestore() const {
725 return StackPointerRegisterToSaveRestore;
728 /// getExceptionPointerRegister - If a physical register, this returns
729 /// the register that receives the exception address on entry to a landing
731 unsigned getExceptionPointerRegister() const {
732 return ExceptionPointerRegister;
735 /// getExceptionSelectorRegister - If a physical register, this returns
736 /// the register that receives the exception typeid on entry to a landing
738 unsigned getExceptionSelectorRegister() const {
739 return ExceptionSelectorRegister;
742 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
743 /// set, the default is 200)
744 unsigned getJumpBufSize() const {
748 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
749 /// (if never set, the default is 0)
750 unsigned getJumpBufAlignment() const {
751 return JumpBufAlignment;
754 /// getMinStackArgumentAlignment - return the minimum stack alignment of an
756 unsigned getMinStackArgumentAlignment() const {
757 return MinStackArgumentAlignment;
760 /// getMinFunctionAlignment - return the minimum function alignment.
762 unsigned getMinFunctionAlignment() const {
763 return MinFunctionAlignment;
766 /// getPrefFunctionAlignment - return the preferred function alignment.
768 unsigned getPrefFunctionAlignment() const {
769 return PrefFunctionAlignment;
772 /// getPrefLoopAlignment - return the preferred loop alignment.
774 unsigned getPrefLoopAlignment() const {
775 return PrefLoopAlignment;
778 /// getShouldFoldAtomicFences - return whether the combiner should fold
779 /// fence MEMBARRIER instructions into the atomic intrinsic instructions.
781 bool getShouldFoldAtomicFences() const {
782 return ShouldFoldAtomicFences;
785 /// getInsertFencesFor - return whether the DAG builder should automatically
786 /// insert fences and reduce ordering for atomics.
788 bool getInsertFencesForAtomic() const {
789 return InsertFencesForAtomic;
792 /// getPreIndexedAddressParts - returns true by value, base pointer and
793 /// offset pointer and addressing mode by reference if the node's address
794 /// can be legally represented as pre-indexed load / store address.
795 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
797 ISD::MemIndexedMode &/*AM*/,
798 SelectionDAG &/*DAG*/) const {
802 /// getPostIndexedAddressParts - returns true by value, base pointer and
803 /// offset pointer and addressing mode by reference if this node can be
804 /// combined with a load / store to form a post-indexed load / store.
805 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
806 SDValue &/*Base*/, SDValue &/*Offset*/,
807 ISD::MemIndexedMode &/*AM*/,
808 SelectionDAG &/*DAG*/) const {
812 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
813 /// current function. The returned value is a member of the
814 /// MachineJumpTableInfo::JTEntryKind enum.
815 virtual unsigned getJumpTableEncoding() const;
817 virtual const MCExpr *
818 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
819 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
820 MCContext &/*Ctx*/) const {
821 llvm_unreachable("Need to implement this hook if target has custom JTIs");
824 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
826 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
827 SelectionDAG &DAG) const;
829 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
830 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
832 virtual const MCExpr *
833 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
834 unsigned JTI, MCContext &Ctx) const;
836 /// isOffsetFoldingLegal - Return true if folding a constant offset
837 /// with the given GlobalAddress is legal. It is frequently not legal in
838 /// PIC relocation models.
839 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
841 /// getStackCookieLocation - Return true if the target stores stack
842 /// protector cookies at a fixed offset in some non-standard address
843 /// space, and populates the address space and offset as
845 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
846 unsigned &/*Offset*/) const {
850 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be
851 /// used for loads / stores from the global.
852 virtual unsigned getMaximalGlobalOffset() const {
856 //===--------------------------------------------------------------------===//
857 // TargetLowering Optimization Methods
860 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
861 /// SDValues for returning information from TargetLowering to its clients
862 /// that want to combine
863 struct TargetLoweringOpt {
870 explicit TargetLoweringOpt(SelectionDAG &InDAG,
872 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
874 bool LegalTypes() const { return LegalTys; }
875 bool LegalOperations() const { return LegalOps; }
877 bool CombineTo(SDValue O, SDValue N) {
883 /// ShrinkDemandedConstant - Check to see if the specified operand of the
884 /// specified instruction is a constant integer. If so, check to see if
885 /// there are any bits set in the constant that are not demanded. If so,
886 /// shrink the constant and return true.
887 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
889 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
890 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
891 /// cast, but it could be generalized for targets with other types of
892 /// implicit widening casts.
893 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
897 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
898 /// DemandedMask bits of the result of Op are ever used downstream. If we can
899 /// use this information to simplify Op, create a new simplified DAG node and
900 /// return true, returning the original and new nodes in Old and New.
901 /// Otherwise, analyze the expression and return a mask of KnownOne and
902 /// KnownZero bits for the expression (used to simplify the caller).
903 /// The KnownZero/One bits may only be accurate for those bits in the
905 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
906 APInt &KnownZero, APInt &KnownOne,
907 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
909 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
910 /// Mask are known to be either zero or one and return them in the
911 /// KnownZero/KnownOne bitsets.
912 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
915 const SelectionDAG &DAG,
916 unsigned Depth = 0) const;
918 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
919 /// targets that want to expose additional information about sign bits to the
921 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
922 unsigned Depth = 0) const;
924 struct DAGCombinerInfo {
925 void *DC; // The DAG Combiner object.
927 bool BeforeLegalizeOps;
928 bool CalledByLegalizer;
932 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
933 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
934 CalledByLegalizer(cl), DAG(dag) {}
936 bool isBeforeLegalize() const { return BeforeLegalize; }
937 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
938 bool isCalledByLegalizer() const { return CalledByLegalizer; }
940 void AddToWorklist(SDNode *N);
941 void RemoveFromWorklist(SDNode *N);
942 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
944 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
945 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
947 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
950 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
951 /// and cc. If it is unable to simplify it, return a null SDValue.
952 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
953 ISD::CondCode Cond, bool foldBooleans,
954 DAGCombinerInfo &DCI, DebugLoc dl) const;
956 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
957 /// node is a GlobalAddress + offset.
959 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
961 /// PerformDAGCombine - This method will be invoked for all target nodes and
962 /// for any target-independent nodes that the target has registered with
965 /// The semantics are as follows:
967 /// SDValue.Val == 0 - No change was made
968 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
969 /// otherwise - N should be replaced by the returned Operand.
971 /// In addition, methods provided by DAGCombinerInfo may be used to perform
972 /// more complex transformations.
974 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
976 /// isTypeDesirableForOp - Return true if the target has native support for
977 /// the specified value type and it is 'desirable' to use the type for the
978 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
979 /// instruction encodings are longer and some i16 instructions are slow.
980 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
981 // By default, assume all legal types are desirable.
982 return isTypeLegal(VT);
985 /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner
986 /// to transform a floating point op of specified opcode to a equivalent op of
987 /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM.
988 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
993 /// IsDesirableToPromoteOp - This method query the target whether it is
994 /// beneficial for dag combiner to promote the specified node. If true, it
995 /// should return the desired promotion type by reference.
996 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
1000 //===--------------------------------------------------------------------===//
1001 // TargetLowering Configuration Methods - These methods should be invoked by
1002 // the derived class constructor to configure this object for the target.
1006 /// setBooleanContents - Specify how the target extends the result of a
1007 /// boolean value from i1 to a wider type. See getBooleanContents.
1008 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
1009 /// setBooleanVectorContents - Specify how the target extends the result
1010 /// of a vector boolean value from a vector of i1 to a wider type. See
1011 /// getBooleanContents.
1012 void setBooleanVectorContents(BooleanContent Ty) {
1013 BooleanVectorContents = Ty;
1016 /// setSchedulingPreference - Specify the target scheduling preference.
1017 void setSchedulingPreference(Sched::Preference Pref) {
1018 SchedPreferenceInfo = Pref;
1021 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
1022 /// use _setjmp to implement llvm.setjmp or the non _ version.
1023 /// Defaults to false.
1024 void setUseUnderscoreSetJmp(bool Val) {
1025 UseUnderscoreSetJmp = Val;
1028 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
1029 /// use _longjmp to implement llvm.longjmp or the non _ version.
1030 /// Defaults to false.
1031 void setUseUnderscoreLongJmp(bool Val) {
1032 UseUnderscoreLongJmp = Val;
1035 /// setSupportJumpTables - Indicate whether the target can generate code for
1037 void setSupportJumpTables(bool Val) {
1038 SupportJumpTables = Val;
1041 /// setMinimumJumpTableEntries - Indicate the number of blocks to generate
1042 /// jump tables rather than if sequence.
1043 void setMinimumJumpTableEntries(int Val) {
1044 MinimumJumpTableEntries = Val;
1047 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
1048 /// specifies the register that llvm.savestack/llvm.restorestack should save
1050 void setStackPointerRegisterToSaveRestore(unsigned R) {
1051 StackPointerRegisterToSaveRestore = R;
1054 /// setExceptionPointerRegister - If set to a physical register, this sets
1055 /// the register that receives the exception address on entry to a landing
1057 void setExceptionPointerRegister(unsigned R) {
1058 ExceptionPointerRegister = R;
1061 /// setExceptionSelectorRegister - If set to a physical register, this sets
1062 /// the register that receives the exception typeid on entry to a landing
1064 void setExceptionSelectorRegister(unsigned R) {
1065 ExceptionSelectorRegister = R;
1068 /// SelectIsExpensive - Tells the code generator not to expand operations
1069 /// into sequences that use the select operations if possible.
1070 void setSelectIsExpensive(bool isExpensive = true) {
1071 SelectIsExpensive = isExpensive;
1074 /// JumpIsExpensive - Tells the code generator not to expand sequence of
1075 /// operations into a separate sequences that increases the amount of
1077 void setJumpIsExpensive(bool isExpensive = true) {
1078 JumpIsExpensive = isExpensive;
1081 /// setIntDivIsCheap - Tells the code generator that integer divide is
1082 /// expensive, and if possible, should be replaced by an alternate sequence
1083 /// of instructions not containing an integer divide.
1084 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1086 /// addBypassSlowDiv - Tells the code generator which bitwidths to bypass.
1087 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1088 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1091 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
1092 /// srl/add/sra for a signed divide by power of two, and let the target handle
1094 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
1096 /// addRegisterClass - Add the specified register class as an available
1097 /// regclass for the specified value type. This indicates the selector can
1098 /// handle values of that class natively.
1099 void addRegisterClass(EVT VT, const TargetRegisterClass *RC) {
1100 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
1101 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1102 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
1105 /// findRepresentativeClass - Return the largest legal super-reg register class
1106 /// of the register class for the specified type and its associated "cost".
1107 virtual std::pair<const TargetRegisterClass*, uint8_t>
1108 findRepresentativeClass(EVT VT) const;
1110 /// computeRegisterProperties - Once all of the register classes are added,
1111 /// this allows us to compute derived properties we expose.
1112 void computeRegisterProperties();
1114 /// setOperationAction - Indicate that the specified operation does not work
1115 /// with the specified type and indicate what to do about it.
1116 void setOperationAction(unsigned Op, MVT VT,
1117 LegalizeAction Action) {
1118 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1119 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1122 /// setLoadExtAction - Indicate that the specified load with extension does
1123 /// not work with the specified type and indicate what to do about it.
1124 void setLoadExtAction(unsigned ExtType, MVT VT,
1125 LegalizeAction Action) {
1126 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
1127 "Table isn't big enough!");
1128 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1131 /// setTruncStoreAction - Indicate that the specified truncating store does
1132 /// not work with the specified type and indicate what to do about it.
1133 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1134 LegalizeAction Action) {
1135 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1136 "Table isn't big enough!");
1137 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1140 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1141 /// does not work with the specified type and indicate what to do abort
1142 /// it. NOTE: All indexed mode loads are initialized to Expand in
1143 /// TargetLowering.cpp
1144 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1145 LegalizeAction Action) {
1146 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1147 (unsigned)Action < 0xf && "Table isn't big enough!");
1148 // Load action are kept in the upper half.
1149 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1150 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1153 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1154 /// does not work with the specified type and indicate what to do about
1155 /// it. NOTE: All indexed mode stores are initialized to Expand in
1156 /// TargetLowering.cpp
1157 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1158 LegalizeAction Action) {
1159 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1160 (unsigned)Action < 0xf && "Table isn't big enough!");
1161 // Store action are kept in the lower half.
1162 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1163 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1166 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1167 /// supported on the target and indicate what to do about it.
1168 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1169 LegalizeAction Action) {
1170 assert(VT < MVT::LAST_VALUETYPE &&
1171 (unsigned)CC < array_lengthof(CondCodeActions) &&
1172 "Table isn't big enough!");
1173 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit
1174 /// value and the upper 27 bits index into the second dimension of the
1175 /// array to select what 64bit value to use.
1176 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5]
1177 &= ~(uint64_t(3UL) << (VT.SimpleTy & 0x1F)*2);
1178 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5]
1179 |= (uint64_t)Action << (VT.SimpleTy & 0x1F)*2;
1182 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1183 /// promotion code defaults to trying a larger integer/fp until it can find
1184 /// one that works. If that default is insufficient, this method can be used
1185 /// by the target to override the default.
1186 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1187 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1190 /// setTargetDAGCombine - Targets should invoke this method for each target
1191 /// independent node that they want to provide a custom DAG combiner for by
1192 /// implementing the PerformDAGCombine virtual method.
1193 void setTargetDAGCombine(ISD::NodeType NT) {
1194 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1195 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1198 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1199 /// bytes); default is 200
1200 void setJumpBufSize(unsigned Size) {
1204 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1205 /// alignment (in bytes); default is 0
1206 void setJumpBufAlignment(unsigned Align) {
1207 JumpBufAlignment = Align;
1210 /// setMinFunctionAlignment - Set the target's minimum function alignment (in
1212 void setMinFunctionAlignment(unsigned Align) {
1213 MinFunctionAlignment = Align;
1216 /// setPrefFunctionAlignment - Set the target's preferred function alignment.
1217 /// This should be set if there is a performance benefit to
1218 /// higher-than-minimum alignment (in log2(bytes))
1219 void setPrefFunctionAlignment(unsigned Align) {
1220 PrefFunctionAlignment = Align;
1223 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1224 /// alignment is zero, it means the target does not care about loop alignment.
1225 /// The alignment is specified in log2(bytes).
1226 void setPrefLoopAlignment(unsigned Align) {
1227 PrefLoopAlignment = Align;
1230 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an
1231 /// argument (in log2(bytes)).
1232 void setMinStackArgumentAlignment(unsigned Align) {
1233 MinStackArgumentAlignment = Align;
1236 /// setShouldFoldAtomicFences - Set if the target's implementation of the
1237 /// atomic operation intrinsics includes locking. Default is false.
1238 void setShouldFoldAtomicFences(bool fold) {
1239 ShouldFoldAtomicFences = fold;
1242 /// setInsertFencesForAtomic - Set if the DAG builder should
1243 /// automatically insert fences and reduce the order of atomic memory
1244 /// operations to Monotonic.
1245 void setInsertFencesForAtomic(bool fence) {
1246 InsertFencesForAtomic = fence;
1250 //===--------------------------------------------------------------------===//
1251 // Lowering methods - These methods must be implemented by targets so that
1252 // the SelectionDAGLowering code knows how to lower these.
1255 /// LowerFormalArguments - This hook must be implemented to lower the
1256 /// incoming (formal) arguments, described by the Ins array, into the
1257 /// specified DAG. The implementation should fill in the InVals array
1258 /// with legal-type argument values, and return the resulting token
1262 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
1264 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
1265 DebugLoc /*dl*/, SelectionDAG &/*DAG*/,
1266 SmallVectorImpl<SDValue> &/*InVals*/) const {
1267 llvm_unreachable("Not Implemented");
1270 struct ArgListEntry {
1281 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1282 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1284 typedef std::vector<ArgListEntry> ArgListTy;
1286 /// CallLoweringInfo - This structure contains all information that is
1287 /// necessary for lowering calls. It is passed to TLI::LowerCallTo when the
1288 /// SelectionDAG builder needs to lower a call, and targets will see this
1289 /// struct in their LowerCall implementation.
1290 struct CallLoweringInfo {
1297 bool DoesNotReturn : 1;
1298 bool IsReturnValueUsed : 1;
1300 // IsTailCall should be modified by implementations of
1301 // TargetLowering::LowerCall that perform tail call conversions.
1304 unsigned NumFixedArgs;
1305 CallingConv::ID CallConv;
1310 ImmutableCallSite *CS;
1311 SmallVector<ISD::OutputArg, 32> Outs;
1312 SmallVector<SDValue, 32> OutVals;
1313 SmallVector<ISD::InputArg, 32> Ins;
1316 /// CallLoweringInfo - Constructs a call lowering context based on the
1317 /// ImmutableCallSite \p cs.
1318 CallLoweringInfo(SDValue chain, Type *retTy,
1319 FunctionType *FTy, bool isTailCall, SDValue callee,
1320 ArgListTy &args, SelectionDAG &dag, DebugLoc dl,
1321 ImmutableCallSite &cs)
1322 : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasSExtAttr(0)),
1323 RetZExt(cs.paramHasZExtAttr(0)), IsVarArg(FTy->isVarArg()),
1324 IsInReg(cs.paramHasInRegAttr(0)),
1325 DoesNotReturn(cs.doesNotReturn()),
1326 IsReturnValueUsed(!cs.getInstruction()->use_empty()),
1327 IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()),
1328 CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag),
1331 /// CallLoweringInfo - Constructs a call lowering context based on the
1332 /// provided call information.
1333 CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt,
1334 bool isVarArg, bool isInReg, unsigned numFixedArgs,
1335 CallingConv::ID callConv, bool isTailCall,
1336 bool doesNotReturn, bool isReturnValueUsed, SDValue callee,
1337 ArgListTy &args, SelectionDAG &dag, DebugLoc dl)
1338 : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt),
1339 IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn),
1340 IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall),
1341 NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee),
1342 Args(args), DAG(dag), DL(dl), CS(NULL) {}
1345 /// LowerCallTo - This function lowers an abstract call to a function into an
1346 /// actual call. This returns a pair of operands. The first element is the
1347 /// return value for the function (if RetTy is not VoidTy). The second
1348 /// element is the outgoing token chain. It calls LowerCall to do the actual
1350 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
1352 /// LowerCall - This hook must be implemented to lower calls into the
1353 /// the specified DAG. The outgoing arguments to the call are described
1354 /// by the Outs array, and the values to be returned by the call are
1355 /// described by the Ins array. The implementation should fill in the
1356 /// InVals array with legal-type return values from the call, and return
1357 /// the resulting token chain value.
1359 LowerCall(CallLoweringInfo &/*CLI*/,
1360 SmallVectorImpl<SDValue> &/*InVals*/) const {
1361 llvm_unreachable("Not Implemented");
1364 /// HandleByVal - Target-specific cleanup for formal ByVal parameters.
1365 virtual void HandleByVal(CCState *, unsigned &) const {}
1367 /// CanLowerReturn - This hook should be implemented to check whether the
1368 /// return values described by the Outs array can fit into the return
1369 /// registers. If false is returned, an sret-demotion is performed.
1371 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
1372 MachineFunction &/*MF*/, bool /*isVarArg*/,
1373 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
1374 LLVMContext &/*Context*/) const
1376 // Return true by default to get preexisting behavior.
1380 /// LowerReturn - This hook must be implemented to lower outgoing
1381 /// return values, described by the Outs array, into the specified
1382 /// DAG. The implementation should return the resulting token chain
1386 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
1388 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
1389 const SmallVectorImpl<SDValue> &/*OutVals*/,
1390 DebugLoc /*dl*/, SelectionDAG &/*DAG*/) const {
1391 llvm_unreachable("Not Implemented");
1394 /// isUsedByReturnOnly - Return true if result of the specified node is used
1395 /// by a return node only. It also compute and return the input chain for the
1397 /// This is used to determine whether it is possible
1398 /// to codegen a libcall as tail call at legalization time.
1399 virtual bool isUsedByReturnOnly(SDNode *, SDValue &Chain) const {
1403 /// mayBeEmittedAsTailCall - Return true if the target may be able emit the
1404 /// call instruction as a tail call. This is used by optimization passes to
1405 /// determine if it's profitable to duplicate return instructions to enable
1406 /// tailcall optimization.
1407 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
1411 /// getTypeForExtArgOrReturn - Return the type that should be used to zero or
1412 /// sign extend a zeroext/signext integer argument or return value.
1413 /// FIXME: Most C calling convention requires the return type to be promoted,
1414 /// but this is not true all the time, e.g. i1 on x86-64. It is also not
1415 /// necessary for non-C calling conventions. The frontend should handle this
1416 /// and include all of the necessary information.
1417 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1418 ISD::NodeType /*ExtendKind*/) const {
1419 EVT MinVT = getRegisterType(Context, MVT::i32);
1420 return VT.bitsLT(MinVT) ? MinVT : VT;
1423 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1424 /// to legalize nodes with an illegal operand type but legal result types.
1425 /// It replaces the LowerOperation callback in the type Legalizer.
1426 /// The reason we can not do away with LowerOperation entirely is that
1427 /// LegalizeDAG isn't yet ready to use this callback.
1428 /// TODO: Consider merging with ReplaceNodeResults.
1430 /// The target places new result values for the node in Results (their number
1431 /// and types must exactly match those of the original return values of
1432 /// the node), or leaves Results empty, which indicates that the node is not
1433 /// to be custom lowered after all.
1434 /// The default implementation calls LowerOperation.
1435 virtual void LowerOperationWrapper(SDNode *N,
1436 SmallVectorImpl<SDValue> &Results,
1437 SelectionDAG &DAG) const;
1439 /// LowerOperation - This callback is invoked for operations that are
1440 /// unsupported by the target, which are registered to use 'custom' lowering,
1441 /// and whose defined values are all legal.
1442 /// If the target has no operations that require custom lowering, it need not
1443 /// implement this. The default implementation of this aborts.
1444 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
1446 /// ReplaceNodeResults - This callback is invoked when a node result type is
1447 /// illegal for the target, and the operation was registered to use 'custom'
1448 /// lowering for that result type. The target places new result values for
1449 /// the node in Results (their number and types must exactly match those of
1450 /// the original return values of the node), or leaves Results empty, which
1451 /// indicates that the node is not to be custom lowered after all.
1453 /// If the target has no operations that require custom lowering, it need not
1454 /// implement this. The default implementation aborts.
1455 virtual void ReplaceNodeResults(SDNode * /*N*/,
1456 SmallVectorImpl<SDValue> &/*Results*/,
1457 SelectionDAG &/*DAG*/) const {
1458 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
1461 /// getTargetNodeName() - This method returns the name of a target specific
1463 virtual const char *getTargetNodeName(unsigned Opcode) const;
1465 /// createFastISel - This method returns a target specific FastISel object,
1466 /// or null if the target does not support "fast" ISel.
1467 virtual FastISel *createFastISel(FunctionLoweringInfo &,
1468 const TargetLibraryInfo *) const {
1472 //===--------------------------------------------------------------------===//
1473 // Inline Asm Support hooks
1476 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1477 /// call to be explicit llvm code if it wants to. This is useful for
1478 /// turning simple inline asms into LLVM intrinsics, which gives the
1479 /// compiler more information about the behavior of the code.
1480 virtual bool ExpandInlineAsm(CallInst *) const {
1484 enum ConstraintType {
1485 C_Register, // Constraint represents specific register(s).
1486 C_RegisterClass, // Constraint represents any of register(s) in class.
1487 C_Memory, // Memory constraint.
1488 C_Other, // Something else.
1489 C_Unknown // Unsupported constraint.
1492 enum ConstraintWeight {
1494 CW_Invalid = -1, // No match.
1495 CW_Okay = 0, // Acceptable.
1496 CW_Good = 1, // Good weight.
1497 CW_Better = 2, // Better weight.
1498 CW_Best = 3, // Best weight.
1500 // Well-known weights.
1501 CW_SpecificReg = CW_Okay, // Specific register operands.
1502 CW_Register = CW_Good, // Register operands.
1503 CW_Memory = CW_Better, // Memory operands.
1504 CW_Constant = CW_Best, // Constant operand.
1505 CW_Default = CW_Okay // Default or don't know type.
1508 /// AsmOperandInfo - This contains information for each constraint that we are
1510 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1511 /// ConstraintCode - This contains the actual string for the code, like "m".
1512 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1513 /// most closely matches the operand.
1514 std::string ConstraintCode;
1516 /// ConstraintType - Information about the constraint code, e.g. Register,
1517 /// RegisterClass, Memory, Other, Unknown.
1518 TargetLowering::ConstraintType ConstraintType;
1520 /// CallOperandval - If this is the result output operand or a
1521 /// clobber, this is null, otherwise it is the incoming operand to the
1522 /// CallInst. This gets modified as the asm is processed.
1523 Value *CallOperandVal;
1525 /// ConstraintVT - The ValueType for the operand value.
1528 /// isMatchingInputConstraint - Return true of this is an input operand that
1529 /// is a matching constraint like "4".
1530 bool isMatchingInputConstraint() const;
1532 /// getMatchedOperand - If this is an input matching constraint, this method
1533 /// returns the output operand it matches.
1534 unsigned getMatchedOperand() const;
1536 /// Copy constructor for copying from an AsmOperandInfo.
1537 AsmOperandInfo(const AsmOperandInfo &info)
1538 : InlineAsm::ConstraintInfo(info),
1539 ConstraintCode(info.ConstraintCode),
1540 ConstraintType(info.ConstraintType),
1541 CallOperandVal(info.CallOperandVal),
1542 ConstraintVT(info.ConstraintVT) {
1545 /// Copy constructor for copying from a ConstraintInfo.
1546 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1547 : InlineAsm::ConstraintInfo(info),
1548 ConstraintType(TargetLowering::C_Unknown),
1549 CallOperandVal(0), ConstraintVT(MVT::Other) {
1553 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
1555 /// ParseConstraints - Split up the constraint string from the inline
1556 /// assembly value into the specific constraints and their prefixes,
1557 /// and also tie in the associated operand values.
1558 /// If this returns an empty vector, and if the constraint string itself
1559 /// isn't empty, there was an error parsing.
1560 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
1562 /// Examine constraint type and operand type and determine a weight value.
1563 /// The operand object must already have been set up with the operand type.
1564 virtual ConstraintWeight getMultipleConstraintMatchWeight(
1565 AsmOperandInfo &info, int maIndex) const;
1567 /// Examine constraint string and operand type and determine a weight value.
1568 /// The operand object must already have been set up with the operand type.
1569 virtual ConstraintWeight getSingleConstraintMatchWeight(
1570 AsmOperandInfo &info, const char *constraint) const;
1572 /// ComputeConstraintToUse - Determines the constraint code and constraint
1573 /// type to use for the specific AsmOperandInfo, setting
1574 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1575 /// being passed in is available, it can be passed in as Op, otherwise an
1576 /// empty SDValue can be passed.
1577 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1579 SelectionDAG *DAG = 0) const;
1581 /// getConstraintType - Given a constraint, return the type of constraint it
1582 /// is for this target.
1583 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1585 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1586 /// {edx}), return the register number and the register class for the
1589 /// Given a register class constraint, like 'r', if this corresponds directly
1590 /// to an LLVM register class, return a register of 0 and the register class
1593 /// This should only be used for C_Register constraints. On error,
1594 /// this returns a register number of 0 and a null register class pointer..
1595 virtual std::pair<unsigned, const TargetRegisterClass*>
1596 getRegForInlineAsmConstraint(const std::string &Constraint,
1599 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1600 /// with another that has more specific requirements based on the type of the
1601 /// corresponding operand. This returns null if there is no replacement to
1603 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1605 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1606 /// vector. If it is invalid, don't add anything to Ops.
1607 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
1608 std::vector<SDValue> &Ops,
1609 SelectionDAG &DAG) const;
1611 //===--------------------------------------------------------------------===//
1612 // Instruction Emitting Hooks
1615 // EmitInstrWithCustomInserter - This method should be implemented by targets
1616 // that mark instructions with the 'usesCustomInserter' flag. These
1617 // instructions are special in various ways, which require special support to
1618 // insert. The specified MachineInstr is created but not inserted into any
1619 // basic blocks, and this method is called to expand it into a sequence of
1620 // instructions, potentially also creating new basic blocks and control flow.
1621 virtual MachineBasicBlock *
1622 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
1624 /// AdjustInstrPostInstrSelection - This method should be implemented by
1625 /// targets that mark instructions with the 'hasPostISelHook' flag. These
1626 /// instructions must be adjusted after instruction selection by target hooks.
1627 /// e.g. To fill in optional defs for ARM 's' setting instructions.
1629 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
1631 //===--------------------------------------------------------------------===//
1632 // Addressing mode description hooks (used by LSR etc).
1635 /// AddrMode - This represents an addressing mode of:
1636 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1637 /// If BaseGV is null, there is no BaseGV.
1638 /// If BaseOffs is zero, there is no base offset.
1639 /// If HasBaseReg is false, there is no base register.
1640 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1644 GlobalValue *BaseGV;
1648 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1651 /// GetAddrModeArguments - CodeGenPrepare sinks address calculations into the
1652 /// same BB as Load/Store instructions reading the address. This allows as
1653 /// much computation as possible to be done in the address mode for that
1654 /// operand. This hook lets targets also pass back when this should be done
1655 /// on intrinsics which load/store.
1656 virtual bool GetAddrModeArguments(IntrinsicInst *I,
1657 SmallVectorImpl<Value*> &Ops,
1658 Type *&AccessTy) const {
1662 /// isLegalAddressingMode - Return true if the addressing mode represented by
1663 /// AM is legal for this target, for a load/store of the specified type.
1664 /// The type may be VoidTy, in which case only return true if the addressing
1665 /// mode is legal for a load/store of any legal type.
1666 /// TODO: Handle pre/postinc as well.
1667 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1669 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1670 /// icmp immediate, that is the target has icmp instructions which can compare
1671 /// a register against the immediate without having to materialize the
1672 /// immediate into a register.
1673 virtual bool isLegalICmpImmediate(int64_t) const {
1677 /// isLegalAddImmediate - Return true if the specified immediate is legal
1678 /// add immediate, that is the target has add instructions which can add
1679 /// a register with the immediate without having to materialize the
1680 /// immediate into a register.
1681 virtual bool isLegalAddImmediate(int64_t) const {
1685 /// isTruncateFree - Return true if it's free to truncate a value of
1686 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1687 /// register EAX to i16 by referencing its sub-register AX.
1688 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1692 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1696 /// isZExtFree - Return true if any actual instruction that defines a
1697 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1698 /// register. This does not necessarily include registers defined in
1699 /// unknown ways, such as incoming arguments, or copies from unknown
1700 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1701 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1702 /// all instructions that define 32-bit values implicit zero-extend the
1703 /// result out to 64 bits.
1704 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1708 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1712 /// isFNegFree - Return true if an fneg operation is free to the point where
1713 /// it is never worthwhile to replace it with a bitwise operation.
1714 virtual bool isFNegFree(EVT) const {
1718 /// isFAbsFree - Return true if an fneg operation is free to the point where
1719 /// it is never worthwhile to replace it with a bitwise operation.
1720 virtual bool isFAbsFree(EVT) const {
1724 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
1725 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
1726 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
1727 /// is expanded to mul + add.
1728 virtual bool isFMAFasterThanMulAndAdd(EVT) const {
1732 /// isNarrowingProfitable - Return true if it's profitable to narrow
1733 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1734 /// from i32 to i8 but not from i32 to i16.
1735 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1739 //===--------------------------------------------------------------------===//
1740 // Div utility functions
1742 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
1743 SelectionDAG &DAG) const;
1744 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
1745 std::vector<SDNode*>* Created) const;
1746 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
1747 std::vector<SDNode*>* Created) const;
1750 //===--------------------------------------------------------------------===//
1751 // Runtime Library hooks
1754 /// setLibcallName - Rename the default libcall routine name for the specified
1756 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1757 LibcallRoutineNames[Call] = Name;
1760 /// getLibcallName - Get the libcall routine name for the specified libcall.
1762 const char *getLibcallName(RTLIB::Libcall Call) const {
1763 return LibcallRoutineNames[Call];
1766 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1767 /// result of the comparison libcall against zero.
1768 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1769 CmpLibcallCCs[Call] = CC;
1772 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1773 /// the comparison libcall against zero.
1774 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1775 return CmpLibcallCCs[Call];
1778 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1779 /// specified libcall.
1780 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1781 LibcallCallingConvs[Call] = CC;
1784 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1785 /// specified libcall.
1786 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1787 return LibcallCallingConvs[Call];
1791 const TargetMachine &TM;
1792 const DataLayout *TD;
1793 const TargetLoweringObjectFile &TLOF;
1795 /// PointerTy - The type to use for pointers, usually i32 or i64.
1799 /// IsLittleEndian - True if this is a little endian target.
1801 bool IsLittleEndian;
1803 /// SelectIsExpensive - Tells the code generator not to expand operations
1804 /// into sequences that use the select operations if possible.
1805 bool SelectIsExpensive;
1807 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1808 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1809 /// a real cost model is in place. If we ever optimize for size, this will be
1810 /// set to true unconditionally.
1813 /// BypassSlowDivMap - Tells the code generator to bypass slow divide or
1814 /// remainder instructions. For example, BypassSlowDivWidths[32,8] tells the
1815 /// code generator to bypass 32-bit integer div/rem with an 8-bit unsigned
1816 /// integer div/rem when the operands are positive and less than 256.
1817 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1819 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1820 /// srl/add/sra for a signed divide by power of two, and let the target handle
1822 bool Pow2DivIsCheap;
1824 /// JumpIsExpensive - Tells the code generator that it shouldn't generate
1825 /// extra flow control instructions and should attempt to combine flow
1826 /// control instructions via predication.
1827 bool JumpIsExpensive;
1829 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1830 /// llvm.setjmp. Defaults to false.
1831 bool UseUnderscoreSetJmp;
1833 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1834 /// llvm.longjmp. Defaults to false.
1835 bool UseUnderscoreLongJmp;
1837 /// SupportJumpTables - Whether the target can generate code for jumptables.
1838 /// If it's not true, then each jumptable must be lowered into if-then-else's.
1839 bool SupportJumpTables;
1841 /// MinimumJumpTableEntries - Number of blocks threshold to use jump tables.
1842 int MinimumJumpTableEntries;
1844 /// BooleanContents - Information about the contents of the high-bits in
1845 /// boolean values held in a type wider than i1. See getBooleanContents.
1846 BooleanContent BooleanContents;
1847 /// BooleanVectorContents - Information about the contents of the high-bits
1848 /// in boolean vector values when the element type is wider than i1. See
1849 /// getBooleanContents.
1850 BooleanContent BooleanVectorContents;
1852 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1853 /// total cycles or lowest register usage.
1854 Sched::Preference SchedPreferenceInfo;
1856 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1857 unsigned JumpBufSize;
1859 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1861 unsigned JumpBufAlignment;
1863 /// MinStackArgumentAlignment - The minimum alignment that any argument
1864 /// on the stack needs to have.
1866 unsigned MinStackArgumentAlignment;
1868 /// MinFunctionAlignment - The minimum function alignment (used when
1869 /// optimizing for size, and to prevent explicitly provided alignment
1870 /// from leading to incorrect code).
1872 unsigned MinFunctionAlignment;
1874 /// PrefFunctionAlignment - The preferred function alignment (used when
1875 /// alignment unspecified and optimizing for speed).
1877 unsigned PrefFunctionAlignment;
1879 /// PrefLoopAlignment - The preferred loop alignment.
1881 unsigned PrefLoopAlignment;
1883 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should
1884 /// be folded into the enclosed atomic intrinsic instruction by the
1886 bool ShouldFoldAtomicFences;
1888 /// InsertFencesForAtomic - Whether the DAG builder should automatically
1889 /// insert fences and reduce ordering for atomics. (This will be set for
1890 /// for most architectures with weak memory ordering.)
1891 bool InsertFencesForAtomic;
1893 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1894 /// specifies the register that llvm.savestack/llvm.restorestack should save
1896 unsigned StackPointerRegisterToSaveRestore;
1898 /// ExceptionPointerRegister - If set to a physical register, this specifies
1899 /// the register that receives the exception address on entry to a landing
1901 unsigned ExceptionPointerRegister;
1903 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1904 /// the register that receives the exception typeid on entry to a landing
1906 unsigned ExceptionSelectorRegister;
1908 /// RegClassForVT - This indicates the default register class to use for
1909 /// each ValueType the target supports natively.
1910 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1911 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1912 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1914 /// RepRegClassForVT - This indicates the "representative" register class to
1915 /// use for each ValueType the target supports natively. This information is
1916 /// used by the scheduler to track register pressure. By default, the
1917 /// representative register class is the largest legal super-reg register
1918 /// class of the register class of the specified type. e.g. On x86, i8, i16,
1919 /// and i32's representative class would be GR32.
1920 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1922 /// RepRegClassCostForVT - This indicates the "cost" of the "representative"
1923 /// register class for each ValueType. The cost is used by the scheduler to
1924 /// approximate register pressure.
1925 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1927 /// TransformToType - For any value types we are promoting or expanding, this
1928 /// contains the value type that we are changing to. For Expanded types, this
1929 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1930 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1931 /// by the system, this holds the same type (e.g. i32 -> i32).
1932 EVT TransformToType[MVT::LAST_VALUETYPE];
1934 /// OpActions - For each operation and each value type, keep a LegalizeAction
1935 /// that indicates how instruction selection should deal with the operation.
1936 /// Most operations are Legal (aka, supported natively by the target), but
1937 /// operations that are not should be described. Note that operations on
1938 /// non-legal value types are not described here.
1939 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1941 /// LoadExtActions - For each load extension type and each value type,
1942 /// keep a LegalizeAction that indicates how instruction selection should deal
1943 /// with a load of a specific value type and extension type.
1944 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1946 /// TruncStoreActions - For each value type pair keep a LegalizeAction that
1947 /// indicates whether a truncating store of a specific value type and
1948 /// truncating type is legal.
1949 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1951 /// IndexedModeActions - For each indexed mode and each value type,
1952 /// keep a pair of LegalizeAction that indicates how instruction
1953 /// selection should deal with the load / store. The first dimension is the
1954 /// value_type for the reference. The second dimension represents the various
1955 /// modes for load store.
1956 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1958 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1959 /// LegalizeAction that indicates how instruction selection should
1960 /// deal with the condition code.
1961 /// Because each CC action takes up 2 bits, we need to have the array size
1962 /// be large enough to fit all of the value types. This can be done by
1963 /// dividing the MVT::LAST_VALUETYPE by 32 and adding one.
1964 uint64_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE / 32) + 1];
1966 ValueTypeActionImpl ValueTypeActions;
1968 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
1971 getTypeConversion(LLVMContext &Context, EVT VT) const {
1972 // If this is a simple type, use the ComputeRegisterProp mechanism.
1973 if (VT.isSimple()) {
1974 assert((unsigned)VT.getSimpleVT().SimpleTy <
1975 array_lengthof(TransformToType));
1976 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
1977 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(VT.getSimpleVT());
1980 (!(NVT.isSimple() && LA != TypeLegal) ||
1981 ValueTypeActions.getTypeAction(NVT.getSimpleVT()) != TypePromoteInteger)
1982 && "Promote may not follow Expand or Promote");
1984 return LegalizeKind(LA, NVT);
1987 // Handle Extended Scalar Types.
1988 if (!VT.isVector()) {
1989 assert(VT.isInteger() && "Float types must be simple");
1990 unsigned BitSize = VT.getSizeInBits();
1991 // First promote to a power-of-two size, then expand if necessary.
1992 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1993 EVT NVT = VT.getRoundIntegerType(Context);
1994 assert(NVT != VT && "Unable to round integer VT");
1995 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1996 // Avoid multi-step promotion.
1997 if (NextStep.first == TypePromoteInteger) return NextStep;
1998 // Return rounded integer type.
1999 return LegalizeKind(TypePromoteInteger, NVT);
2002 return LegalizeKind(TypeExpandInteger,
2003 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
2006 // Handle vector types.
2007 unsigned NumElts = VT.getVectorNumElements();
2008 EVT EltVT = VT.getVectorElementType();
2010 // Vectors with only one element are always scalarized.
2012 return LegalizeKind(TypeScalarizeVector, EltVT);
2014 // Try to widen vector elements until a legal type is found.
2015 if (EltVT.isInteger()) {
2016 // Vectors with a number of elements that is not a power of two are always
2017 // widened, for example <3 x float> -> <4 x float>.
2018 if (!VT.isPow2VectorType()) {
2019 NumElts = (unsigned)NextPowerOf2(NumElts);
2020 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
2021 return LegalizeKind(TypeWidenVector, NVT);
2024 // Examine the element type.
2025 LegalizeKind LK = getTypeConversion(Context, EltVT);
2027 // If type is to be expanded, split the vector.
2028 // <4 x i140> -> <2 x i140>
2029 if (LK.first == TypeExpandInteger)
2030 return LegalizeKind(TypeSplitVector,
2031 EVT::getVectorVT(Context, EltVT, NumElts / 2));
2033 // Promote the integer element types until a legal vector type is found
2034 // or until the element integer type is too big. If a legal type was not
2035 // found, fallback to the usual mechanism of widening/splitting the
2038 // Increase the bitwidth of the element to the next pow-of-two
2039 // (which is greater than 8 bits).
2040 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
2041 ).getRoundIntegerType(Context);
2043 // Stop trying when getting a non-simple element type.
2044 // Note that vector elements may be greater than legal vector element
2045 // types. Example: X86 XMM registers hold 64bit element on 32bit systems.
2046 if (!EltVT.isSimple()) break;
2048 // Build a new vector type and check if it is legal.
2049 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
2050 // Found a legal promoted vector type.
2051 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
2052 return LegalizeKind(TypePromoteInteger,
2053 EVT::getVectorVT(Context, EltVT, NumElts));
2057 // Try to widen the vector until a legal type is found.
2058 // If there is no wider legal type, split the vector.
2060 // Round up to the next power of 2.
2061 NumElts = (unsigned)NextPowerOf2(NumElts);
2063 // If there is no simple vector type with this many elements then there
2064 // cannot be a larger legal vector type. Note that this assumes that
2065 // there are no skipped intermediate vector types in the simple types.
2066 if (!EltVT.isSimple()) break;
2067 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
2068 if (LargerVector == MVT()) break;
2070 // If this type is legal then widen the vector.
2071 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
2072 return LegalizeKind(TypeWidenVector, LargerVector);
2075 // Widen odd vectors to next power of two.
2076 if (!VT.isPow2VectorType()) {
2077 EVT NVT = VT.getPow2VectorType(Context);
2078 return LegalizeKind(TypeWidenVector, NVT);
2081 // Vectors with illegal element types are expanded.
2082 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
2083 return LegalizeKind(TypeSplitVector, NVT);
2086 std::vector<std::pair<EVT, const TargetRegisterClass*> > AvailableRegClasses;
2088 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
2089 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
2090 /// which sets a bit in this array.
2092 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2094 /// PromoteToType - For operations that must be promoted to a specific type,
2095 /// this holds the destination type. This map should be sparse, so don't hold
2098 /// Targets add entries to this map with AddPromotedToType(..), clients access
2099 /// this with getTypeToPromoteTo(..).
2100 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2103 /// LibcallRoutineNames - Stores the name each libcall.
2105 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
2107 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
2108 /// of each of the comparison libcall against zero.
2109 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2111 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
2113 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2116 /// When lowering \@llvm.memset this field specifies the maximum number of
2117 /// store operations that may be substituted for the call to memset. Targets
2118 /// must set this value based on the cost threshold for that target. Targets
2119 /// should assume that the memset will be done using as many of the largest
2120 /// store operations first, followed by smaller ones, if necessary, per
2121 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2122 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2123 /// store. This only applies to setting a constant array of a constant size.
2124 /// @brief Specify maximum number of store instructions per memset call.
2125 unsigned maxStoresPerMemset;
2127 /// Maximum number of stores operations that may be substituted for the call
2128 /// to memset, used for functions with OptSize attribute.
2129 unsigned maxStoresPerMemsetOptSize;
2131 /// When lowering \@llvm.memcpy this field specifies the maximum number of
2132 /// store operations that may be substituted for a call to memcpy. Targets
2133 /// must set this value based on the cost threshold for that target. Targets
2134 /// should assume that the memcpy will be done using as many of the largest
2135 /// store operations first, followed by smaller ones, if necessary, per
2136 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2137 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2138 /// and one 1-byte store. This only applies to copying a constant array of
2140 /// @brief Specify maximum bytes of store instructions per memcpy call.
2141 unsigned maxStoresPerMemcpy;
2143 /// Maximum number of store operations that may be substituted for a call
2144 /// to memcpy, used for functions with OptSize attribute.
2145 unsigned maxStoresPerMemcpyOptSize;
2147 /// When lowering \@llvm.memmove this field specifies the maximum number of
2148 /// store instructions that may be substituted for a call to memmove. Targets
2149 /// must set this value based on the cost threshold for that target. Targets
2150 /// should assume that the memmove will be done using as many of the largest
2151 /// store operations first, followed by smaller ones, if necessary, per
2152 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2153 /// with 8-bit alignment would result in nine 1-byte stores. This only
2154 /// applies to copying a constant array of constant size.
2155 /// @brief Specify maximum bytes of store instructions per memmove call.
2156 unsigned maxStoresPerMemmove;
2158 /// Maximum number of store instructions that may be substituted for a call
2159 /// to memmove, used for functions with OpSize attribute.
2160 unsigned maxStoresPerMemmoveOptSize;
2162 /// This field specifies whether the target can benefit from code placement
2164 bool benefitFromCodePlacementOpt;
2166 /// predictableSelectIsExpensive - Tells the code generator that select is
2167 /// more expensive than a branch if the branch is usually predicted right.
2168 bool predictableSelectIsExpensive;
2171 /// isLegalRC - Return true if the value types that can be represented by the
2172 /// specified register class are all legal.
2173 bool isLegalRC(const TargetRegisterClass *RC) const;
2176 /// GetReturnInfo - Given an LLVM IR type and return type attributes,
2177 /// compute the return value EVTs and flags, and optionally also
2178 /// the offsets, if the return value is being lowered to memory.
2179 void GetReturnInfo(Type* ReturnType, Attributes attr,
2180 SmallVectorImpl<ISD::OutputArg> &Outs,
2181 const TargetLowering &TLI);
2183 } // end llvm namespace