2 * Device Tree support for Rockchip RK3288
4 * Copyright (C) 2014 ROCKCHIP, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clocksource.h>
19 #include <linux/cpuidle.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/irqchip.h>
23 #include <linux/kernel.h>
24 #include <linux/of_address.h>
25 #include <linux/of_platform.h>
26 #include <linux/rockchip/common.h>
27 #include <linux/rockchip/cpu.h>
28 #include <linux/rockchip/cru.h>
29 #include <linux/rockchip/dvfs.h>
30 #include <linux/rockchip/grf.h>
31 #include <linux/rockchip/iomap.h>
32 #include <linux/rockchip/pmu.h>
34 #include <asm/cpuidle.h>
35 #include <asm/cputype.h>
36 #include <asm/mach/arch.h>
37 #include <asm/mach/map.h>
44 #define RK3288_DEVICE(name) \
46 .virtual = (unsigned long) RK_##name##_VIRT, \
47 .pfn = __phys_to_pfn(RK3288_##name##_PHYS), \
48 .length = RK3288_##name##_SIZE, \
52 #define RK3288_SERVICE_DEVICE(name) \
53 RK_DEVICE(RK3288_SERVICE_##name##_VIRT, RK3288_SERVICE_##name##_PHYS, RK3288_SERVICE_##name##_SIZE)
55 #define RK3288_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
56 #define RK3288_TIMER7_VIRT (RK_TIMER_VIRT + 0x20)
58 static struct map_desc rk3288_io_desc[] __initdata = {
65 RK3288_SERVICE_DEVICE(CORE),
66 RK3288_SERVICE_DEVICE(DMAC),
67 RK3288_SERVICE_DEVICE(GPU),
68 RK3288_SERVICE_DEVICE(PERI),
69 RK3288_SERVICE_DEVICE(VIO),
70 RK3288_SERVICE_DEVICE(VIDEO),
71 RK3288_SERVICE_DEVICE(HEVC),
72 RK3288_SERVICE_DEVICE(BUS),
73 RK_DEVICE(RK_DDR_VIRT, RK3288_DDR_PCTL0_PHYS, RK3288_DDR_PCTL_SIZE),
74 RK_DEVICE(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE, RK3288_DDR_PUBL0_PHYS, RK3288_DDR_PUBL_SIZE),
75 RK_DEVICE(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE, RK3288_DDR_PCTL1_PHYS, RK3288_DDR_PCTL_SIZE),
76 RK_DEVICE(RK_DDR_VIRT + 2 * RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE, RK3288_DDR_PUBL1_PHYS, RK3288_DDR_PUBL_SIZE),
77 RK_DEVICE(RK_GPIO_VIRT(0), RK3288_GPIO0_PHYS, RK3288_GPIO_SIZE),
78 RK_DEVICE(RK_GPIO_VIRT(1), RK3288_GPIO1_PHYS, RK3288_GPIO_SIZE),
79 RK_DEVICE(RK_GPIO_VIRT(2), RK3288_GPIO2_PHYS, RK3288_GPIO_SIZE),
80 RK_DEVICE(RK_GPIO_VIRT(3), RK3288_GPIO3_PHYS, RK3288_GPIO_SIZE),
81 RK_DEVICE(RK_GPIO_VIRT(4), RK3288_GPIO4_PHYS, RK3288_GPIO_SIZE),
82 RK_DEVICE(RK_GPIO_VIRT(5), RK3288_GPIO5_PHYS, RK3288_GPIO_SIZE),
83 RK_DEVICE(RK_GPIO_VIRT(6), RK3288_GPIO6_PHYS, RK3288_GPIO_SIZE),
84 RK_DEVICE(RK_GPIO_VIRT(7), RK3288_GPIO7_PHYS, RK3288_GPIO_SIZE),
85 RK_DEVICE(RK_GPIO_VIRT(8), RK3288_GPIO8_PHYS, RK3288_GPIO_SIZE),
86 RK_DEVICE(RK_DEBUG_UART_VIRT, RK3288_UART_DBG_PHYS, RK3288_UART_SIZE),
87 RK_DEVICE(RK_GIC_VIRT, RK3288_GIC_DIST_PHYS, RK3288_GIC_DIST_SIZE),
88 RK_DEVICE(RK_GIC_VIRT + RK3288_GIC_DIST_SIZE, RK3288_GIC_CPU_PHYS, RK3288_GIC_CPU_SIZE),
89 RK_DEVICE(RK_BOOTRAM_VIRT, RK3288_BOOTRAM_PHYS, RK3288_BOOTRAM_SIZE),
90 RK_DEVICE(RK3288_IMEM_VIRT, RK3288_IMEM_PHYS, SZ_4K),
91 RK_DEVICE(RK_TIMER_VIRT, RK3288_TIMER6_PHYS, RK3288_TIMER_SIZE),
94 static void __init rk3288_boot_mode_init(void)
96 u32 flag = readl_relaxed(RK_PMU_VIRT + RK3288_PMU_SYS_REG0);
97 u32 mode = readl_relaxed(RK_PMU_VIRT + RK3288_PMU_SYS_REG1);
98 u32 rst_st = readl_relaxed(RK_CRU_VIRT + RK3288_CRU_GLB_RST_ST);
100 if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER))
101 mode = BOOT_MODE_RECOVERY;
102 if (rst_st & ((1 << 4) | (1 << 5)))
103 mode = BOOT_MODE_WATCHDOG;
104 else if (rst_st & ((1 << 2) | (1 << 3)))
105 mode = BOOT_MODE_TSADC;
106 rockchip_boot_mode_init(flag, mode);
109 static void usb_uart_init(void)
113 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
114 soc_status2 = (readl_relaxed(RK_GRF_VIRT + RK3288_GRF_SOC_STATUS2));
116 #ifdef CONFIG_RK_USB_UART
117 if (!(soc_status2 & (1<<14)) && (soc_status2 & (1<<17))) {
118 /* software control usb phy enable */
119 writel_relaxed(0x00040004, RK_GRF_VIRT + RK3288_GRF_UOC0_CON2);
120 /* usb phy enter suspend */
121 writel_relaxed(0x003f002a, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
122 writel_relaxed(0x00c000c0, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
127 extern void secondary_startup(void);
129 static void __init rk3288_dt_map_io(void)
133 rockchip_soc_id = ROCKCHIP_SOC_RK3288;
135 iotable_init(rk3288_io_desc, ARRAY_SIZE(rk3288_io_desc));
139 /* pmu reset by second global soft reset */
140 v = readl_relaxed(RK_CRU_VIRT + RK3288_CRU_GLB_RST_CON);
143 writel_relaxed(v, RK_CRU_VIRT + RK3288_CRU_GLB_RST_CON);
145 /* rkpwm is used instead of old pwm */
146 writel_relaxed(0x00010001, RK_GRF_VIRT + RK3288_GRF_SOC_CON2);
148 /* disable address remap */
149 writel_relaxed(0x08000000, RK_SGRF_VIRT + RK3288_SGRF_SOC_CON0);
151 /* enable timer7 for core */
152 writel_relaxed(0, RK3288_TIMER7_VIRT + 0x10);
154 writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x00);
155 writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x04);
157 writel_relaxed(1, RK3288_TIMER7_VIRT + 0x10);
160 /* power up/down GPU domain wait 1us */
161 writel_relaxed(24, RK_PMU_VIRT + RK3288_PMU_GPU_PWRDWN_CNT);
162 writel_relaxed(24, RK_PMU_VIRT + RK3288_PMU_GPU_PWRUP_CNT);
164 rk3288_boot_mode_init();
165 rockchip_efuse_init();
168 static const u8 pmu_st_map[] = {
182 static bool rk3288_pmu_power_domain_is_on(enum pmu_power_domain pd)
184 /* 1'b0: power on, 1'b1: power off */
185 return !(readl_relaxed(RK_PMU_VIRT + RK3288_PMU_PWRDN_ST) & BIT(pmu_st_map[pd]));
188 static DEFINE_SPINLOCK(pmu_idle_lock);
190 static const u8 pmu_idle_map[] = {
194 [IDLE_REQ_VIDEO] = 3,
197 [IDLE_REQ_ALIVE] = 6,
203 static int rk3288_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
205 u32 bit = pmu_idle_map[req];
206 u32 idle_mask = BIT(bit) | BIT(bit + 16);
207 u32 idle_target = (idle << bit) | (idle << (bit + 16));
212 spin_lock_irqsave(&pmu_idle_lock, flags);
213 val = readl_relaxed(RK_PMU_VIRT + RK3288_PMU_IDLE_REQ);
218 writel_relaxed(val, RK_PMU_VIRT + RK3288_PMU_IDLE_REQ);
221 while ((readl_relaxed(RK_PMU_VIRT + RK3288_PMU_IDLE_ST) & idle_mask) != idle_target)
223 spin_unlock_irqrestore(&pmu_idle_lock, flags);
228 static const u8 pmu_pd_map[] = {
242 static DEFINE_SPINLOCK(pmu_pd_lock);
244 static noinline void rk3288_do_pmu_set_power_domain(enum pmu_power_domain domain, bool on)
246 u8 pd = pmu_pd_map[domain];
247 u32 val = readl_relaxed(RK_PMU_VIRT + RK3288_PMU_PWRDN_CON);
252 writel_relaxed(val, RK_PMU_VIRT + RK3288_PMU_PWRDN_CON);
255 while ((readl_relaxed(RK_PMU_VIRT + RK3288_PMU_PWRDN_ST) & BIT(pmu_st_map[domain])) == on)
259 static u32 gpu_r_qos[CPU_AXI_QOS_NUM_REGS];
260 static u32 gpu_w_qos[CPU_AXI_QOS_NUM_REGS];
261 static u32 vio0_iep_qos[CPU_AXI_QOS_NUM_REGS];
262 static u32 vio0_vip_qos[CPU_AXI_QOS_NUM_REGS];
263 static u32 vio0_vop_qos[CPU_AXI_QOS_NUM_REGS];
264 static u32 vio1_isp_r_qos[CPU_AXI_QOS_NUM_REGS];
265 static u32 vio1_isp_w0_qos[CPU_AXI_QOS_NUM_REGS];
266 static u32 vio1_isp_w1_qos[CPU_AXI_QOS_NUM_REGS];
267 static u32 vio1_vop_qos[CPU_AXI_QOS_NUM_REGS];
268 static u32 vio2_rga_r_qos[CPU_AXI_QOS_NUM_REGS];
269 static u32 vio2_rga_w_qos[CPU_AXI_QOS_NUM_REGS];
270 static u32 video_qos[CPU_AXI_QOS_NUM_REGS];
271 static u32 hevc_r_qos[CPU_AXI_QOS_NUM_REGS];
272 static u32 hevc_w_qos[CPU_AXI_QOS_NUM_REGS];
274 #define SAVE_QOS(array, NAME) CPU_AXI_SAVE_QOS(array, RK3288_CPU_AXI_##NAME##_QOS_VIRT)
275 #define RESTORE_QOS(array, NAME) CPU_AXI_RESTORE_QOS(array, RK3288_CPU_AXI_##NAME##_QOS_VIRT)
277 static int rk3288_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
281 spin_lock_irqsave(&pmu_pd_lock, flags);
282 if (rk3288_pmu_power_domain_is_on(pd) == on)
286 /* if power down, idle request to NIU first */
288 SAVE_QOS(vio0_iep_qos, VIO0_IEP);
289 SAVE_QOS(vio0_vip_qos, VIO0_VIP);
290 SAVE_QOS(vio0_vop_qos, VIO0_VOP);
291 SAVE_QOS(vio1_isp_r_qos, VIO1_ISP_R);
292 SAVE_QOS(vio1_isp_w0_qos, VIO1_ISP_W0);
293 SAVE_QOS(vio1_isp_w1_qos, VIO1_ISP_W1);
294 SAVE_QOS(vio1_vop_qos, VIO1_VOP);
295 SAVE_QOS(vio2_rga_r_qos, VIO2_RGA_R);
296 SAVE_QOS(vio2_rga_w_qos, VIO2_RGA_W);
297 rk3288_pmu_set_idle_request(IDLE_REQ_VIO, true);
298 } else if (pd == PD_VIDEO) {
299 SAVE_QOS(video_qos, VIDEO);
300 rk3288_pmu_set_idle_request(IDLE_REQ_VIDEO, true);
301 } else if (pd == PD_GPU) {
302 SAVE_QOS(gpu_r_qos, GPU_R);
303 SAVE_QOS(gpu_w_qos, GPU_W);
304 rk3288_pmu_set_idle_request(IDLE_REQ_GPU, true);
305 } else if (pd == PD_HEVC) {
306 SAVE_QOS(hevc_r_qos, HEVC_R);
307 SAVE_QOS(hevc_w_qos, HEVC_W);
308 rk3288_pmu_set_idle_request(IDLE_REQ_HEVC, true);
309 } else if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
310 writel_relaxed(0x20002 << (pd - PD_CPU_1), RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(0));
313 else if (pd == PD_PERI) {
314 rk3288_pmu_set_idle_request(IDLE_REQ_PERI, true);
319 rk3288_do_pmu_set_power_domain(pd, on);
322 /* if power up, idle request release to NIU */
324 rk3288_pmu_set_idle_request(IDLE_REQ_VIO, false);
325 RESTORE_QOS(vio0_iep_qos, VIO0_IEP);
326 RESTORE_QOS(vio0_vip_qos, VIO0_VIP);
327 RESTORE_QOS(vio0_vop_qos, VIO0_VOP);
328 RESTORE_QOS(vio1_isp_r_qos, VIO1_ISP_R);
329 RESTORE_QOS(vio1_isp_w0_qos, VIO1_ISP_W0);
330 RESTORE_QOS(vio1_isp_w1_qos, VIO1_ISP_W1);
331 RESTORE_QOS(vio1_vop_qos, VIO1_VOP);
332 RESTORE_QOS(vio2_rga_r_qos, VIO2_RGA_R);
333 RESTORE_QOS(vio2_rga_w_qos, VIO2_RGA_W);
334 } else if (pd == PD_VIDEO) {
335 rk3288_pmu_set_idle_request(IDLE_REQ_VIDEO, false);
336 RESTORE_QOS(video_qos, VIDEO);
337 } else if (pd == PD_GPU) {
338 rk3288_pmu_set_idle_request(IDLE_REQ_GPU, false);
339 RESTORE_QOS(gpu_r_qos, GPU_R);
340 RESTORE_QOS(gpu_w_qos, GPU_W);
341 } else if (pd == PD_HEVC) {
342 rk3288_pmu_set_idle_request(IDLE_REQ_HEVC, false);
343 RESTORE_QOS(hevc_r_qos, HEVC_R);
344 RESTORE_QOS(hevc_w_qos, HEVC_W);
345 } else if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
347 writel_relaxed(0x20000 << (pd - PD_CPU_1), RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(0));
350 writel_relaxed(virt_to_phys(secondary_startup), RK3288_IMEM_VIRT + 8);
351 writel_relaxed(0xDEADBEAF, RK3288_IMEM_VIRT + 4);
355 else if (pd == PD_PERI) {
356 rk3288_pmu_set_idle_request(IDLE_REQ_PERI, false);
361 spin_unlock_irqrestore(&pmu_pd_lock, flags);
365 static int rk3288_sys_set_power_domain(enum pmu_power_domain pd, bool on)
367 u32 clks_ungating[RK3288_CRU_CLKGATES_CON_CNT];
368 u32 clks_save[RK3288_CRU_CLKGATES_CON_CNT];
371 for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) {
372 clks_save[i] = cru_readl(RK3288_CRU_CLKGATES_CON(i));
373 clks_ungating[i] = 0;
379 clks_ungating[5] = 1 << 7;
381 clks_ungating[18] = 1 << 0;
384 /* aclk_vdpu_src hclk_vpu aclk_vepu_src */
385 clks_ungating[3] = 1 << 11 | 1 << 10 | 1 << 9;
386 /* hclk_video aclk_video */
387 clks_ungating[9] = 1 << 1 | 1 << 0;
390 /* aclk_lcdc0/1_src dclk_lcdc0/1_src rga_core aclk_rga_src */
391 /* edp_24m edp isp isp_jpeg */
393 1 << 0 | 1 << 1 | 1 << 2 | 1 << 3 | 1 << 4 | 1 << 5 |
394 1 << 12 | 1 << 13 | 1 << 14 | 1 << 15;
395 clks_ungating[15] = 0xffff;
396 clks_ungating[16] = 0x0fff;
399 /* hevc_core hevc_cabac aclk_hevc */
400 clks_ungating[13] = 1 << 15 | 1 << 14 | 1 << 13;
404 clks_ungating[12] = 1 << 11 | 1 < 10 | 1 << 9 | 1 << 8;
411 for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) {
412 if (clks_ungating[i])
413 cru_writel(clks_ungating[i] << 16, RK3288_CRU_CLKGATES_CON(i));
416 ret = rk3288_pmu_set_power_domain(pd, on);
418 for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) {
419 if (clks_ungating[i])
420 cru_writel(clks_save[i] | 0xffff0000, RK3288_CRU_CLKGATES_CON(i));
426 static void __init rk3288_dt_init_timer(void)
428 rockchip_pmu_ops.set_power_domain = rk3288_sys_set_power_domain;
429 rockchip_pmu_ops.power_domain_is_on = rk3288_pmu_power_domain_is_on;
430 rockchip_pmu_ops.set_idle_request = rk3288_pmu_set_idle_request;
432 clocksource_of_init();
436 static void __init rk3288_reserve(void)
438 /* reserve memory for ION */
439 rockchip_ion_reserve();
442 static const char * const rk3288_dt_compat[] __initconst = {
447 static void rk3288_restart(char mode, const char *cmd)
449 u32 boot_flag, boot_mode;
451 rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
453 writel_relaxed(boot_flag, RK_PMU_VIRT + RK3288_PMU_SYS_REG0); // for loader
454 writel_relaxed(boot_mode, RK_PMU_VIRT + RK3288_PMU_SYS_REG1); // for linux
457 /* pll enter slow mode */
458 writel_relaxed(0xf3030000, RK_CRU_VIRT + RK3288_CRU_MODE_CON);
460 writel_relaxed(0xeca8, RK_CRU_VIRT + RK3288_CRU_GLB_SRST_SND_VALUE);
464 static struct cpuidle_driver rk3288_cpuidle_driver = {
465 .name = "rk3288_cpuidle",
466 .owner = THIS_MODULE,
467 .states[0] = ARM_CPUIDLE_WFI_STATE,
471 static int rk3288_cpuidle_enter(struct cpuidle_device *dev,
472 struct cpuidle_driver *drv, int index)
474 void *sel = RK_CRU_VIRT + RK3288_CRU_CLKSELS_CON(36);
475 u32 con = readl_relaxed(sel);
476 u32 cpu = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 0);
477 writel_relaxed(0x70007 << (cpu << 2), sel);
479 writel_relaxed((0x70000 << (cpu << 2)) | con, sel);
484 static void __init rk3288_init_cpuidle(void)
488 if (!rockchip_jtag_enabled)
489 rk3288_cpuidle_driver.states[0].enter = rk3288_cpuidle_enter;
490 ret = cpuidle_register(&rk3288_cpuidle_driver, NULL);
492 pr_err("%s: failed to register cpuidle driver: %d\n", __func__, ret);
495 static int rk3288_pll_early_suspend_notifier_call(struct notifier_block *self,
496 unsigned long action, void *data)
498 struct fb_event *event = data;
499 int blank_mode = *((int *)event->data);
501 if (action == FB_EARLY_EVENT_BLANK) {
502 switch (blank_mode) {
503 case FB_BLANK_UNBLANK:
504 clk_prepare_enable(clk_get_sys(NULL, "clk_cpll"));
505 clk_prepare_enable(clk_get_sys(NULL, "clk_npll"));
510 } else if (action == FB_EVENT_BLANK) {
511 switch (blank_mode) {
512 case FB_BLANK_POWERDOWN:
513 clk_disable_unprepare(clk_get_sys(NULL, "clk_cpll"));
514 clk_disable_unprepare(clk_get_sys(NULL, "clk_npll"));
524 static struct notifier_block rk3288_pll_early_suspend_notifier = {
525 .notifier_call = rk3288_pll_early_suspend_notifier_call,
529 static void __init rk3288_init_suspend(void);
531 static void __init rk3288_init_late(void)
534 rk3288_init_suspend();
536 #ifdef CONFIG_CPU_IDLE
537 rk3288_init_cpuidle();
539 if (rockchip_jtag_enabled)
540 clk_prepare_enable(clk_get_sys(NULL, "clk_jtag"));
543 DT_MACHINE_START(RK3288_DT, "Rockchip RK3288 (Flattened Device Tree)")
544 .smp = smp_ops(rockchip_smp_ops),
545 .map_io = rk3288_dt_map_io,
546 .init_time = rk3288_dt_init_timer,
547 .dt_compat = rk3288_dt_compat,
548 .init_late = rk3288_init_late,
549 .reserve = rk3288_reserve,
550 .restart = rk3288_restart,
553 char PIE_DATA(sram_stack)[1024];
554 EXPORT_PIE_SYMBOL(DATA(sram_stack));
556 static int __init rk3288_pie_init(void)
559 if (!cpu_is_rk3288())
562 err = rockchip_pie_init();
566 rockchip_pie_chunk = pie_load_sections(rockchip_sram_pool, rk3288);
567 if (IS_ERR(rockchip_pie_chunk)) {
568 err = PTR_ERR(rockchip_pie_chunk);
569 pr_err("%s: failed to load section %d\n", __func__, err);
570 rockchip_pie_chunk = NULL;
574 rockchip_sram_virt = kern_to_pie(rockchip_pie_chunk, &__pie_common_start[0]);
575 rockchip_sram_stack = kern_to_pie(rockchip_pie_chunk, (char *) DATA(sram_stack) + sizeof(DATA(sram_stack)));
579 arch_initcall(rk3288_pie_init);
581 #include "pm-rk3288.c"
583 static u32 rk_pmu_pwrdn_st;
584 static inline void rk_pm_soc_pd_suspend(void)
586 rk_pmu_pwrdn_st = pmu_readl(RK3288_PMU_PWRDN_ST);
588 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_GPU])))
589 rk3288_sys_set_power_domain(PD_GPU, false);
591 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_HEVC])))
592 rk3288_sys_set_power_domain(PD_HEVC, false);
594 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_VIO])))
595 rk3288_sys_set_power_domain(PD_VIO, false);
597 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_VIDEO])))
598 rk3288_sys_set_power_domain(PD_VIDEO, false);
600 rkpm_ddr_printascii("pd state:");
601 rkpm_ddr_printhex(rk_pmu_pwrdn_st);
602 rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRDN_ST));
603 rkpm_ddr_printascii("\n");
606 static inline void rk_pm_soc_pd_resume(void)
608 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_GPU])))
609 rk3288_sys_set_power_domain(PD_GPU, true);
611 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_HEVC])))
612 rk3288_sys_set_power_domain(PD_HEVC, true);
614 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_VIO])))
615 rk3288_sys_set_power_domain(PD_VIO, true);
617 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_VIDEO])))
618 rk3288_sys_set_power_domain(PD_VIDEO, true);
621 rkpm_ddr_printascii("pd state:");
622 rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRDN_ST));
623 rkpm_ddr_printascii("\n");
626 void inline rkpm_periph_pd_dn(bool on)
628 rk3288_sys_set_power_domain(PD_PERI, on);
631 static void __init rk3288_init_suspend(void)
633 printk("%s\n",__FUNCTION__);
634 fb_register_client(&rk3288_pll_early_suspend_notifier);
635 rockchip_suspend_init();
637 rk3288_suspend_init();
638 rkpm_set_ops_pwr_dmns(rk_pm_soc_pd_suspend,rk_pm_soc_pd_resume);
642 extern bool console_suspend_enabled;
644 static int __init rk3288_pm_dbg(void)
647 console_suspend_enabled=0;
649 pm_suspend(PM_SUSPEND_MEM);
657 //late_initcall_sync(rk3288_pm_dbg);
662 #define sram_printascii(s) do {} while (0) /* FIXME */
663 #include "ddr_rk32.c"
665 static int __init rk3288_ddr_init(void)
669 ddr_change_freq = _ddr_change_freq;
670 ddr_round_rate = _ddr_round_rate;
671 ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
672 ddr_bandwidth_get = _ddr_bandwidth_get;
674 ddr_init(DDR3_DEFAULT, 0);
679 arch_initcall_sync(rk3288_ddr_init);