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R600/SI: Add check for low 32 bits of encoding to mubuf tests
2014-08-11 Tom StellardR600/SI: Add check for low 32 bits of encoding to mubuf...
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2014-08-11 Tom StellardR600/SI: Clear lds bit on MUBUF instructions used for...
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2014-08-11 Tom StellardR600/SI: Fix broken test
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2014-08-09 Tom StellardR600/SI: Custom lower CONCAT_VECTORS
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2014-08-09 Tom StellardR600/SI: Update concat_vectors.ll to check for scratch...
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2014-08-05 Tom StellardR600/SI: Update MUBUF assembly string to match AMD...
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2014-08-05 Tom StellardR600/SI: Avoid generating REGISTER_LOAD instructions.
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2014-08-01 Tom StellardRevert "R600: Move code for generating REGISTER_LOAD...
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2014-08-01 Tom StellardR600/SI: Remove leftover debugging code
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2014-08-01 Tom StellardR600: Move code for generating REGISTER_LOAD into R600ISelLo...
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2014-08-01 Tom StellardR600/SI: Fix build warning
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2014-08-01 Tom StellardR600/SI: Do abs/neg folding with ComplexPatterns
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2014-08-01 Tom StellardTableGen: Allow AddedComplexity values to be negative
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2014-08-01 Tom StellardR600/SI: Simplify and fix handling of VOP2 in SIInstrInfo...
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2014-08-01 Tom StellardR600/SI: Fold immediates when shrinking instructions
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2014-08-01 Tom StellardR600/SI: Fix incorrect commute operation in shrink...
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2014-07-21 Tom Stellardtest-release.sh: Add support for dot releases
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2014-07-21 Tom StellardR600/SI: Refactor VOP3 instruction definitions
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2014-07-21 Tom StellardR600/SI: Separate encoding and operand definitions...
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2014-07-21 Tom StellardR600/SI: Initailize encoding fields of unused VOP3...
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2014-07-21 Tom StellardR600/SI: Initialize unused VOP3 sources to 0 instead...
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2014-07-21 Tom StellardR600/SI: Add instruction shrinking pass
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2014-07-21 Tom StellardR600/SI: VOPC instructions explicitly define VCC
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2014-07-21 Tom StellardR600/SI: Clean up some of the unused REGISTER_{LOAD...
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2014-07-21 Tom StellardR600/SI: Use scratch memory for large private arrays
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2014-07-21 Tom StellardR600/SI: Specify wavefront size for SI and CI
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2014-07-21 Tom StellardR600/SI: Remove vaddr operand from BUFFER_LOAD_*_OFFSET...
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2014-07-21 Tom Stellarddocs: Update relaease documents to include the patch...
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2014-07-21 Tom StellardR600/SI: Store constant initializer data in constant...
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2014-07-21 Tom StellardR600/SI: Add isCFDepth0 Predicate to SALU addc pattern
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2014-07-21 Tom StellardR600/SI: Use VALU for i1 XOR
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2014-07-21 Tom StellardR600/SI: Use a custom encoding method for simm16 in...
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2014-07-21 Tom StellardR600/SI: Rename SOPP operands to match the encoding...
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2014-07-21 Tom StellardTableGen: Allow AddedComplexity values to be negative
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2014-07-02 Tom StellardR600: Add a comment that llvm.AMDGPU.trunc is a legacy...
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2014-07-02 Tom StellardR600/SI: Use a ComplexPattern for ADDR64 addressing...
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2014-07-02 Tom StellardR600: Promote i64 loads to v2i32
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2014-07-02 Tom StellardR600/SI: Adjsut SGPR live ranges before register allocation
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2014-07-02 Tom StellardR600/SI: Add verifier check for immediates in register...
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2014-06-24 Tom StellardR600/SI: Use a ComplexPattern for MUBUF stores
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2014-06-24 Tom StellardR600: Promote i64 stores to v2i32
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2014-06-20 Tom StellardR600/SI: Add patterns for ctpop inside a branch
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2014-06-20 Tom StellardR600/SI: Add a pattern for f32 ftrunc
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2014-06-20 Tom StellardR600: Expand vector flog2
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2014-06-20 Tom StellardR600: Expand vector fexp2
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2014-06-20 Tom StellardR600/SI: SI Control Flow Annotation bug fixed
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2014-06-20 Tom StellardR600/SI: Add a VALU pattern for i64 xor
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2014-06-17 Tom StellardR600/SI: Make sure target flags are set on pseudo VOP3...
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2014-06-17 Tom StellardR600: Use LDS and vectors for private memory
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2014-06-17 Tom StellardR600/SI: Add a pattern for llvm.AMDGPU.barrier.global
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2014-06-17 Tom StellardSelectionDAG: Expand i64 = FP_TO_SINT i32
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2014-06-17 Tom StellardR600/SI: Re-initialize the m0 register after using...
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2014-06-13 Tom StellardR600: Remove AMDIL instruction and register definitions
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2014-06-13 Tom StellardR600: Move AMDGPUInstrInfo from AMDGPUTargetMachine...
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2014-06-13 Tom StellardR600: Drop use of cached TargetMachine in R600InstrInfo.cpp
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2014-06-13 Tom StellardR600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cpp
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2014-06-12 Tom StellardRevert "SelectionDAG: Enable (and (setcc x), (setcc...
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2014-06-11 Tom StellardR600: Set correct InstrItinClass for instructions using...
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2014-06-11 Tom StellardR600: BCNT_INT is a vector only instruction
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2014-06-10 Tom StellardR600/SI: Emit an error when attempting to spill VGPRs v4
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2014-06-10 Tom StellardR600/SI: Fix a crash when spilling SGPRs
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2014-06-10 Tom StellardHexagon: Expand i1 SELECT_CC
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2014-06-10 Tom StellardSelectionDAG: Don't use MVT::Other to determine legality...
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2014-06-10 Tom StellardSelectionDAG: Enable (and (setcc x), (setcc y)) ->...
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2014-06-10 Tom StellardSelectionDAG: Expand SELECT_CC to SELECT + SETCC
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2014-05-16 Tom StellardR600/SI: Refactor the VOP3_32 tablegen class
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2014-05-16 Tom StellardR600/SI: Add a PredicateControl class for managing...
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2014-05-16 Tom StellardR600/SI: Move tablegen patterns away from instruction...
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2014-05-16 Tom StellardR600/SI: Remove unused instruction
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2014-05-16 Tom StellardR600/SI: Promote f32 SELECT to i32
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2014-05-16 Tom StellardR600/SI: Remove duplicate pattern
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2014-05-15 Tom Stellardautoconf: Fix libLLVM-Major-Minor-Patch.so symlink
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2014-05-15 Tom StellardR600/SI: Stop using VSrc_* as the default register...
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2014-05-15 Tom StellardR600/SI: Fix a bug with handling of INSERT_SUBREG in...
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2014-05-15 Tom StellardR600/SI: Only use SALU instructions for 64-bit add...
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2014-05-15 Tom StellardR600/SI: Use VALU instructions for i1 ops
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2014-05-13 Tom Stellardautoconf: Fix soname for libLLVM-Major.Minor.so (2nd...
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2014-05-13 Tom StellardRevert "autoconf: Fix soname for libLLVM-Major.Minor.so"
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2014-05-13 Tom Stellardautoconf: Fix soname for libLLVM-Major.Minor.so
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2014-05-09 Tom StellardR600/SI: Teach SIInstrInfo::moveToVALU() how to move...
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2014-05-09 Tom StellardR600/SI: Fix SMRD pattern for offsets > 32 bits
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2014-05-09 Tom StellardR600: Expand i64 SELECT_CC
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2014-05-09 Tom StellardR600: Move MIN/MAX matching from LowerOperation() to...
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2014-05-05 Tom StellardR600: Expand i64 ISD:SUB
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2014-05-02 Tom StellardR600/SI: Add processor type for Mullins.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2014-05-02 Tom StellardR600: Expand vector sin and cos.
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2014-05-02 Tom StellardR600: Expand TruncStore i64 -> {i16,i8}
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2014-05-02 Tom StellardR600/SI: Only create one instruction when spilling...
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2014-04-30 Tom StellardR600/SI: Use VALU instructions for copying i1 values
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2014-04-30 Tom StellardR600/SI: Teach moveToVALU how to handle some SMRD instructions
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2014-04-30 Tom StellardR600: Remove unused function AMDGPUSubtarget::getDefaultSize()
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2014-04-29 Tom StellardR600: Remove duplicate setting of SELECT expansion.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2014-04-29 Tom StellardR600/SI: Custom lower SI_IF and SI_ELSE to avoid machine...
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2014-04-29 Tom StellardR600/SI: Only select SALU instructions in the entry...
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2014-04-29 Tom StellardR600: optimize the UDIVREM 64 algorithm
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2014-04-29 Tom StellardR600: Implement iterative algorithm for udivrem
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2014-04-29 Tom StellardR600: Change UDIV/UREM to UDIVREM when legalizing types
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2014-04-29 Tom StellardR600: remove unused variable
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2014-04-22 Tom StellardR600/SI: Reorganize SIInstructions.td
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2014-04-18 Tom StellardR600/SI: Use SReg_64 instead of VSrc_64 when selecting...
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C/C++ LLVM-based compilers that forbids OOTA behaviors