8 years agoAdd back commits r219835 and a fixed version of r219829.
Rafael Espindola [Fri, 17 Oct 2014 01:48:58 +0000 (01:48 +0000)]
Add back commits r219835 and a fixed version of r219829.

The only difference from r219829 is using


instead of


in ELFObjectWriter which causes us to use the correct section symbol even if
we have multiple sections with the same name.

Original messages:

Correctly handle references to section symbols.

When processing assembly like

.long .text

we were creating a new undefined symbol .text. GAS on the other hand would
handle that as a reference to the .text section.

This patch implements that by creating the section symbols earlier so that
they are visible during asm parsing.

The patch also updates llvm-readobj to print the symbol number in the relocation
dump so that the test can differentiate between two sections with the same name.

Allow forward references to section symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220021 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PPC] Adjust some PowerPC tests to account for presence/absence of VSX
Bill Schmidt [Fri, 17 Oct 2014 01:41:22 +0000 (01:41 +0000)]
[PPC] Adjust some PowerPC tests to account for presence/absence of VSX

Patch by Bill Seurer; committed on his behalf.

These test cases generate slightly different code sequences when VSX
is activated and thus fail. The update turns off VSX explicitly for
the existing checks and then adds a second set of checks for most of
them that test the VSX instruction output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220019 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd a test that would have found the bug in r219829.
Rafael Espindola [Fri, 17 Oct 2014 01:34:23 +0000 (01:34 +0000)]
Add a test that would have found the bug in r219829.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220016 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoARM: Fix a bug which was causing convergence failure in constant-island pass.
Akira Hatanaka [Fri, 17 Oct 2014 01:31:47 +0000 (01:31 +0000)]
ARM: Fix a bug which was causing convergence failure in constant-island pass.

The bug is in ARMConstantIslands::createNewWater where the upper bound of the
new water split point is computed:

// This could point off the end of the block if we've already got constant
// pool entries following this block; only the last one is in the water list.
// Back past any possible branches (allow for a conditional and a maximally
// long unconditional).
if (BaseInsertOffset + 8 >= UserBBI.postOffset()) {
  BaseInsertOffset = UserBBI.postOffset() - UPad - 8;
  DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset));

The split point is supposed to be somewhere between the machine instruction that
loads from the constant pool entry and the end of the basic block, before branch
instructions. The code above is fine if the basic block is large enough and
there are a sufficient number of instructions following the machine instruction.
However, if the machine instruction is near the end of the basic block,
BaseInsertOffset can point to the machine instruction or another instruction
that precedes it, and this can lead to convergence failure.

This commit fixes this bug by ensuring BaseInsertOffset is larger than the
offset of the instruction following the constant-loading instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220015 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert commit r219835 and r219829.
Rafael Espindola [Fri, 17 Oct 2014 01:06:02 +0000 (01:06 +0000)]
Revert commit r219835 and r219829.

Revert "Correctly handle references to section symbols."
Revert "Allow forward references to section symbols."

Rui found a regression I am debugging.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220010 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[OCaml] Add Llvm.instr_clone.
Peter Zotov [Fri, 17 Oct 2014 01:02:40 +0000 (01:02 +0000)]
[OCaml] Add Llvm.instr_clone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220008 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[LLVM-C] Add LLVMInstructionClone.
Peter Zotov [Fri, 17 Oct 2014 01:02:34 +0000 (01:02 +0000)]
[LLVM-C] Add LLVMInstructionClone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220007 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[llvm-symbolizer] Introduce the -dsym-hint option.
Alexander Potapenko [Fri, 17 Oct 2014 00:50:19 +0000 (00:50 +0000)]
[llvm-symbolizer] Introduce the -dsym-hint option.

llvm-symbolizer will consult one of the .dSYM paths passed via -dsym-hint
if it fails to find the .dSYM bundle at the default location.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220004 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Simplify debug printing
Matt Arsenault [Fri, 17 Oct 2014 00:36:20 +0000 (00:36 +0000)]
R600/SI: Simplify debug printing

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219999 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd our own copy of the find_executable function to cope with installations
Peter Collingbourne [Thu, 16 Oct 2014 23:43:20 +0000 (23:43 +0000)]
Add our own copy of the find_executable function to cope with installations
that do not have the distutils.spawn package. Should hopefully fix the
aarch64 buildbot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219991 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Remove another VALU pattern
Matt Arsenault [Thu, 16 Oct 2014 23:33:37 +0000 (23:33 +0000)]
R600/SI: Remove another VALU pattern

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219988 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoInitial version of Go bindings.
Peter Collingbourne [Thu, 16 Oct 2014 22:48:02 +0000 (22:48 +0000)]
Initial version of Go bindings.

This code is based on the existing LLVM Go bindings project hosted at:

Note that all contributors to the gollvm project have agreed to relicense
their changes under the LLVM license and submit them to the LLVM project.

Differential Revision: http://reviews.llvm.org/D5684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219976 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoIntroduce LLVMParseCommandLineOptions C API function.
Peter Collingbourne [Thu, 16 Oct 2014 22:47:52 +0000 (22:47 +0000)]
Introduce LLVMParseCommandLineOptions C API function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219975 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReduce code duplication between patchpoint and non-patchpoint lowering. NFC.
Juergen Ributzka [Thu, 16 Oct 2014 21:26:35 +0000 (21:26 +0000)]
Reduce code duplication between patchpoint and non-patchpoint lowering. NFC.

This is in preparation for another patch that makes patchpoints invokable.

Reviewers: atrick, ributzka
Reviewed By: ributzka
Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5657

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219967 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SROA] Switch the common variable name for the 'AllocaSlices' class to
Chandler Carruth [Thu, 16 Oct 2014 21:11:55 +0000 (21:11 +0000)]
[SROA] Switch the common variable name for the 'AllocaSlices' class to

Using 'S' as this was a terrible idea. Arguably, 'AS' is not much
better, but it at least follows the idea of using initialisms and
removes active confusion about the AllocaSlices variable and a Slice

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219963 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SROA] More range-based cleanups to SROA, these brought to you by
Chandler Carruth [Thu, 16 Oct 2014 21:05:14 +0000 (21:05 +0000)]
[SROA] More range-based cleanups to SROA, these brought to you by

I did have to clean up the variable types and whitespace a bit because
the use of auto made the code much less readable here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219962 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SROA] Switch a couple of overly complex iterator accessors to just be
Chandler Carruth [Thu, 16 Oct 2014 20:42:08 +0000 (20:42 +0000)]
[SROA] Switch a couple of overly complex iterator accessors to just be
ArrayRef accessors.

I think this even came up in review that this was over-engineered, and
indeed it was. Time to un-build it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219958 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoErase fence insertion from SelectionDAGBuilder.cpp (NFC)
Robin Morisset [Thu, 16 Oct 2014 20:34:57 +0000 (20:34 +0000)]
Erase fence insertion from SelectionDAGBuilder.cpp (NFC)

Backends can use setInsertFencesForAtomic to signal to the middle-end that
montonic is the only memory ordering they can accept for
stores/loads/rmws/cmpxchg. The code lowering those accesses with a stronger
ordering to fences + monotonic accesses is currently living in
SelectionDAGBuilder.cpp. In this patch I propose moving this logic out of it
for several reasons:
- There is lots of redundancy to avoid: extremely similar logic already
  exists in AtomicExpand.
- The current code in SelectionDAGBuilder does not use any target-hooks, it
  does the same transformation for every backend that requires it
- As a result it is plain *unsound*, as it was apparently designed for ARM.
  It happens to mostly work for the other targets because they are extremely
  conservative, but Power for example had to switch to AtomicExpand to be
  able to use lwsync safely (see r218331).
- Because it produces IR-level fences, it cannot be made sound ! This is noted
  in the C++11 standard (section 29.3, page 1140):
Fences cannot, in general, be used to restore sequential consistency for atomic
operations with weaker ordering semantics.
It can also be seen by the following example (called IRIW in the litterature):
atomic<int> x = y = 0;
int r1, r2, r3, r4;
Thread 0:
Thread 1:
Thread 2:
  r1 = x.load();
  r2 = y.load();
Thread 3:
  r3 = y.load();
  r4 = x.load();
r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all seq_cst.
But if they are lowered to monotonic accesses, no amount of fences can prevent it..

This patch does three things (I could cut it into parts, but then some of them
would not be tested/testable, please tell me if you would prefer that):
- it provides a default implementation for emitLeadingFence/emitTrailingFence in
terms of IR-level fences, that mimic the original logic of SelectionDAGBuilder.
As we saw above, this is unsound, but the best that can be done without knowing
the targets well (and there is a comment warning about this risk).
- it then switches Mips/Sparc/XCore to use AtomicExpand, relying on this default
implementation (that exactly replicates the logic of SelectionDAGBuilder, so no
functional change)
- it finally erase this logic from SelectionDAGBuilder as it is dead-code.

Ideally, each target would define its own override for emitLeading/TrailingFence
using target-specific fences, but I do not know the Sparc/Mips/XCore memory model
well enough to do this, and they appear to be dealing fine with the ARM-inspired
default expansion for now (probably because they are overly conservative, as
Power was). If anyone wants to compile fences more agressively on these
platforms, the long comment should make it clear why he should first override

Test Plan: make check-all, no functional change

Reviewers: jfb, t.p.northover

Subscribers: aemerson, llvm-commits

Differential Revision: http://reviews.llvm.org/D5474

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219957 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Remove unnecessary VALU patterns
Matt Arsenault [Thu, 16 Oct 2014 20:31:50 +0000 (20:31 +0000)]
R600/SI: Remove unnecessary VALU patterns

These haven't been necessary since allowing
selecting SALU instructions in non-entry blocks
was enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219956 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SROA] Start more deeply moving SROA to use ranges rather than just
Chandler Carruth [Thu, 16 Oct 2014 20:24:07 +0000 (20:24 +0000)]
[SROA] Start more deeply moving SROA to use ranges rather than just

There are a ton of places where it essentially wants ranges
rather than just iterators. This is just the first step that adds the
core slice range typedefs and uses them in a couple of places. I still
have to explicitly construct them because they've not been punched
throughout the entire set of code. More range-based cleanups incoming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219955 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Fix nonsensical implementation of computeKnownBits for BFE
Matt Arsenault [Thu, 16 Oct 2014 20:07:40 +0000 (20:07 +0000)]
R600: Fix nonsensical implementation of computeKnownBits for BFE

This was resulting in invalid simplifications of sdiv

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219953 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDelete -std-compile-opts.
Rafael Espindola [Thu, 16 Oct 2014 20:00:02 +0000 (20:00 +0000)]
Delete -std-compile-opts.

These days -std-compile-opts was just a silly alias for -O3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219951 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAllow call-slop optzn for destinations with a suitable dereferenceable attribute
Bjorn Steinbrink [Thu, 16 Oct 2014 19:43:08 +0000 (19:43 +0000)]
Allow call-slop optzn for destinations with a suitable dereferenceable attribute

Currently, call slot optimization requires that if the destination is an
argument, the argument has the sret attribute. This is to ensure that
the memory access won't trap. In addition to sret, we can also allow the
optimization to happen for arguments that have the new dereferenceable
attribute, which gives the same guarantee.

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5832

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219950 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix lang-ref doc bug: s/icmp lt/icmp slt/
Jonathan Roelofs [Thu, 16 Oct 2014 19:28:10 +0000 (19:28 +0000)]
Fix lang-ref doc bug: s/icmp lt/icmp slt/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219947 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[llvm-objdump] Fix -private-headers for mach-o to print all LC_*_DYLIB variants
Nick Kledzik [Thu, 16 Oct 2014 18:58:20 +0000 (18:58 +0000)]
[llvm-objdump] Fix -private-headers for mach-o to print all LC_*_DYLIB variants

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219945 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agofold: sqrt(x * x * y) -> fabs(x) * sqrt(y)
Sanjay Patel [Thu, 16 Oct 2014 18:48:17 +0000 (18:48 +0000)]
fold: sqrt(x * x * y) -> fabs(x) * sqrt(y)

If a square root call has an FP multiplication argument that can be reassociated,
then we can hoist a repeated factor out of the square root call and into a fabs().

In the simplest case, this:

   y = sqrt(x * x);

becomes this:

   y = fabs(x);

This patch relies on an earlier optimization in instcombine or reassociate to put the
multiplication tree into a canonical form, so we don't have to search over
every permutation of the multiplication tree.

Because there are no IR-level FastMathFlags for intrinsics (PR21290), we have to
use function-level attributes to do this optimization. This needs to be fixed
for both the intrinsics and in the backend.

Differential Revision: http://reviews.llvm.org/D5787

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219944 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AArch64] Fix miscompile of sdiv-by-power-of-2.
Juergen Ributzka [Thu, 16 Oct 2014 16:41:15 +0000 (16:41 +0000)]
[AArch64] Fix miscompile of sdiv-by-power-of-2.

When the constant divisor was larger than 32bits, then the optimized code
generated for the AArch64 backend would emit the wrong code, because the shift
was defined as a shift of a 32bit constant '(1<<Lg2(divisor))' and we would
loose the upper 32bits.

This fixes rdar://problem/18678801.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219934 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[mips] Account for endianess when expanding BuildPairF64/ExtractElementF64 nodes.
Vasileios Kalintiris [Thu, 16 Oct 2014 15:41:51 +0000 (15:41 +0000)]
[mips] Account for endianess when expanding BuildPairF64/ExtractElementF64 nodes.

In order to support big endian targets for the BuildPairF64 nodes we
just need to swap the low/high pair registers. Additionally, for the
ExtractElementF64 nodes we have to calculate the correct stack offset
with respect to the node's register/operand that we want to extract.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5753

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219931 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[mips] Marked the DI/EI instruction aliases as MIPS32r2
Vasileios Kalintiris [Thu, 16 Oct 2014 15:23:52 +0000 (15:23 +0000)]
[mips] Marked the DI/EI instruction aliases as MIPS32r2

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5751

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219927 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoTest commit access: remove extra new line at the end of file
Vasileios Kalintiris [Thu, 16 Oct 2014 14:37:00 +0000 (14:37 +0000)]
Test commit access: remove extra new line at the end of file

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219925 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd missing header guard.
Benjamin Kramer [Thu, 16 Oct 2014 10:10:07 +0000 (10:10 +0000)]
Add missing header guard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219922 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReapply r219832 - InstCombine: Narrow switch instructions using known bits.
Akira Hatanaka [Thu, 16 Oct 2014 06:00:46 +0000 (06:00 +0000)]
Reapply r219832 - InstCombine: Narrow switch instructions using known bits.

The code committed in r219832 asserted when it attempted to shrink a switch
statement whose type was larger than 64-bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219902 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoTRE: make TRE a bit more aggressive
Saleem Abdulrasool [Thu, 16 Oct 2014 03:27:30 +0000 (03:27 +0000)]
TRE: make TRE a bit more aggressive

Make tail recursion elimination a bit more aggressive.  This allows us to get
tail recursion on functions that are just branches to a different function.  The
fact that the function takes a byval argument does not restrict it from being
optimised into just a tail call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219899 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert r219832.
Akira Hatanaka [Thu, 16 Oct 2014 01:17:02 +0000 (01:17 +0000)]
Revert r219832.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219884 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[LVI] Add some additional comments about caching and context instructions
Hal Finkel [Thu, 16 Oct 2014 00:40:05 +0000 (00:40 +0000)]
[LVI] Add some additional comments about caching and context instructions

Philip Reames and I had a long conversation about this, mostly because it is
not obvious why the current logic is correct. Hopefully, these comments will
prevent such confusion in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219882 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agollvm/Support/Options.h: Use \tparam. [-Wdocumentation]
NAKAMURA Takumi [Thu, 16 Oct 2014 00:14:57 +0000 (00:14 +0000)]
llvm/Support/Options.h: Use \tparam. [-Wdocumentation]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219881 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Remove dead function
Matt Arsenault [Thu, 16 Oct 2014 00:08:09 +0000 (00:08 +0000)]
R600: Remove dead function

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219879 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert "r219834 - Teach ScalarEvolution to sharpen range information"
Sanjoy Das [Wed, 15 Oct 2014 23:46:04 +0000 (23:46 +0000)]
Revert "r219834 - Teach ScalarEvolution to sharpen range information"

This change breaks the asan buildbots:

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219878 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoPreserve non-byval pointer alignment attributes using @llvm.assume when inlining
Hal Finkel [Wed, 15 Oct 2014 23:44:41 +0000 (23:44 +0000)]
Preserve non-byval pointer alignment attributes using @llvm.assume when inlining

For pointer-typed function arguments, enhanced alignment can be asserted using
the 'align' attribute. When inlining, if this enhanced alignment information is
not otherwise available, preserve it using @llvm.assume-based alignment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219876 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd CreateAlignmentAssumption to IRBuilder
Hal Finkel [Wed, 15 Oct 2014 23:44:22 +0000 (23:44 +0000)]
Add CreateAlignmentAssumption to IRBuilder

Clang CodeGen had a utility function for creating pointer alignment assumptions
using the @llvm.assume intrinsic. This functionality will also be needed by the
inliner (to preserve function-argument alignment attributes when inlining), so
this moves the utility function into IRBuilder where it can be used both by
Clang CodeGen and also other LLVM-level code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219875 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Add DQ subvector inserts
Adam Nemet [Wed, 15 Oct 2014 23:42:17 +0000 (23:42 +0000)]
[AVX512] Add DQ subvector inserts

In AVX512f we support 64x2 and 32x8 inserts via matching them to 32x4 and 64x4
respectively.  These are matched by "Alt" Pat<>'s (Alt stands for alternative

Since DQ has native support for these intructions, I peeled off the non-"Alt"
part of the baseclass into vinsert_for_size_no_alt. The DQ instructions are
derived from this multiclass.  The "Alt" Pat<>'s are disabled with DQ.

Fixes <rdar://problem/18426089>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219874 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Add SKX testing to avx512-insert-extract.ll
Adam Nemet [Wed, 15 Oct 2014 23:42:14 +0000 (23:42 +0000)]
[AVX512] Add SKX testing to avx512-insert-extract.ll

This is in preparation to adding DQ subvector inserts to this testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219873 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Fix test to produce a defined value
Adam Nemet [Wed, 15 Oct 2014 23:42:11 +0000 (23:42 +0000)]
[AVX512] Fix test to produce a defined value

We're inserting into a 8 wide vector, so the index should be < 8.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219872 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Two new attributes in X86VectorVTInfo for subvector insert
Adam Nemet [Wed, 15 Oct 2014 23:42:09 +0000 (23:42 +0000)]
[AVX512] Two new attributes in X86VectorVTInfo for subvector insert

The new attributes are NumElts and the CD8TupleForm.  This prepares the code
to enable x8 and x2 inserts.

NFC, no change in X86.td.expanded except for the new attributes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219871 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Rename arg from Opcode32/64 to Opcode128/256 in vinsert_for_size
Adam Nemet [Wed, 15 Oct 2014 23:42:04 +0000 (23:42 +0000)]
[AVX512] Rename arg from Opcode32/64 to Opcode128/256 in vinsert_for_size

It's the W bit that selects between 32 or 64 elt type and not the opcode.  The
opcode selects between the width of the insert (128 or 256).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219870 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Remove unnecessary part of computeKnownBitsForTargetNode
Matt Arsenault [Wed, 15 Oct 2014 23:37:49 +0000 (23:37 +0000)]
R600: Remove unnecessary part of computeKnownBitsForTargetNode

Zero-width BFEs are combined away already, so there's no point in
handling them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219868 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMove variable down to use
Matt Arsenault [Wed, 15 Oct 2014 23:37:42 +0000 (23:37 +0000)]
Move variable down to use

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219867 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd MachOObjectFile::getUuid()
Alexander Potapenko [Wed, 15 Oct 2014 23:35:45 +0000 (23:35 +0000)]
Add MachOObjectFile::getUuid()

This CL introduces MachOObjectFile::getUuid(). This function returns an ArrayRef to the object file's UUID, or an empty ArrayRef if the object file doesn't contain an LC_UUID load command.
The new function is gonna be used by llvm-symbolizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219866 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUpdating documentation based on my change to remove the template disambiguation.
Chris Bieneman [Wed, 15 Oct 2014 23:11:40 +0000 (23:11 +0000)]
Updating documentation based on my change to remove the template disambiguation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219862 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFixing the build failure due to compiler warnings and unnecessary disambiguation.
Chris Bieneman [Wed, 15 Oct 2014 23:11:35 +0000 (23:11 +0000)]
Fixing the build failure due to compiler warnings and unnecessary disambiguation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219861 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDefining a new API for debug options that doesn't rely on static global cl::opts.
Chris Bieneman [Wed, 15 Oct 2014 21:54:35 +0000 (21:54 +0000)]
Defining a new API for debug options that doesn't rely on static global cl::opts.

This is based on the discussions from the LLVMDev thread:

Reviewers: chandlerc

Reviewed By: chandlerc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5389

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219854 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Fix bug where immediates were being used in DS addr operands
Tom Stellard [Wed, 15 Oct 2014 21:08:59 +0000 (21:08 +0000)]
R600/SI: Fix bug where immediates were being used in DS addr operands

The SelectDS1Addr1Offset complex pattern always tries to store constant
lds pointers in the offset operand and store a zero value in the addr operand.
Since the addr operand does not accept immediates, the zero value
needs to first be copied to a register.

This newly created zero value will not go through normal instruction
selection, so we need to manually insert a V_MOV_B32_e32 in the complex

This bug was hidden by the fact that if there was another zero value
in the DAG that had not been selected yet, then the CSE done by the DAG
would use the unselected node for the addr operand rather than the one
that was just created.  This would lead to the zero value being selected
and the DAG automatically inserting a V_MOV_B32_e32 instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219848 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAvoid caching the MachineFunction, we don't use it outside of
Eric Christopher [Wed, 15 Oct 2014 21:06:25 +0000 (21:06 +0000)]
Avoid caching the MachineFunction, we don't use it outside of

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219847 91177308-0d34-0410-b5e6-96231b3b80d8

Sid Manning [Wed, 15 Oct 2014 20:41:17 +0000 (20:41 +0000)]

This original fix for the build break was correct.  LLVM_ATTRIBUTE_USED
removes the warning message because it keeps the function in the object
file.  LLVM_ATTRIBUTE_UNUSED indicates that it may or may not be used
depending on build settings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219846 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoIR: Move NumOperands from User to Value, NFC
Duncan P. N. Exon Smith [Wed, 15 Oct 2014 20:39:05 +0000 (20:39 +0000)]
IR: Move NumOperands from User to Value, NFC

Store `User::NumOperands` (and `MDNode::NumOperands`) in `Value`.

On 64-bit host architectures, this reduces `sizeof(User)` and all
subclasses by 8, and has no effect on `sizeof(Value)` (or, incidentally,
on `sizeof(MDNode)`).

On 32-bit host architectures, this increases `sizeof(Value)` by 4.
However, it has no effect on `sizeof(User)` and `sizeof(MDNode)`, so the
only concrete subclasses of `Value` that actually see the increase are
`BasicBlock`, `Argument`, `InlineAsm`, and `MDString`.  Moreover, I'll
be shocked and confused if this causes a tangible memory regression.

This has no functionality change (other than memory footprint).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219845 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoIR: Cleanup comments for Value, User, and MDNode
Duncan P. N. Exon Smith [Wed, 15 Oct 2014 20:28:31 +0000 (20:28 +0000)]
IR: Cleanup comments for Value, User, and MDNode

A follow-up commit will modify the memory-layout of `Value`, `User`, and
`MDNode`.  First fix the comments to be doxygen-friendly (and to follow
the coding standards).

  - Use "\brief" instead of "repeatedName -".
  - Add a brief intro where it was missing.
  - Remove duplicated comments from source files (and a couple of
    noisy/trivial comments altogether).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219844 91177308-0d34-0410-b5e6-96231b3b80d8

Sid Manning [Wed, 15 Oct 2014 19:32:52 +0000 (19:32 +0000)]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219837 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAllow forward references to section symbols.
Rafael Espindola [Wed, 15 Oct 2014 19:30:18 +0000 (19:30 +0000)]
Allow forward references to section symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219835 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoTeach ScalarEvolution to sharpen range information.
Sanjoy Das [Wed, 15 Oct 2014 19:25:28 +0000 (19:25 +0000)]
Teach ScalarEvolution to sharpen range information.

If x is known to have the range [a, b) in a loop predicated by (icmp
ne x, a), its range can be sharpened to [a + 1, b).  Get
ScalarEvolution and hence IndVars to exploit this fact.

This change triggers an optimization to widen-loop-comp.ll, so it had
to be edited to get it to pass.

phabricator: http://reviews.llvm.org/D5639

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219834 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd LLVM_ATTRIBUTE_UNUSED to function currently just used in an assert
Sid Manning [Wed, 15 Oct 2014 19:24:14 +0000 (19:24 +0000)]
Add LLVM_ATTRIBUTE_UNUSED to function currently just used in an assert

Fixes break when -Wunused-function is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219833 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoInstCombine: Narrow switch instructions using known bits.
Akira Hatanaka [Wed, 15 Oct 2014 19:05:50 +0000 (19:05 +0000)]
InstCombine: Narrow switch instructions using known bits.

Truncate the operands of a switch instruction to a narrower type if the upper
bits are known to be all ones or zeros.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219832 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReapply "[FastISel][AArch64] Add custom lowering for GEPs."
Juergen Ributzka [Wed, 15 Oct 2014 18:58:07 +0000 (18:58 +0000)]
Reapply "[FastISel][AArch64] Add custom lowering for GEPs."

This is mostly a copy of the existing FastISel GEP code, but we have to
duplicate it for AArch64, because otherwise we would bail out even for simple
cases. This is because the standard fastEmit functions don't cover MUL at all
and ADD is lowered very inefficientily.

The original commit had a bug in the add emit logic, which has been fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219831 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[FastISel][AArch64] Factor out add with immediate emission into a helper function...
Juergen Ributzka [Wed, 15 Oct 2014 18:58:02 +0000 (18:58 +0000)]
[FastISel][AArch64] Factor out add with immediate emission into a helper function. NFC.

Simplify add with immediate emission by factoring it out into a helper function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219830 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoCorrectly handle references to section symbols.
Rafael Espindola [Wed, 15 Oct 2014 18:55:30 +0000 (18:55 +0000)]
Correctly handle references to section symbols.

When processing assembly like

.long .text

we were creating a new undefined symbol .text. GAS on the other hand would
handle that as a reference to the .text section.

This patch implements that by creating the section symbols earlier so that
they are visible during asm parsing.

The patch also updates llvm-readobj to print the symbol number in the relocation
dump so that the test can differentiate between two sections with the same name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219829 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoEnable the instruction printer in HexagonMCTargetDesc
Sid Manning [Wed, 15 Oct 2014 18:27:40 +0000 (18:27 +0000)]
Enable the instruction printer in HexagonMCTargetDesc

This adds the MCInstPrinter to the LLVMHexagonDesc library and removes
the dependency LLVMHexagonAsmPrinter had on LLVMHexagonDesc. This is
a prerequisite needed by the disassembler.

Phabricator Revision: http://reviews.llvm.org/D5734

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219826 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Also try to use 0 base for misaligned 8-byte DS loads.
Matt Arsenault [Wed, 15 Oct 2014 18:06:43 +0000 (18:06 +0000)]
R600/SI: Also try to use 0 base for misaligned 8-byte DS loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219823 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Fix miscompiles when BFE has multiple uses
Matt Arsenault [Wed, 15 Oct 2014 17:58:34 +0000 (17:58 +0000)]
R600: Fix miscompiles when BFE has multiple uses

SimplifyDemandedBits would break the other uses of the operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219819 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agocorrect const-ness with auto and dyn_cast
Sanjay Patel [Wed, 15 Oct 2014 17:45:13 +0000 (17:45 +0000)]
correct const-ness with auto and dyn_cast

1. Use const with autos.
2. Don't bother with explicit const in cast ops because they do it automagically.

Thanks, David B. / Aaron B. / Reid K.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219817 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SLPVectorize] Basic ephemeral-value awareness
Hal Finkel [Wed, 15 Oct 2014 17:35:01 +0000 (17:35 +0000)]
[SLPVectorize] Basic ephemeral-value awareness

The SLP vectorizer should not vectorize ephemeral values. These are used to
express information to the optimizer, and vectorizing them does not lead to
faster code (because the ephemeral values are dropped prior to code generation,
vectorized or not), and obscures the information the instructions are
attempting to communicate (the logic that interprets the arguments to
@llvm.assume generically does not understand vectorized conditions).

Also, uses by ephemeral values are free (because they, and the necessary
extractelement instructions, will be dropped prior to code generation).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219816 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoTreat the WorkSet used to find ephemeral values as double-ended
Hal Finkel [Wed, 15 Oct 2014 17:34:48 +0000 (17:34 +0000)]
Treat the WorkSet used to find ephemeral values as double-ended

We need to make sure that we visit all operands of an instruction before moving
deeper in the operand graph. We had been pushing operands onto the back of the work
set, and popping them off the back as well, meaning that we might visit an
instruction before visiting all of its uses that sit in between it and the call
to @llvm.assume.

To provide an explicit example, given the following:
  %q0 = extractelement <4 x float> %rd, i32 0
  %q1 = extractelement <4 x float> %rd, i32 1
  %q2 = extractelement <4 x float> %rd, i32 2
  %q3 = extractelement <4 x float> %rd, i32 3
  %q4 = fadd float %q0, %q1
  %q5 = fadd float %q2, %q3
  %q6 = fadd float %q4, %q5
  %qi = fcmp olt float %q6, %q5
  call void @llvm.assume(i1 %qi)

%q5 is used by both %qi and %q6. When we visit %qi, it will be marked as
ephemeral, and we'll queue %q6 and %q5. %q6 will be marked as ephemeral and
we'll queue %q4 and %q5. Under the old system, we'd then visit %q4, which
would become ephemeral, %q1 and then %q0, which would become ephemeral as
well, and now we have a problem. We'd visit %rd, but it would not be marked as
ephemeral because we've not yet visited %q2 and %q3 (because we've not yet
visited %q5).

This will be covered by a test case in a follow-up commit that enables
ephemeral-value awareness in the SLP vectorizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219815 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[MC] Make bundle alignment mode setting idempotent and support nested bundles
Derek Schuff [Wed, 15 Oct 2014 17:10:04 +0000 (17:10 +0000)]
[MC] Make bundle alignment mode setting idempotent and support nested bundles

Currently an error is thrown if bundle alignment mode is set more than once
per module (either via the API or the .bundle_align_mode directive). This
change allows setting it multiple times as long as the alignment doesn't

Also nested bundle_lock groups are currently not allowed. This change allows
them, with the effect that the group stays open until all nests are exited,
and if any of the bundle_lock directives has the align_to_end flag, the
group becomes align_to_end.

These changes make the bundle aligment simpler to use in the compiler, and
also better match the corresponding support in GNU as.

Reviewers: jvoung, eliben

Differential Revision: http://reviews.llvm.org/D5801

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219811 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDI: Make comments "brief"-er, NFC
Duncan P. N. Exon Smith [Wed, 15 Oct 2014 17:01:28 +0000 (17:01 +0000)]
DI: Make comments "brief"-er, NFC

Follow-up to r219801.  Post-commit review pointed out that all comments
require a `\brief` description [1], so I converted many and recrafted a
few to be briefer or to include a brief intro.  (If I'm going to clean
them up, I should do it right!)

[1]: http://llvm.org/docs/CodingStandards.html#doxygen-use-in-documentation-comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219808 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUse 'auto' for easier reading; no functional change intended.
Sanjay Patel [Wed, 15 Oct 2014 16:21:37 +0000 (16:21 +0000)]
Use 'auto' for easier reading; no functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219804 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoremove function names from comments; NFC
Sanjay Patel [Wed, 15 Oct 2014 16:20:45 +0000 (16:20 +0000)]
remove function names from comments; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219803 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDI: Cleanup comments, NFC
Duncan P. N. Exon Smith [Wed, 15 Oct 2014 16:15:15 +0000 (16:15 +0000)]
DI: Cleanup comments, NFC

A number of comment cleanups:

  - Remove duplicated function and class names from comments.

  - Remove duplicated comments from source file (some of which were

  - Move any unduplicated comments from source file to header.

  - Remove some noisy comments entirely (e.g., a comment for
    `DIDescriptor::print()` saying "print descriptor" just gets in the
    way of reading the code).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219801 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSimplify handling of --noexecstack by using getNonexecutableStackSection.
Rafael Espindola [Wed, 15 Oct 2014 16:12:52 +0000 (16:12 +0000)]
Simplify handling of --noexecstack by using getNonexecutableStackSection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219799 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDI: Use a `DenseMap` instead of named metadata, NFC
Duncan P. N. Exon Smith [Wed, 15 Oct 2014 16:11:41 +0000 (16:11 +0000)]
DI: Use a `DenseMap` instead of named metadata, NFC

Remove a strange round-trip through named metadata to assign preserved
local variables to their subprograms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219798 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMove getNonexecutableStackSection up to the base ELF class.
Rafael Espindola [Wed, 15 Oct 2014 15:44:16 +0000 (15:44 +0000)]
Move getNonexecutableStackSection up to the base ELF class.

The .note.GNU-stack section is not SystemZ/X86 specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219796 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Use existing variable
Matt Arsenault [Wed, 15 Oct 2014 05:07:00 +0000 (05:07 +0000)]
R600: Use existing variable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219778 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Remove outdated comment
Matt Arsenault [Wed, 15 Oct 2014 05:06:57 +0000 (05:06 +0000)]
R600: Remove outdated comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219777 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert "[FastISel][AArch64] Add custom lowering for GEPs."
Juergen Ributzka [Wed, 15 Oct 2014 04:55:48 +0000 (04:55 +0000)]
Revert "[FastISel][AArch64] Add custom lowering for GEPs."

This breaks our internal build bots. Reverting it to get the bots green again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219776 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[MachineSink] Use the real post dominator tree
Jingyue Wu [Wed, 15 Oct 2014 03:27:43 +0000 (03:27 +0000)]
[MachineSink] Use the real post dominator tree

Fixes a FIXME in MachineSinking. Instead of using the simple heuristics in
isPostDominatedBy, use the real MachinePostDominatorTree and MachineLoopInfo.
The old heuristics caused instructions to sink unnecessarily, and might create
register pressure.

This is the second try of the fix. The first one (D4814) caused a performance
regression due to failing to sink instructions out of loops (PR21115). This
patch fixes PR21115 by sinking an instruction from a deeper loop to a shallower
one regardless of whether the target block post-dominates the source.

Thanks Alexey Volkov for reporting PR21115!

Test Plan:
Added a NVPTX codegen test to verify that our change prevents the backend from
over-sinking. It also shows the unnecessary register pressure caused by

Added an X86 test to verify we can sink instructions out of loops regardless of
the dominance relationship. This test is reduced from Alexey's test in PR21115.

Updated an affected test in X86.

Also ran SPEC CINT2006 and llvm-test-suite for compilation time and runtime
performance. Results are attached separately in the review thread.

Reviewers: Jiangning, resistor, hfinkel

Reviewed By: hfinkel

Subscribers: hfinkel, bruno, volkalexey, llvm-commits, meheff, eliben, jholewinski

Differential Revision: http://reviews.llvm.org/D5633

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219773 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoARM: drop check for triple that's no longer used.
Tim Northover [Wed, 15 Oct 2014 01:05:01 +0000 (01:05 +0000)]
ARM: drop check for triple that's no longer used.

Early attempts to support AAPCS bare metal MachO targets based the decision on
the CPU being compiled for. This was not a particularly great idea and we've
got a better option now, but this check remained.

No functional change for any target we care about.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219767 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemove unused variable.
Eric Christopher [Wed, 15 Oct 2014 00:09:07 +0000 (00:09 +0000)]
Remove unused variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219750 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoNo need to cache this unused variable.
Eric Christopher [Tue, 14 Oct 2014 23:58:51 +0000 (23:58 +0000)]
No need to cache this unused variable.

Patch by Ehsan Akhgari.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219749 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AArch64] Wrong CC access in CSINC-conditional branch sequence
Gerolf Hoflehner [Tue, 14 Oct 2014 23:55:00 +0000 (23:55 +0000)]
[AArch64] Wrong CC access in CSINC-conditional branch sequence

This is a follow up to commit r219742. It removes the CCInMI variable
and accesses the CC in CSCINC directly. In the case of a conditional
branch accessing the CC with CCInMI was wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219748 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[llvm-objdump] Update error message and add test case for mach-o file with bad librar...
Nick Kledzik [Tue, 14 Oct 2014 23:29:38 +0000 (23:29 +0000)]
[llvm-objdump] Update error message and add test case for mach-o file with bad library ordinals

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219746 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AAarch64] Optimize CSINC-branch sequence
Gerolf Hoflehner [Tue, 14 Oct 2014 23:07:53 +0000 (23:07 +0000)]
[AAarch64] Optimize CSINC-branch sequence

Peephole optimization that generates a single conditional branch
for csinc-branch sequences like in the examples below. This is
possible when the csinc sets or clears a register based on a condition
code and the branch checks that register. Also the condition
code may not be modified between the csinc and the original branch.


1. Convert csinc w9, wzr, wzr, <CC>;tbnz w9, #0, 0x44
   to b.<invCC>

2. Convert csinc w9, wzr, wzr, <CC>; tbz w9, #0, 0x44
   to b.<CC>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219742 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[LoopVectorize] Ignore @llvm.assume for cost estimates and legality
Hal Finkel [Tue, 14 Oct 2014 22:59:49 +0000 (22:59 +0000)]
[LoopVectorize] Ignore @llvm.assume for cost estimates and legality

A few minor changes to prevent @llvm.assume from interfering with loop
vectorization. First, treat @llvm.assume like the lifetime intrinsics, which
are scalarized (but don't otherwise interfere with the legality checking).
Second, ignore the cost of ephemeral instructions in the loop (these will go
away anyway during CodeGen).

Alignment assumptions and other uses of @llvm.assume can often end up inside of
loops that should be vectorized (this is not uncommon for assumptions generated
by __attribute__((align_value(n))), for example).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219741 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMC, COFF: Make bigobj test compatible with python3
David Majnemer [Tue, 14 Oct 2014 22:35:11 +0000 (22:35 +0000)]
MC, COFF: Make bigobj test compatible with python3

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219739 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86][SSE] pslldq/psrldq shuffle mask decodes
Simon Pilgrim [Tue, 14 Oct 2014 22:31:34 +0000 (22:31 +0000)]
[X86][SSE] pslldq/psrldq shuffle mask decodes

Patch to provide shuffle decodes and asm comments for the sse pslldq/psrldq SSE2/AVX2 byte shift instructions.

Differential Revision: http://reviews.llvm.org/D5598

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219738 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMC: Rewrite bigobj test in python
David Majnemer [Tue, 14 Oct 2014 22:26:49 +0000 (22:26 +0000)]
MC: Rewrite bigobj test in python

This makes the test easier to work with.  No functionality change

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219737 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoARM: remove ARM/Thumb distinction for preferred alignment.
Tim Northover [Tue, 14 Oct 2014 22:12:17 +0000 (22:12 +0000)]
ARM: remove ARM/Thumb distinction for preferred alignment.

Thumb1 has legitimate reasons for preferring 32-bit alignment of types
i1/i8/i16, since the 16-bit encoding of "add rD, sp, #imm" requires #imm to be
a multiple of 4. However, this is a trade-off betweem code size and RAM usage;
the DataLayout string is not the best place to represent it even if desired.

So this patch removes the extra Thumb requirements, hopefully making ARM and
Thumb completely compatible in this respect.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219734 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoARM: allow misaligned local variables in Thumb1 mode.
Tim Northover [Tue, 14 Oct 2014 22:12:14 +0000 (22:12 +0000)]
ARM: allow misaligned local variables in Thumb1 mode.

There's no hard requirement on LLVM to align local variable to 32-bits, so the
Thumb1 frame handling needs to be able to deal with variables that are only
naturally aligned without falling over.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219733 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd a test for writing COFF BigObj
David Majnemer [Tue, 14 Oct 2014 21:47:53 +0000 (21:47 +0000)]
Add a test for writing COFF BigObj

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219729 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[FastISel][AArch64] Add custom lowering for GEPs.
Juergen Ributzka [Tue, 14 Oct 2014 21:41:23 +0000 (21:41 +0000)]
[FastISel][AArch64] Add custom lowering for GEPs.

This is mostly a copy of the existing FastISel GEP code, but on AArch64 we bail
out even for simple cases, because the standard fastEmit functions don't cover
MUL and ADD is lowered inefficientily.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219726 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86 asm] allow fwait alias in both At&t and Intel modes (PR21208)
Hans Wennborg [Tue, 14 Oct 2014 21:41:17 +0000 (21:41 +0000)]
[x86 asm] allow fwait alias in both At&t and Intel modes (PR21208)

Differential Revision: http://reviews.llvm.org/D5741

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219725 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoARM: set preferred aggregate alignment to 32 universally.
Tim Northover [Tue, 14 Oct 2014 20:57:26 +0000 (20:57 +0000)]
ARM: set preferred aggregate alignment to 32 universally.

Before, ARM and Thumb mode code had different preferred alignments, which could
lead to some rather unexpected results. There's justification for reducing it
from the default 64-bits (wasted space), but I don't think there is for going
below 32-bits.

There's no actual ABI change here, just to reassure people.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219719 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[CFL-AA] CFL-AA should not assert on an va_arg instruction
Hal Finkel [Tue, 14 Oct 2014 20:51:26 +0000 (20:51 +0000)]
[CFL-AA] CFL-AA should not assert on an va_arg instruction

The CFL-AA implementation was missing a visit* routine for va_arg instructions,
causing it to assert when run on a function that had one. For now, handle these
in a conservative way.

Fixes PR20954.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219718 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoOptimize away fabs() calls when input is squared (known positive).
Sanjay Patel [Tue, 14 Oct 2014 20:43:11 +0000 (20:43 +0000)]
Optimize away fabs() calls when input is squared (known positive).

Eliminate library calls and intrinsic calls to fabs when the input
is a squared value.

Note that no unsafe-math / fast-math assumptions are needed for
this optimization.

Differential Revision: http://reviews.llvm.org/D5777

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219717 91177308-0d34-0410-b5e6-96231b3b80d8