Fix PR2076. CodeGenPrepare now sinks address computation for inline asm memory
operands into inline asm block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47589 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor inline asm constraint matching code out of SDIsel into TargetLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47587 91177308-0d34-0410-b5e6-96231b3b80d8

Remove debugging help.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47585 91177308-0d34-0410-b5e6-96231b3b80d8

test svn commit capability

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47584 91177308-0d34-0410-b5e6-96231b3b80d8

Update bitcode reader and writer to handle multiple return values.
Take 2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47583 91177308-0d34-0410-b5e6-96231b3b80d8

Pass const vectors by reference.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47577 91177308-0d34-0410-b5e6-96231b3b80d8

Add missing include (for ptrdiff_t).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47576 91177308-0d34-0410-b5e6-96231b3b80d8

Revert the assert for MUL_LOHI with an unused high result; Chris
pointed out that this isn't correct at -O0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47575 91177308-0d34-0410-b5e6-96231b3b80d8

when making bytecode modules, link as library

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47574 91177308-0d34-0410-b5e6-96231b3b80d8

Revise previous patch per review.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47573 91177308-0d34-0410-b5e6-96231b3b80d8

Factor the assert for indexed loads/stores out of LoadSDNode
and StoreSDNode into LSBaseSDNode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47570 91177308-0d34-0410-b5e6-96231b3b80d8

Add an assert to verify that we don't see an
{S,U}MUL_LOHI with an unused high value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47569 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the hack that turned an {S,U}MUL_LOHI with an unused high
result into a MUL late in the X86 codegen process. ISD::MUL is
once again Legal on X86, so this is no longer needed. And, the
hack was suboptimal; see PR1874 for details.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47567 91177308-0d34-0410-b5e6-96231b3b80d8

Make some static variables const.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47566 91177308-0d34-0410-b5e6-96231b3b80d8

add an assertion to catch a null PATypeHolder, patch by Erick Tryzelaar

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47563 91177308-0d34-0410-b5e6-96231b3b80d8

Convert MaskedValueIsZero and all its users to use APInt. Also add
a SignBitIsZero function to simplify a common use case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47561 91177308-0d34-0410-b5e6-96231b3b80d8

add LSBaseSDNode::getOffset at Dan's request.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47558 91177308-0d34-0410-b5e6-96231b3b80d8

All remat'ed loads cannot be folded into two-address code. Not just argument loads. This change doesn't really have any impact on codegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47557 91177308-0d34-0410-b5e6-96231b3b80d8

prune #includes, fit in 80 cols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47556 91177308-0d34-0410-b5e6-96231b3b80d8

make this self contained.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47555 91177308-0d34-0410-b5e6-96231b3b80d8

Expand removal of MMX memory copies to allow 1 level
of TokenFactor underneath chain (seems to be enough)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47554 91177308-0d34-0410-b5e6-96231b3b80d8

Add a new method to SDNode/SDOperand named getValueSizeInBits
that combines getValueType and MVT::getSizeInBits, since this
occurrs frequently.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47552 91177308-0d34-0410-b5e6-96231b3b80d8

In debug builds check that the key property holds: all
result and operand types are legal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47546 91177308-0d34-0410-b5e6-96231b3b80d8

Correctly determine whether a argument load can be folded into its uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47545 91177308-0d34-0410-b5e6-96231b3b80d8

Fix an issue where GVN was performing the return slot optimization when it was
not safe.  This is fixed by more aggressively checking that the return slot is
not used elsewhere in the function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47544 91177308-0d34-0410-b5e6-96231b3b80d8

Temporarily reverting 46959.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47542 91177308-0d34-0410-b5e6-96231b3b80d8

Fix an issue where GVN would try to use an instruction before its definition when performing return slot optimization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47541 91177308-0d34-0410-b5e6-96231b3b80d8

Add support to LegalizeTypes for building legal vectors
out of illegal elements (BUILD_VECTOR).  Uses and beefs
up BUILD_PAIR, though it didn't really have to.  Like
most of LegalizeTypes, does not support soft-float.
This cures all "make check" vector building failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47537 91177308-0d34-0410-b5e6-96231b3b80d8

Some platforms use the same name for 32-bit and 64-bit registers (like
%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47534 91177308-0d34-0410-b5e6-96231b3b80d8

Backing out r47521 for now. This has broken a number of tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47533 91177308-0d34-0410-b5e6-96231b3b80d8

Merge current work back to tree to minimize diffs and drift. Major highlights
for CellSPU modifications:

- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
  esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
  rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
  is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
  compiles and generates the right code. More work still needs to be done.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47532 91177308-0d34-0410-b5e6-96231b3b80d8

Testcase for Revision 47478.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47531 91177308-0d34-0410-b5e6-96231b3b80d8

Rematerialization logic was overly conservative when it comes to loads from fixed stack slots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47529 91177308-0d34-0410-b5e6-96231b3b80d8

Update test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47527 91177308-0d34-0410-b5e6-96231b3b80d8

If remating a machine instr with virtual register operand, make sure the vr is avaliable at all uses regardless of whether it would be folded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47526 91177308-0d34-0410-b5e6-96231b3b80d8

Remat of pic loads are now on by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47525 91177308-0d34-0410-b5e6-96231b3b80d8

Turning on remat of pic loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47524 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bug that caused opt and other tools to silently ignore
invalid command-line options.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47523 91177308-0d34-0410-b5e6-96231b3b80d8

No need recognize load from a fixed argument slot as re-materializable. LiveIntervalAnalysis already handles it as a special case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47522 91177308-0d34-0410-b5e6-96231b3b80d8

Properly read and write bitcodes for multiple return values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47521 91177308-0d34-0410-b5e6-96231b3b80d8

Recognize loads of arguments as re-materializable first. Therefore if isReallyTriviallyReMaterializable() returns true it doesn't confuse it as a "normal" re-materializable instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47520 91177308-0d34-0410-b5e6-96231b3b80d8

Regenerate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47519 91177308-0d34-0410-b5e6-96231b3b80d8

Use isa check instead of getTypeID() check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47518 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed buffer overflow reported by Argiris Kirtzidis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47517 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unnecessary "inline" keywords.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47516 91177308-0d34-0410-b5e6-96231b3b80d8

print getresult operand and its type directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47514 91177308-0d34-0410-b5e6-96231b3b80d8

Really. Why doesn't every arch support MMX?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47513 91177308-0d34-0410-b5e6-96231b3b80d8

Use dyn_cast instead of isa + cast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47511 91177308-0d34-0410-b5e6-96231b3b80d8

Forgot this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47510 91177308-0d34-0410-b5e6-96231b3b80d8

Regenerate

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47509 91177308-0d34-0410-b5e6-96231b3b80d8

To support multiple return values, now ret instruction supports multiple operands instead of one aggregate operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47508 91177308-0d34-0410-b5e6-96231b3b80d8

Fix spill weight updating bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47507 91177308-0d34-0410-b5e6-96231b3b80d8

Split ParameterAttributes.h, putting the complicated
stuff into ParamAttrsList.h.  Per feedback from
ParamAttrs changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47504 91177308-0d34-0410-b5e6-96231b3b80d8

Improving wording.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47503 91177308-0d34-0410-b5e6-96231b3b80d8

Adding a note about IR generation to the LLVM FAQ.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47502 91177308-0d34-0410-b5e6-96231b3b80d8

Test case for PR2082.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47501 91177308-0d34-0410-b5e6-96231b3b80d8

Same isPhysRegAvailable bug as local register allocator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47500 91177308-0d34-0410-b5e6-96231b3b80d8

Really really bad local register allocator bug. On X86, it was never using ESI, EDI, and EBP because of a bug in RALocal::isPhysRegAvailable(). For example, when
it checks if ESI is available, it then looks at registers aliases to ESI. SIL is marked -2 (not allocatable) but isPhysRegAvailable() incorrectly assumes it is in use and returns false for ESI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47499 91177308-0d34-0410-b5e6-96231b3b80d8

Add debugging printfs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47496 91177308-0d34-0410-b5e6-96231b3b80d8

Regenerate

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47495 91177308-0d34-0410-b5e6-96231b3b80d8

Use SymbolicValueRef to parse getresult operand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47494 91177308-0d34-0410-b5e6-96231b3b80d8

Remove an invalid assertion now that there are implicit virtual register operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47493 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure reload of implicit uses are issued before remat's.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47492 91177308-0d34-0410-b5e6-96231b3b80d8

Add StripDeadPrototypes pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47488 91177308-0d34-0410-b5e6-96231b3b80d8

Generated files for 47484.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47485 91177308-0d34-0410-b5e6-96231b3b80d8

Pass alignment on ByVal parameters, from FE, all
the way through.  It is now used for codegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47484 91177308-0d34-0410-b5e6-96231b3b80d8

MMX vectors are passed 4-byte aligned.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47483 91177308-0d34-0410-b5e6-96231b3b80d8

Add smart refcounting pointer class to ADT back (known before as IntrusiveSPtr.h).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47482 91177308-0d34-0410-b5e6-96231b3b80d8

fix some bugs in tutorial, patch by Erick Tryzelaar

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47481 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak build for VC2008. Patch by Argiris Kirtzidis!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47480 91177308-0d34-0410-b5e6-96231b3b80d8

Provide __main hooks for cygwin & mingw32

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47479 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed a typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47478 91177308-0d34-0410-b5e6-96231b3b80d8

Allow re-materialization of pic load (controlled by -remat-pic-load for now).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47476 91177308-0d34-0410-b5e6-96231b3b80d8

Enable re-materialization of instructions which have virtual register operands if
the definition of the operand also reaches its uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47475 91177308-0d34-0410-b5e6-96231b3b80d8

copy mmx values from/to memory with GPRs on x86-32
instead of with mmx registers.  This horribleness is apparently
done by gcc to avoid having to insert emms in places that really
should have it.  This is the second half of rdar://5741668.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47474 91177308-0d34-0410-b5e6-96231b3b80d8

Print getresult instruction properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47473 91177308-0d34-0410-b5e6-96231b3b80d8

Print ret instruction that returns aggregates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47472 91177308-0d34-0410-b5e6-96231b3b80d8

Read and write getresult.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47471 91177308-0d34-0410-b5e6-96231b3b80d8

Start using GPR's to copy around mmx value instead of mmx regs.
GCC apparently does this, and code depends on not having to do
emms when this happens.  This is x86-64 only so far, second half
should handle x86-32.

rdar://5741668

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47470 91177308-0d34-0410-b5e6-96231b3b80d8

minor cleanups to LSBaseSDNode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47469 91177308-0d34-0410-b5e6-96231b3b80d8

Fix compiler warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47468 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a regression in 403.gcc and 186.crafty introduced in 47383. To test
that a value is >= 32, check that all of the high bits are zero, not
just one or more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47467 91177308-0d34-0410-b5e6-96231b3b80d8

print getresult instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47461 91177308-0d34-0410-b5e6-96231b3b80d8

Use isa<> instead of getTypeID() to check StructType.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47460 91177308-0d34-0410-b5e6-96231b3b80d8

A few minor updates, removing implemented stuff and adding a couple of
new things.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47458 91177308-0d34-0410-b5e6-96231b3b80d8

Make the clobber analysis a bit more smart: we only are careful about
early clobbers if the clobber list contains a *register* not some thing
like {memory}, {dirflag} etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47457 91177308-0d34-0410-b5e6-96231b3b80d8

Treat clobber operands like early clobbers: if we have
any, we force sdisel to do all regalloc for an asm.  This
leads to gross but correct codegen.

This fixes the rest of PR2078.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47454 91177308-0d34-0410-b5e6-96231b3b80d8

Clear PhysRegPartUse for the sub register as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47453 91177308-0d34-0410-b5e6-96231b3b80d8

Adjust the MaxAlignment for the special register scavenging spill slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47452 91177308-0d34-0410-b5e6-96231b3b80d8

Help testing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47448 91177308-0d34-0410-b5e6-96231b3b80d8

Change a C-style cast to const_cast, to avoid a -Wcast-qual warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47437 91177308-0d34-0410-b5e6-96231b3b80d8

Better names as per Evan's request

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47435 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify this code, no functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47434 91177308-0d34-0410-b5e6-96231b3b80d8

GlobalValues are Constants, remove redundant code. Also fix typo in a comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47433 91177308-0d34-0410-b5e6-96231b3b80d8

Remove llvm-upgrade and update tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47432 91177308-0d34-0410-b5e6-96231b3b80d8

Dan implemented one multiply issue.  Replace it with another. :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47431 91177308-0d34-0410-b5e6-96231b3b80d8

Atomic op support.  If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47430 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for matching mem operands.  This fixes PR1133, patch by
Eli Friedman.  This implements CodeGen/Generic/2008-02-20-MatchingMem.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47428 91177308-0d34-0410-b5e6-96231b3b80d8

testcase for PR1133

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47427 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a (harmless) but where vregs were added to the used reg lists for
inline asms.

Fix PR2078 by marking aliases of registers used when a register is
marked used.  This prevents EAX from being allocated when AX is listed
in the clobber set for the asm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47426 91177308-0d34-0410-b5e6-96231b3b80d8