7 years agoSelectionDAG switch lowering: use 'unsigned' to count destination popularity
Hans Wennborg [Tue, 16 Dec 2014 23:41:59 +0000 (23:41 +0000)]
SelectionDAG switch lowering: use 'unsigned' to count destination popularity

SwitchInst::getNumCases() returns unsinged, so using uint64_t to count cases
seems unnecessary.

Also fix a missing CHECK in the test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224393 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Updating doubleword shift usages to new versions.
Colin LeMahieu [Tue, 16 Dec 2014 23:36:15 +0000 (23:36 +0000)]
[Hexagon] Updating doubleword shift usages to new versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224391 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd printing the LC_ENCRYPTION_INFO load command with llvm-objdump’s -private-headers.
Kevin Enderby [Tue, 16 Dec 2014 23:25:52 +0000 (23:25 +0000)]
Add printing the LC_ENCRYPTION_INFO load command with llvm-objdump’s -private-headers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224390 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLinker: Drop superseded subprograms
Duncan P. N. Exon Smith [Tue, 16 Dec 2014 23:23:41 +0000 (23:23 +0000)]
Linker: Drop superseded subprograms

When a function gets replaced by `ModuleLinker`, drop superseded
subprograms.  This ensures that the "first" subprogram pointing at a
function is the same one that `!dbg` references point at.

This is a stop-gap fix for PR21910.  Notably, this fixes Release+Asserts
bootstraps that are currently asserting out in
`LexicalScopes::initialize()` due to the explicit instantiations in
`lib/IR/Dominators.cpp` eventually getting replaced by -argpromotion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224389 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agofix typo, add spaces; NFC
Sanjay Patel [Tue, 16 Dec 2014 22:48:42 +0000 (22:48 +0000)]
fix typo, add spaces; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224384 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][SSE] Vector double -> float conversion memory folding (cvtpd2ps)
Simon Pilgrim [Tue, 16 Dec 2014 22:30:10 +0000 (22:30 +0000)]
[X86][SSE] Vector double -> float conversion memory folding (cvtpd2ps)

Added a missing memory folding relationship for the (V)CVTPD2PS instruction - we can safely fold these for stack reloads.

Differential Revision: http://reviews.llvm.org/D6663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224383 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMake the assert a bit stronger.
Rafael Espindola [Tue, 16 Dec 2014 22:29:43 +0000 (22:29 +0000)]
Make the assert a bit stronger.

We should get no declarations in here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224382 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Removing old XTYPE/BIT instructions and replacing usages.
Colin LeMahieu [Tue, 16 Dec 2014 22:17:09 +0000 (22:17 +0000)]
[Hexagon] Removing old XTYPE/BIT instructions and replacing usages.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224381 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agomerge consecutive loads that are offset from a base address
Sanjay Patel [Tue, 16 Dec 2014 21:57:18 +0000 (21:57 +0000)]
merge consecutive loads that are offset from a base address

SelectionDAG::isConsecutiveLoad() was not detecting consecutive loads
when the first load was offset from a base address.

This patch recognizes that pattern and subtracts the offset before comparing
the second load to see if it is consecutive.

The codegen change in the new test case improves from:

vmovsd 32(%rdi), %xmm0
vmovsd 48(%rdi), %xmm1
vmovhpd 56(%rdi), %xmm1, %xmm1
vmovhpd 40(%rdi), %xmm0, %xmm0
vinsertf128 $1, %xmm1, %ymm0, %ymm0


vmovups 32(%rdi), %ymm0

An existing test case is also improved from:

vmovsd (%rdi), %xmm0
vmovsd 16(%rdi), %xmm1
vmovsd 24(%rdi), %xmm2
vunpcklpd %xmm2, %xmm0, %xmm0 ## xmm0 = xmm0[0],xmm2[0]
vmovhpd 8(%rdi), %xmm1, %xmm3


vmovsd (%rdi), %xmm0
vmovsd 16(%rdi), %xmm1
vmovhpd 24(%rdi), %xmm0, %xmm0
vmovhpd 8(%rdi), %xmm1, %xmm1

This patch fixes PR21771 ( http://llvm.org/bugs/show_bug.cgi?id=21771 ).

Differential Revision: http://reviews.llvm.org/D6642

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224379 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix a bug in llvm-objdump’s -private-headers for the LC_VERSION_MIN_IPHONEOS
Kevin Enderby [Tue, 16 Dec 2014 21:48:27 +0000 (21:48 +0000)]
Fix a bug in llvm-objdump’s -private-headers for the LC_VERSION_MIN_IPHONEOS
load command not getting printed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224376 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding tstbit/bitclr/bitset instructions.
Colin LeMahieu [Tue, 16 Dec 2014 21:28:58 +0000 (21:28 +0000)]
[Hexagon] Adding tstbit/bitclr/bitset instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224374 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[sanitizer] prevent function call merging for sanitizer-coverage callbacks
Kostya Serebryany [Tue, 16 Dec 2014 21:24:15 +0000 (21:24 +0000)]
[sanitizer] prevent function call merging for sanitizer-coverage callbacks

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224372 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix another use of PRIx32 that should have been PRIx64.
Kevin Enderby [Tue, 16 Dec 2014 21:00:25 +0000 (21:00 +0000)]
Fix another use of PRIx32 that should have been PRIx64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224368 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding bit count and twiddling instructions.
Colin LeMahieu [Tue, 16 Dec 2014 20:57:56 +0000 (20:57 +0000)]
[Hexagon] Adding bit count and twiddling instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224367 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding asr/lsr/asl reg/imm, asl with saturation, asr with rounding. Double...
Colin LeMahieu [Tue, 16 Dec 2014 20:40:23 +0000 (20:40 +0000)]
[Hexagon] Adding asr/lsr/asl reg/imm, asl with saturation, asr with rounding.  Doubleword abs/neg/not.  Interleave and deinterleave instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224365 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[dsymutil] Pass the verbosity flag down to the processing. NFC for now.
Frederic Riss [Tue, 16 Dec 2014 20:22:11 +0000 (20:22 +0000)]
[dsymutil] Pass the verbosity flag down to the processing. NFC for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224361 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[dsymutil] Avoid calling getStringTableData() for each symbol. NFC.
Frederic Riss [Tue, 16 Dec 2014 20:21:34 +0000 (20:21 +0000)]
[dsymutil] Avoid calling getStringTableData() for each symbol. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224360 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agox86-32: PUSHF/POPF use/def EFLAGS
JF Bastien [Tue, 16 Dec 2014 20:15:45 +0000 (20:15 +0000)]
x86-32: PUSHF/POPF use/def EFLAGS

Summary: As a side-quest for D6629 jvoung pointed out that I should use -verify-machineinstrs and this found a bug in x86-32's handling of EFLAGS for PUSHF/POPF. This patch fixes the use/def, and adds -verify-machineinstrs to all x86 tests which contain 'EFLAGS'. One exception: this patch leaves inline-asm-fpstack.ll as-is because it fails -verify-machineinstrs in a way unrelated to EFLAGS. This patch also modifies cmpxchg-clobber-flags.ll along the lines of what D6629 already does by also testing i386.

Test Plan: ninja check

Reviewers: t.p.northover, jvoung

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6687

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224359 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse CastInst::castIsValid to simplify the verifier.
Rafael Espindola [Tue, 16 Dec 2014 19:29:29 +0000 (19:29 +0000)]
Use CastInst::castIsValid to simplify the verifier.

Also delete a dead member variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224356 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoNVPTX: Remove duplicate of AsmPrinter::lowerConstant
Matt Arsenault [Tue, 16 Dec 2014 19:16:17 +0000 (19:16 +0000)]
NVPTX: Remove duplicate of AsmPrinter::lowerConstant

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224355 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMove lowerConstant to AsmPrinter
Matt Arsenault [Tue, 16 Dec 2014 19:16:14 +0000 (19:16 +0000)]
Move lowerConstant to AsmPrinter

This was a static function before, and NVPTX duplicated it
because it wasn't exposed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224354 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CodeGenPrepare] Move sign/zero extensions near loads using type promotion.
Quentin Colombet [Tue, 16 Dec 2014 19:09:03 +0000 (19:09 +0000)]
[CodeGenPrepare] Move sign/zero extensions near loads using type promotion.

This patch extends the optimization in CodeGenPrepare that moves a sign/zero
extension near a load when the target can combine them. The optimization may
promote any operations between the extension and the load to make that possible.

Although this optimization may be beneficial for all targets, in particular
AArch64, this is enabled for X86 only as I have not benchmarked it for other
targets yet.

** Context **

Most targets feature extended loads, i.e., loads that perform a zero or sign
extension for free. In that context it is interesting to expose such pattern in
CodeGenPrepare so that the instruction selection pass can form such loads.
Sometimes, this pattern is blocked because of instructions between the load and
the extension. When those instructions are promotable to the extended type, we
can expose this pattern.

** Motivating Example **

Let us consider an example:
define void @foo(i8* %addr1, i32* %addr2, i8 %a, i32 %b) {
  %ld = load i8* %addr1
  %zextld = zext i8 %ld to i32
  %ld2 = load i32* %addr2
  %add = add nsw i32 %ld2, %zextld
  %sextadd = sext i32 %add to i64
  %zexta = zext i8 %a to i32
  %addza = add nsw i32 %zexta, %zextld
  %sextaddza = sext i32 %addza to i64
  %addb = add nsw i32 %b, %zextld
  %sextaddb = sext i32 %addb to i64
  call void @dummy(i64 %sextadd, i64 %sextaddza, i64 %sextaddb)
  ret void

As it is, this IR generates the following assembly on x86_64:
  movzbl  (%rdi), %eax   # zero-extended load
  movl  (%rsi), %es      # plain load
  addl  %eax, %esi       # 32-bit add
  movslq  %esi, %rdi     # sign extend the result of add
  movzbl  %dl, %edx      # zero extend the first argument
  addl  %eax, %edx       # 32-bit add
  movslq  %edx, %rsi     # sign extend the result of add
  addl  %eax, %ecx       # 32-bit add
  movslq  %ecx, %rdx     # sign extend the result of add
The throughput of this sequence is 7.45 cycles on Ivy Bridge according to IACA.

Now, by promoting the additions to form more extended loads we would generate:
  movzbl  (%rdi), %eax   # zero-extended load
  movslq  (%rsi), %rdi   # sign-extended load
  addq  %rax, %rdi       # 64-bit add
  movzbl  %dl, %esi      # zero extend the first argument
  addq  %rax, %rsi       # 64-bit add
  movslq  %ecx, %rdx     # sign extend the second argument
  addq  %rax, %rdx       # 64-bit add
The throughput of this sequence is 6.15 cycles on Ivy Bridge according to IACA.

This kind of sequences happen a lot on code using 32-bit indexes on 64-bit

Note: The throughput numbers are similar on Sandy Bridge and Haswell.

** Proposed Solution **

To avoid the penalty of all these sign/zero extensions, we merge them in the
loads at the beginning of the chain of computation by promoting all the chain of
computation on the extended type. The promotion is done if and only if we do not
introduce new extensions, i.e., if we do not degrade the code quality.
To achieve this, we extend the existing “move ext to load” optimization with the
promotion mechanism introduced to match larger patterns for addressing mode
The idea of this extension is to perform the following transformation:

The promotion mechanism in that optimization is enabled by a new TargetLowering
switch, which is off by default. In other words, by default, the optimization
performs the “move ext to load” optimization as it was before this patch.

** Performance **

Configuration: x86_64: Ivy Bridge fixed at 2900MHz running OS X 10.10.
Tested Optimization Levels: O3/Os
Tests: llvm-testsuite + externals.
- No regression beside noise.
- Improvements:
CINT2006/473.astar:  ~2%
Benchmarks/PAQ8p: ~2%
Misc/perlin: ~3%

The results are consistent for both O3 and Os.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224351 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix the arm build bots for a test that was added. A printing routine was incorrectly...
Kevin Enderby [Tue, 16 Dec 2014 18:58:11 +0000 (18:58 +0000)]
Fix the arm build bots for a test that was added.  A printing routine was incorrectly using PRIx32
when it should have been using PRIx64 for the value that was passed as uint64_t .

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224350 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AVX512] Enable integer arithmetic lowering for AVX512BW/VL subsets.
Robert Khasanov [Tue, 16 Dec 2014 18:24:07 +0000 (18:24 +0000)]
[AVX512] Enable integer arithmetic lowering for AVX512BW/VL subsets.
Added lowering tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224349 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoOn behalf of Matthew Wahab:
Evgeny Astigeevich [Tue, 16 Dec 2014 18:16:17 +0000 (18:16 +0000)]
On behalf of Matthew Wahab:

An instruction alias defined with InstAlias and an optional operand in the
middle of the AsmString field, "..${a} <operands>", would get the final
"}" printed in the instruction disassembly. This wouldn't happen if the optional
operand appeared as the last item in the AsmString which is how the current
backends avoided the problem.

There don't appear to be any tests for this part of Tablegen but it passes the
pre-commit tests. Manually tested the change by enabling the generic alias
printer in the ARM backend and checking the output.

Differential Revision: http://reviews.llvm.org/D6529

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224348 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[MC] Reset the MCInst in the matcher function before adding opcode/operands.
Ahmed Bougacha [Tue, 16 Dec 2014 18:05:28 +0000 (18:05 +0000)]
[MC] Reset the MCInst in the matcher function before adding opcode/operands.

On X86, the Intel asm parser tries to match all memory operand sizes when
none is explicitly specified.  For LEA, which doesn't really have a memory
operand (just a pointer one), this results in multiple successful matches,
one for each memory size.  There's no error because it's same opcode, so
really, it's just one match.  However, the tablegen'd matcher function
adds opcode/operands to the passed MCInst, and this results in multiple
duplicated operands.

This commit clears the MCInst in the tablegen'd matcher function.
We sometimes clear it when the match failed, so there's no expectation of
keeping the previous content anyway.

Differential Revision: http://reviews.llvm.org/D6670

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224347 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding absolute value, and negate with saturation
Colin LeMahieu [Tue, 16 Dec 2014 17:44:49 +0000 (17:44 +0000)]
[Hexagon] Adding absolute value, and negate with saturation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224346 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agocombine consecutive subvector 16-byte loads into one 32-byte load
Sanjay Patel [Tue, 16 Dec 2014 16:30:01 +0000 (16:30 +0000)]
combine consecutive subvector 16-byte loads into one 32-byte load

This is a fix for PR21709 ( http://llvm.org/bugs/show_bug.cgi?id=21709 ).
When we have 2 consecutive 16-byte loads that are merged into one 32-byte vector,
we can use a single 32-byte load instead.
But we don't do this for SandyBridge / IvyBridge because they have slower 32-byte memops.
We also don't bother using 32-byte *integer* loads on a machine that only has AVX1 (btver2)
because those operands would have to be split in half anyway since there is no support for
32-byte integer math ops.

Differential Revision: http://reviews.llvm.org/D6492

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224344 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding saturate and swizzle instructions.
Colin LeMahieu [Tue, 16 Dec 2014 16:27:17 +0000 (16:27 +0000)]
[Hexagon] Adding saturate and swizzle instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224343 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AVX512] Add a comment for avx512_broadcast_pat multiclass
Robert Khasanov [Tue, 16 Dec 2014 16:12:11 +0000 (16:12 +0000)]
[AVX512] Add a comment for avx512_broadcast_pat multiclass

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224341 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Removing old multiply defs and updating references to new versions.
Colin LeMahieu [Tue, 16 Dec 2014 16:10:01 +0000 (16:10 +0000)]
[Hexagon] Removing old multiply defs and updating references to new versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224340 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoThe single check for N64 inside MipsDisassemblerBase's subclasses is actually wrong...
Vladimir Medic [Tue, 16 Dec 2014 15:29:12 +0000 (15:29 +0000)]
The single check for N64 inside MipsDisassemblerBase's subclasses is actually wrong. It should be testing for FeatureGP64bit.There are no functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224339 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][microMIPS] Implement SWP and LWP instructions
Zoran Jovanovic [Tue, 16 Dec 2014 14:59:10 +0000 (14:59 +0000)]
[mips][microMIPS] Implement SWP and LWP instructions
Differential Revision: http://reviews.llvm.org/D5667

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224338 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFixing -Wsign-compare warnings; NFC.
Aaron Ballman [Tue, 16 Dec 2014 14:04:11 +0000 (14:04 +0000)]
Fixing -Wsign-compare warnings; NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224337 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd disassembler tests for mips4 platform. There are no functional changes.
Vladimir Medic [Tue, 16 Dec 2014 13:02:25 +0000 (13:02 +0000)]
Add disassembler tests for mips4 platform. There are no functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224335 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMasked Load and Store Intrinsics in loop vectorizer.
Elena Demikhovsky [Tue, 16 Dec 2014 11:50:42 +0000 (11:50 +0000)]
Masked Load and Store Intrinsics in loop vectorizer.
The loop vectorizer optimizes loops containing conditional memory
accesses by generating masked load and store intrinsics.
This decision is target dependent.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224334 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Fix arguments-struct.ll for Windows and OSX hosts.
Daniel Sanders [Tue, 16 Dec 2014 11:21:58 +0000 (11:21 +0000)]
[mips] Fix arguments-struct.ll for Windows and OSX hosts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224333 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Prevent PerformVCVTCombine from combining a vmul/vcvt with 8 lanes
Bradley Smith [Tue, 16 Dec 2014 10:59:27 +0000 (10:59 +0000)]
[ARM] Prevent PerformVCVTCombine from combining a vmul/vcvt with 8 lanes

This would result in a crash since the vcvt used does not support v8i32 types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224332 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoX86: Added FeatureVectorUAMem for all AVX architectures.
Elena Demikhovsky [Tue, 16 Dec 2014 09:10:08 +0000 (09:10 +0000)]
X86: Added FeatureVectorUAMem for all AVX architectures.
According to AVX specification:

"Most arithmetic and data processing instructions encoded using the VEX prefix and
performing memory accesses have more flexible memory alignment requirements
than instructions that are encoded without the VEX prefix. Specifically,
With the exception of explicitly aligned 16 or 32 byte SIMD load/store instructions,
most VEX-encoded, arithmetic and data processing instructions operate in
a flexible environment regarding memory address alignment, i.e. VEX-encoded
instruction with 32-byte or 16-byte load semantics will support unaligned load
operation by default. Memory arguments for most instructions with VEX prefix
operate normally without causing #GP(0) on any byte-granularity alignment
(unlike Legacy SSE instructions)."

The same for AVX-512.

This change does not affect anything right now, because only the "memop pattern fragment"
depends on FeatureVectorUAMem and it is not used in AVX patterns.
All AVX patterns are based on the "unaligned load" anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224330 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove 'metadata' from comments
Duncan P. N. Exon Smith [Tue, 16 Dec 2014 07:45:05 +0000 (07:45 +0000)]
Remove 'metadata' from comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224328 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIR: Stop printing 'metadata' in Metadata::print()
Duncan P. N. Exon Smith [Tue, 16 Dec 2014 07:40:31 +0000 (07:40 +0000)]
IR: Stop printing 'metadata' in Metadata::print()

Stop printing `metadata` in `Metadata::print()` and

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224327 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIR: Make MDNode::dump() useful by adding addresses
Duncan P. N. Exon Smith [Tue, 16 Dec 2014 07:09:37 +0000 (07:09 +0000)]
IR: Make MDNode::dump() useful by adding addresses

It's horrible to inspect `MDNode`s in a debugger.  All of their operands
that are `MDNode`s get dumped as `<badref>`, since we can't assign
metadata slots in the context of a `Metadata::dump()`.  (Why not?  Why
not assign numbers lazily?  Because then each time you called `dump()`,
a given `MDNode` could have a different lazily assigned number.)

Fortunately, the C memory model gives us perfectly good identifiers for
`MDNode`.  Add pointer addresses to the dumps, transforming this:

    (lldb) e N->dump()
    !{i32 662302, i32 26, <badref>, null}

    (lldb) e ((MDNode*)N->getOperand(2))->dump()
    !{i32 4, !"foo"}


    (lldb) e N->dump()
    !{i32 662302, i32 26, <0x100706ee0>, null}

    (lldb) e ((MDNode*)0x100706ee0)->dump()
    !{i32 4, !"foo"}

and this:

    (lldb) e N->dump()
    0x101200248 = !{<badref>, <badref>, <badref>, <badref>, <badref>}

    (lldb) e N->getOperand(0)
    (const llvm::MDOperand) $0 = {
      MD = 0x00000001012004e0
    (lldb) e N->getOperand(1)
    (const llvm::MDOperand) $1 = {
      MD = 0x00000001012004e0
    (lldb) e N->getOperand(2)
    (const llvm::MDOperand) $2 = {
      MD = 0x0000000101200058
    (lldb) e N->getOperand(3)
    (const llvm::MDOperand) $3 = {
      MD = 0x00000001012004e0
    (lldb) e N->getOperand(4)
    (const llvm::MDOperand) $4 = {
      MD = 0x0000000101200058
    (lldb) e ((MDNode*)0x00000001012004e0)->dump()

    (lldb) e ((MDNode*)0x0000000101200058)->dump()


    (lldb) e N->dump()
    !{<0x1012004e0>, <0x1012004e0>, <0x101200058>, <0x1012004e0>, <0x101200058>}

    (lldb) e ((MDNode*)0x1012004e0)->dump()

    (lldb) e ((MDNode*)0x101200058)->dump()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224325 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Update testcase to actually check something
Duncan P. N. Exon Smith [Tue, 16 Dec 2014 07:08:19 +0000 (07:08 +0000)]
DebugInfo: Update testcase to actually check something

This test was missing a `Debug Info Version` so it's `not grep` was
passing vacuously.  Update it to CHECK for something useful at the same
time so it doesn't bitrot quite so easily in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224324 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM: diagnose deprecated syntax
Saleem Abdulrasool [Tue, 16 Dec 2014 05:53:25 +0000 (05:53 +0000)]
ARM: diagnose deprecated syntax

The use of SP and PC in the register list for stores is deprecated on ARM
(ARM ARM A.8.8.199):

  ARM deprecates the use of ARM instructions that include the SP or the PC in
  the list.

Provide a deprecation warning from the assembler in the case that the syntax is
ever seen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224319 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Improve instruction selection bit-permuting operations (32-bit)
Hal Finkel [Tue, 16 Dec 2014 05:51:41 +0000 (05:51 +0000)]
[PowerPC] Improve instruction selection bit-permuting operations (32-bit)

The PowerPC backend, somewhat embarrassingly, did not generate an
optimal-length sequence of instructions for a 32-bit bswap. While adding a
pattern for the bswap intrinsic to fix this would not have been terribly
difficult, doing so would not have addressed the real problem: we had been
generating poor code for many bit-permuting operations (by which I mean things
like byte-swap that permute the bits of one or more inputs around in various
ways). Here are some initial steps toward solving this deficiency.

Bit-permuting operations are represented, at the SDAG level, using ISD::ROTL,
SHL, SRL, AND and OR (mostly with constant second operands). Looking back
through these operations, we can build up a description of the bits in the
resulting value in terms of bits of one or more input values (and constant
zeros). For each bit, we compute the rotation amount from the original value,
and then group consecutive (value, rotation factor) bits into groups. Groups
sharing these attributes are then collected and sorted, and we can then
instruction select the entire permutation using a combination of masked
rotations (rlwinm), imm ands (andi/andis), and masked rotation inserts

The result is that instead of lowering an i32 bswap as:

rlwinm 5, 3, 24, 16, 23
rlwinm 4, 3, 24, 0, 7
rlwimi 4, 3, 8, 8, 15
rlwimi 5, 3, 8, 24, 31
rlwimi 4, 5, 0, 16, 31

we now produce:

rlwinm 4, 3, 8, 0, 31
rlwimi 4, 3, 24, 16, 23
rlwimi 4, 3, 24, 0, 7

and for the 'test6' example in the PowerPC/README.txt file:

 unsigned test6(unsigned x) {
   return ((x & 0x00FF0000) >> 16) | ((x & 0x000000FF) << 16);

we used to produce:

lis 4, 255
rlwinm 3, 3, 16, 0, 31
ori 4, 4, 255
and 3, 3, 4

and now we produce:

rlwinm 4, 3, 16, 24, 31
rlwimi 4, 3, 16, 8, 15

and, as a nice bonus, this fixes the FIXME in

This commit does not include instruction-selection for i64 operations, those
will come later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224318 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM: 80-column
Saleem Abdulrasool [Tue, 16 Dec 2014 04:10:10 +0000 (04:10 +0000)]
ARM: 80-column

clang-format a function with an overly long string constant.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224314 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLiveRangeCalc: Rewrite subrange calculation
Matthias Braun [Tue, 16 Dec 2014 04:03:38 +0000 (04:03 +0000)]
LiveRangeCalc: Rewrite subrange calculation

This changes subrange calculation to calculate subranges sequentially
instead of in parallel. The code is easier to understand that way and
addresses the code review issues raised about LiveOutData being
hard to understand/needing more comments by removing them :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224313 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove the last unnecessary member variable of mapped_file_region. NFC.
Rafael Espindola [Tue, 16 Dec 2014 03:10:29 +0000 (03:10 +0000)]
Remove the last unnecessary member variable of mapped_file_region. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224312 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoConvert a member variable to a local variable. NFC.
Rafael Espindola [Tue, 16 Dec 2014 02:53:35 +0000 (02:53 +0000)]
Convert a member variable to a local variable. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224311 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove unused member and simplify. NFC.
Rafael Espindola [Tue, 16 Dec 2014 02:19:26 +0000 (02:19 +0000)]
Remove unused member and simplify. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224309 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoStart adding thin archive support.
Rafael Espindola [Tue, 16 Dec 2014 01:43:41 +0000 (01:43 +0000)]
Start adding thin archive support.

This is just sufficient for 'ar t' to work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224307 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix a bug in llvm-objdump’s -private-headers for 32-bit Mach-O files
Kevin Enderby [Tue, 16 Dec 2014 01:14:45 +0000 (01:14 +0000)]
Fix a bug in llvm-objdump’s -private-headers for 32-bit Mach-O files
printing the section header.  And add some tests for this for 32-bit files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224302 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM/AArch64: Attach the FrameSetup MIFlag to CFI instructions.
Adrian Prantl [Tue, 16 Dec 2014 00:20:49 +0000 (00:20 +0000)]
ARM/AArch64: Attach the FrameSetup MIFlag to CFI instructions.
Debug info marks the first instruction without the FrameSetup flag
as being the end of the function prologue. Any CFI instructions in the
middle of the function prologue would cause debug info to end the prologue
too early and worse, attach the line number of the CFI instruction, which
incidentally is often 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224294 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding doubleword multiplies with and without accumulation.
Colin LeMahieu [Tue, 16 Dec 2014 00:07:24 +0000 (00:07 +0000)]
[Hexagon] Adding doubleword multiplies with and without accumulation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224293 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSink the isa into the assert
Michael Ilseman [Mon, 15 Dec 2014 23:41:21 +0000 (23:41 +0000)]
Sink the isa into the assert

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224291 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding halfword to doubleword multiplies.
Colin LeMahieu [Mon, 15 Dec 2014 23:29:37 +0000 (23:29 +0000)]
[Hexagon] Adding halfword to doubleword multiplies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224289 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding logical-logical accumulation instructions and tests.
Colin LeMahieu [Mon, 15 Dec 2014 23:19:07 +0000 (23:19 +0000)]
[Hexagon] Adding logical-logical accumulation instructions and tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224288 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTeach ScalarEvolution to exploit min and max expressions when proving
Sanjoy Das [Mon, 15 Dec 2014 22:50:15 +0000 (22:50 +0000)]
Teach ScalarEvolution to exploit min and max expressions when proving

The motivation for this change is to optimize away checks in loops
like this:

    limit = min(t, len)
    for (i = 0 to limit)
      if (i >= len || i < 0) throw_array_of_of_bounds();
      a[i] = ...

Differential Revision: http://reviews.llvm.org/D6635

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224285 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdded missing tests for X86vzmovl folding. NFC.
Simon Pilgrim [Mon, 15 Dec 2014 22:45:48 +0000 (22:45 +0000)]
Added missing tests for X86vzmovl folding. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224284 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agox86: Emit LOCK prefix after DATA16
JF Bastien [Mon, 15 Dec 2014 22:34:58 +0000 (22:34 +0000)]
x86: Emit LOCK prefix after DATA16

Summary: x86 allows either ordering for the LOCK and DATA16 prefixes, but using GCC+GAS leads to different code generation than using LLVM. This change matches the order that GAS emits the x86 prefixes when a semicolon isn't used in inline assembly (see tc-i386.c comment before define LOCK_PREFIX), and helps simplify tooling that operates on the instruction's byte sequence (such as NaCl's validator). This change shouldn't have any performance impact.

Test Plan: ninja check

Reviewers: craig.topper, jvoung

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D6630

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224283 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding a number of additional multiply forms with tests.
Colin LeMahieu [Mon, 15 Dec 2014 22:10:37 +0000 (22:10 +0000)]
[Hexagon] Adding a number of additional multiply forms with tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224282 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoClean up warning about unused variable
Michael Ilseman [Mon, 15 Dec 2014 21:47:09 +0000 (21:47 +0000)]
Clean up warning about unused variable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224281 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "LiveRangeCalc: Rewrite subrange calculation"
Matthias Braun [Mon, 15 Dec 2014 21:36:35 +0000 (21:36 +0000)]
Revert "LiveRangeCalc: Rewrite subrange calculation"

Revert until I find out why non-subreg enabled targets break.

This reverts commit 6097277eefb9c5fb35a7f493c783ee1fd1b9d6a7.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224278 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert of r223763, in spirit.
Michael Ilseman [Mon, 15 Dec 2014 21:36:29 +0000 (21:36 +0000)]
Revert of r223763, in spirit.

r223763 was made to work around a temporary issue where a user of the
JIT was passing down a declaration (incorrectly). This shouldn't
occur, so assert rather than silently continue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224277 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoClarify HowFarToZero computation when the step is a positive power of two. Functiona...
Mark Heffernan [Mon, 15 Dec 2014 21:19:53 +0000 (21:19 +0000)]
Clarify HowFarToZero computation when the step is a positive power of two.  Functionally this should be identical to the existing code except for the case where Step is maximally negative (eg, INT_MIN).  We now punt in that one corner case to make reasoning about the code easier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224274 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding misc multiply encodings and tests.
Colin LeMahieu [Mon, 15 Dec 2014 21:17:03 +0000 (21:17 +0000)]
[Hexagon] Adding misc multiply encodings and tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224273 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLiveRangeCalc: Rewrite subrange calculation
Matthias Braun [Mon, 15 Dec 2014 21:16:21 +0000 (21:16 +0000)]
LiveRangeCalc: Rewrite subrange calculation

This changes subrange calculation to calculate subranges sequentially
instead of in parallel. The code is easier to understand that way and
addresses the code review issues raised about LiveOutData being
hard to understand/needing more comments by removing them :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224272 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding doubleworld accumulating multiplies of halfwords.
Colin LeMahieu [Mon, 15 Dec 2014 20:17:46 +0000 (20:17 +0000)]
[Hexagon] Adding doubleworld accumulating multiplies of halfwords.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224267 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding accumulating half word multiplies.
Colin LeMahieu [Mon, 15 Dec 2014 20:10:28 +0000 (20:10 +0000)]
[Hexagon] Adding accumulating half word multiplies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224266 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding multiply with rnd/sat/rndsat
Colin LeMahieu [Mon, 15 Dec 2014 20:01:59 +0000 (20:01 +0000)]
[Hexagon] Adding multiply with rnd/sat/rndsat

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224265 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] And also test INSERTPS shuffle mask pretty-printing.
Ahmed Bougacha [Mon, 15 Dec 2014 19:47:35 +0000 (19:47 +0000)]
[X86] And also test INSERTPS shuffle mask pretty-printing.

For r224260.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224264 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLiveRangeCalc: use more range based for loops; NFC
Matthias Braun [Mon, 15 Dec 2014 19:40:46 +0000 (19:40 +0000)]
LiveRangeCalc: use more range based for loops; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224263 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding encoding bits for halfword multiplies.
Colin LeMahieu [Mon, 15 Dec 2014 19:22:07 +0000 (19:22 +0000)]
[Hexagon] Adding encoding bits for halfword multiplies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224261 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Also pretty-print shuffle mask for INSERTPS rm variants.
Ahmed Bougacha [Mon, 15 Dec 2014 19:17:54 +0000 (19:17 +0000)]
[X86] Also pretty-print shuffle mask for INSERTPS rm variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224260 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIR: Make metadata typeless in assembly
Duncan P. N. Exon Smith [Mon, 15 Dec 2014 19:07:53 +0000 (19:07 +0000)]
IR: Make metadata typeless in assembly

Now that `Metadata` is typeless, reflect that in the assembly.  These
are the matching assembly changes for the metadata/value split in

  - Only use the `metadata` type when referencing metadata from a call
    intrinsic -- i.e., only when it's used as a `Value`.

  - Stop pretending that `ValueAsMetadata` is wrapped in an `MDNode`
    when referencing it from call intrinsics.

So, assembly like this:

    define @foo(i32 %v) {
      call void @llvm.foo(metadata !{i32 %v}, metadata !0)
      call void @llvm.foo(metadata !{i32 7}, metadata !0)
      call void @llvm.foo(metadata !1, metadata !0)
      call void @llvm.foo(metadata !3, metadata !0)
      call void @llvm.foo(metadata !{metadata !3}, metadata !0)
      ret void, !bar !2
    !0 = metadata !{metadata !2}
    !1 = metadata !{i32* @global}
    !2 = metadata !{metadata !3}
    !3 = metadata !{}

turns into this:

    define @foo(i32 %v) {
      call void @llvm.foo(metadata i32 %v, metadata !0)
      call void @llvm.foo(metadata i32 7, metadata !0)
      call void @llvm.foo(metadata i32* @global, metadata !0)
      call void @llvm.foo(metadata !3, metadata !0)
      call void @llvm.foo(metadata !{!3}, metadata !0)
      ret void, !bar !2
    !0 = !{!2}
    !1 = !{i32* @global}
    !2 = !{!3}
    !3 = !{}

I wrote an upgrade script that handled almost all of the tests in llvm
and many of the tests in cfe (even handling many `CHECK` lines).  I've
attached it (or will attach it in a moment if you're speedy) to PR21532
to help everyone update their out-of-tree testcases.

This is part of PR21532.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224257 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSilence more static analyzer warnings.
Michael Ilseman [Mon, 15 Dec 2014 18:48:43 +0000 (18:48 +0000)]
Silence more static analyzer warnings.

Add in definedness checks for shift operators, null checks when
pointers are assumed by the code to be non-null, and explicit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224255 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMove mips1 tests to test/MC/Disassembler/Mips/mips1
Reid Kleckner [Mon, 15 Dec 2014 17:56:02 +0000 (17:56 +0000)]
Move mips1 tests to test/MC/Disassembler/Mips/mips1

This matches the pattern of the mips2 and 3 tests, as well as our normal

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224254 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd disassembler tests for mips3 platform. There are no functional changes.
Vladimir Medic [Mon, 15 Dec 2014 16:19:34 +0000 (16:19 +0000)]
Add disassembler tests for mips3 platform. There are no functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224253 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd disassembler tests for mips2 platform. There are no functional changes.
Vladimir Medic [Mon, 15 Dec 2014 15:58:20 +0000 (15:58 +0000)]
Add disassembler tests for mips2 platform. There are no functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224252 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoThis is the first in a series of patches that add missing disassembler tests for...
Vladimir Medic [Mon, 15 Dec 2014 15:22:33 +0000 (15:22 +0000)]
This is the first in a series of patches that add missing disassembler tests for mips platform. The patches are divided per version of mips CPU to keep the patches smaller and ease the review. There are no functional changes, code is changed only if new tests reveal a bug.This patch adds disassembler tests for mips1 CPU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224251 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoChanging a cast from unsigned to uint64_t, should be NFC in practice.
Aaron Ballman [Mon, 15 Dec 2014 14:25:12 +0000 (14:25 +0000)]
Changing a cast from unsigned to uint64_t, should be NFC in practice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224249 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdded a test related to 224247 revision
Elena Demikhovsky [Mon, 15 Dec 2014 14:14:10 +0000 (14:14 +0000)]
Added a test related to 224247 revision

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224248 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSink store based on alias analysis
Elena Demikhovsky [Mon, 15 Dec 2014 14:09:53 +0000 (14:09 +0000)]
Sink store based on alias analysis
 - by Ella Bolshinsky
The alias analysis is used define whether the given instruction
is a barrier for store sinking. For 2 identical stores, following
instructions are checked in the both basic blocks, to determine
whether they are sinking barriers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224247 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Break false dependencies before partial register updates when the source operan...
Michael Kuperstein [Mon, 15 Dec 2014 13:18:21 +0000 (13:18 +0000)]
[X86] Break false dependencies before partial register updates when the source operand is in memory

Adds the various "rm" instruction variants into the list of instructions that have a partial register update. Also adds all variants of SQRTSD that were missing in the original list.

Differential Revision: http://reviews.llvm.org/D6620

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224246 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTypo Correction in Test Case. NFC.
Suyog Sarda [Mon, 15 Dec 2014 12:19:46 +0000 (12:19 +0000)]
Typo Correction in Test Case. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224244 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAVX-512: Added EXPAND instructions and intrinsics.
Elena Demikhovsky [Mon, 15 Dec 2014 10:03:52 +0000 (10:03 +0000)]
AVX-512: Added EXPAND instructions and intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224241 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix line mapping information in LLVM JIT profiling with Vtune
Alexey Bataev [Mon, 15 Dec 2014 04:45:43 +0000 (04:45 +0000)]
Fix line mapping information in LLVM JIT profiling with Vtune
The line mapping information for dynamic code is reported incorrectly. It causes VTune to map LLVM generated code to source lines incorrectly. This patch fix this issue.
Patch by Denis Pravdin.
Differential Revision: http://reviews.llvm.org/D6603

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224229 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoThreadLocal: Move Unix-specific code out of Support/ThreadLocal.cpp
David Majnemer [Mon, 15 Dec 2014 01:19:53 +0000 (01:19 +0000)]
ThreadLocal: Move Unix-specific code out of Support/ThreadLocal.cpp

Just a cleanup, no functionality change is intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224227 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoStringPool: Cleanup typos in unittest comments
David Majnemer [Mon, 15 Dec 2014 01:04:49 +0000 (01:04 +0000)]
StringPool: Cleanup typos in unittest comments

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224226 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoThreadLocal: Return a mutable pointer if templated with a non-const type
David Majnemer [Mon, 15 Dec 2014 01:04:45 +0000 (01:04 +0000)]
ThreadLocal: Return a mutable pointer if templated with a non-const type

It makes more sense for ThreadLocal<const T>::get to return a const T*
and ThreadLocal<T>::get to return a T*.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224225 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse unique_ptr to remove explicit delete.
Craig Topper [Mon, 15 Dec 2014 00:40:07 +0000 (00:40 +0000)]
Use unique_ptr to remove explicit delete.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224224 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLoop Vectorizer minor changes in the code -
Elena Demikhovsky [Sun, 14 Dec 2014 09:43:50 +0000 (09:43 +0000)]
Loop Vectorizer minor changes in the code -
some comments, function names, identation.

Reviewed here: http://reviews.llvm.org/D6527

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224218 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAPInt: udivrem should use machine instructions for single-word APInts
David Majnemer [Sun, 14 Dec 2014 09:41:56 +0000 (09:41 +0000)]
APInt: udivrem should use machine instructions for single-word APInts

This mirrors the behavior of APInt::udiv and APInt::urem.  Some
architectures, like X86, have a single instruction which can compute
both division and remainder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224217 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoScalarEvolution: Remove SCEVUDivision, it's unused
David Majnemer [Sun, 14 Dec 2014 09:12:33 +0000 (09:12 +0000)]
ScalarEvolution: Remove SCEVUDivision, it's unused

This is just a code simplification, no functionality change is intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224216 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Handle cmp op promotion for SELECT[_CC] nodes in PPCTL::DAGCombineExtBoolTrunc
Hal Finkel [Sun, 14 Dec 2014 05:53:19 +0000 (05:53 +0000)]
[PowerPC] Handle cmp op promotion for SELECT[_CC] nodes in PPCTL::DAGCombineExtBoolTrunc

PPCTargetLowering::DAGCombineExtBoolTrunc contains logic to remove unwanted
truncations and extensions when dealing with nodes of the form:
  zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)

There was a FIXME in the implementation (now removed) regarding the fact that
the function would abort the transformations if any of the non-output operands
of a SELECT or SELECT_CC node would need to be promoted (because they were
also output operands, for example). As a result, we continued to generate
unnecessary zero-extends for code such as this:

  unsigned foo(unsigned a, unsigned b) {
    return  (a <= b) ? a : b;

which would produce:

  cmplw 0, 3, 4
  isel 3, 4, 3, 1
  rldicl 3, 3, 0, 32

and now we produce:

  cmplw 0, 3, 4
  isel 3, 4, 3, 1

which is better in the obvious way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224213 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoReapply "[ARM] Combine base-updating/post-incrementing vector load/stores."
Ahmed Bougacha [Sat, 13 Dec 2014 23:22:12 +0000 (23:22 +0000)]
Reapply "[ARM] Combine base-updating/post-incrementing vector load/stores."

r223862 tried to also combine base-updating load/stores.
r224198 reverted it, as "it created a regression on the test-suite
on test MultiSource/Benchmarks/Ptrdist/anagram by scrambling the order
in which the words are shown."
Reapply, with a fix to ignore non-normal load/stores.
Truncstores are handled elsewhere (you can actually write a pattern for
those, whereas for postinc loads you can't, since they return two values),
but it should be possible to also combine extloads base updates, by checking
that the memory (rather than result) type is of the same size as the addend.

Original commit message:
We used to only combine intrinsics, and turn them into VLD1_UPD/VST1_UPD
when the base pointer is incremented after the load/store.

We can do the same thing for generic load/stores.

Note that we can only combine the first load/store+adds pair in
a sequence (as might be generated for a v16f32 load for instance),
because other combines turn the base pointer addition chain (each
computing the address of the next load, from the address of the last
load) into independent additions (common base pointer + this load's

Differential Revision: http://reviews.llvm.org/D6585

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224203 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "[ARM] Combine base-updating/post-incrementing vector load/stores."
Renato Golin [Sat, 13 Dec 2014 20:23:18 +0000 (20:23 +0000)]
Revert "[ARM] Combine base-updating/post-incrementing vector load/stores."

This reverts commit r223862, as it created a regression on the test-suite
on test MultiSource/Benchmarks/Ptrdist/anagram by scrambling the order
in which the words are shown. We'll investigate the issue and re-apply
when safe.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224198 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix Doxygen command misspellings.
Benjamin Kramer [Sat, 13 Dec 2014 19:19:07 +0000 (19:19 +0000)]
Fix Doxygen command misspellings.

Found by -Wdocumentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224197 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSilencing a -Wsign-compare warning; NFC.
Aaron Ballman [Sat, 13 Dec 2014 16:55:02 +0000 (16:55 +0000)]
Silencing a -Wsign-compare warning; NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224195 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSilencing a *lot* of -Wsign-compare warnings; NFC.
Aaron Ballman [Sat, 13 Dec 2014 16:53:15 +0000 (16:53 +0000)]
Silencing a *lot* of -Wsign-compare warnings; NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224194 91177308-0d34-0410-b5e6-96231b3b80d8