[Hexagon] Adding logical-logical accumulation instructions and tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224288 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td
index 18cc7d02bcb621c354aa353ac9713e613aaeb7c0..fed06334468944809eda667da8f53100b8a053bb 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -2178,9 +2178,49 @@ let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
                             IntRegs:$src1))]>, ImmRegRel;
 }
 
+let CextOpcode = "ADD_acc", isCodeGenOnly = 0 in {
+  let isExtentSigned = 1 in
+  def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext,
+                 [(set (i32 IntRegs:$dst),
+                       (add (add (i32 IntRegs:$src2), s8_16ExtPred:$src3),
+                            (i32 IntRegs:$src1)))]>, ImmRegRel;
+
+  def M2_acci  : T_MType_acc_rr <"+= add",  0b000, 0b001, 0,
+                 [(set (i32 IntRegs:$dst),
+                       (add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
+                            (i32 IntRegs:$src1)))]>, ImmRegRel;
+}
+
+let CextOpcode = "SUB_acc", isCodeGenOnly = 0 in {
+  let isExtentSigned = 1 in
+  def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8Ext>, ImmRegRel;
+
+  def M2_nacci  : T_MType_acc_rr <"-= add",  0b100, 0b001, 0>, ImmRegRel;
+}
+
 let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in
 def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>;
 
+let isCodeGenOnly = 0 in {
+def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>;
+def M2_subacc : T_MType_acc_rr <"+= sub",  0b000, 0b011, 1>;
+}
+
+class T_MType_acc_pat1 <InstHexagon MI, SDNode firstOp, SDNode secOp,
+                        PatLeaf ImmPred>
+  : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
+         (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
+
+class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
+  : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
+         (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
+
+def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
+def : T_MType_acc_pat1 <M2_macsin, mul, sub, u8ExtPred>;
+
+def : T_MType_acc_pat1 <M2_naccii, add, sub, s8_16ExtPred>;
+def : T_MType_acc_pat2 <M2_nacci, add, sub>;
+
 // Multiply and use lower result.
 // Rd=+mpyi(Rs,#u8)
 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
@@ -2307,16 +2347,6 @@ def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
                             (i64 (anyext (i32 IntRegs:$src3))))))],
             "$src1 = $dst">;
 
-
-let InputType = "reg", CextOpcode = "ADD_acc" in
-def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
-                            IntRegs:$src2, IntRegs:$src3),
-             "$dst += add($src2, $src3)",
-             [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
-                                                 (i32 IntRegs:$src3)),
-                                            (i32 IntRegs:$src1)))],
-             "$src1 = $dst">, ImmRegRel;
-
 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
 InputType = "imm", CextOpcode = "ADD_acc" in
 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
@@ -2327,15 +2357,6 @@ def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
                                             (i32 IntRegs:$src1)))],
              "$src1 = $dst">, ImmRegRel;
 
-let CextOpcode = "SUB_acc", InputType = "reg" in
-def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
-                            IntRegs:$src2, IntRegs:$src3),
-             "$dst -= add($src2, $src3)",
-             [(set (i32 IntRegs:$dst),
-                   (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
-                                                  (i32 IntRegs:$src3))))],
-             "$src1 = $dst">, ImmRegRel;
-
 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
 CextOpcode = "SUB_acc", InputType = "imm" in
 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,

diff --git a/test/MC/Disassembler/Hexagon/xtype_alu.txt b/test/MC/Disassembler/Hexagon/xtype_alu.txt
index 58c397ae32b9892972a8783c80241302947bbace..66bdc4379010c5307b8b196dffc78f98cd9cbe4e 100644 (file)
--- a/test/MC/Disassembler/Hexagon/xtype_alu.txt
+++ b/test/MC/Disassembler/Hexagon/xtype_alu.txt
@@ -1,5 +1,13 @@
 # RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
 
+0xf1 0xc2 0x15 0xe2
+# CHECK: r17 += add(r21, #23)
+0xf1 0xc2 0x95 0xe2
+# CHECK: r17 -= add(r21, #23)
+0x31 0xdf 0x15 0xef
+# CHECK: r17 += add(r21, r31)
+0x31 0xdf 0x95 0xef
+# CHECK: r17 -= add(r21, r31)
 0xf0 0xde 0x14 0xd3
 # CHECK: r17:16 = add(r21:20, r31:30)
 0x11 0xd5 0x1f 0xd5
@@ -36,6 +44,8 @@
 # CHECK: r17:16 = add(r21:20, r31:30):raw:hi
 0x10 0xde 0xf4 0xd3
 # CHECK: r17:16 = and(r21:20, r31:30)
+0x71 0xdf 0x95 0xef
+# CHECK: r17 ^= xor(r21, r31)
 0x11 0xdf 0xd5 0xd5
 # CHECK: r17 = max(r21, r31)
 0x91 0xdf 0xd5 0xd5
@@ -54,6 +64,8 @@
 # CHECK: r17:16 = minu(r21:20, r31:30)
 0x50 0xde 0xf4 0xd3
 # CHECK: r17:16 = or(r21:20, r31:30)
+0x71 0xd5 0x1f 0xef
+# CHECK: r17 += sub(r21, r31)
 0x11 0xd5 0x3f 0xd5
 # CHECK: r17 = sub(r21.l, r31.l)
 0x51 0xd5 0x3f 0xd5