oota-llvm.git
7 years agoSpecialCaseList: Add support for parsing multiple input files.
Alexey Samsonov [Wed, 4 Feb 2015 17:39:48 +0000 (17:39 +0000)]
SpecialCaseList: Add support for parsing multiple input files.

Summary:
This change allows users to create SpecialCaseList objects from
multiple local files. This is needed to implement a proper support
for -fsanitize-blacklist flag (allow users to specify multiple blacklists,
in addition to default blacklist, see PR22431).

DFSan can also benefit from this change, as DFSan instrumentation pass now
accepts ABI-lists both from -fsanitize-blacklist= and -mllvm -dfsan-abilist flags.

Go bindings are fixed accordingly.

Test Plan: regression test suite

Reviewers: pcc

Subscribers: llvm-commits, axw, kcc

Differential Revision: http://reviews.llvm.org/D7367

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228155 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding encoding information for absolute-set stores.
Colin LeMahieu [Wed, 4 Feb 2015 17:24:04 +0000 (17:24 +0000)]
[Hexagon] Adding encoding information for absolute-set stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228154 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding encoding bits for indirect long load instructions.
Colin LeMahieu [Wed, 4 Feb 2015 16:56:46 +0000 (16:56 +0000)]
[Hexagon] Adding encoding bits for indirect long load instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228152 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Fix subtarget feature set truncation when using .cpu directive
Bradley Smith [Wed, 4 Feb 2015 16:23:24 +0000 (16:23 +0000)]
[ARM] Fix subtarget feature set truncation when using .cpu directive

This is a bug that was caused due to storing the feature bitset in a 32-bit
variable when it is a 64-bit mask, discarding the top half of the feature set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228151 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][microMIPS] Implement CodeGen support for SW16 and LW16 instructions
Zoran Jovanovic [Wed, 4 Feb 2015 15:43:17 +0000 (15:43 +0000)]
[mips][microMIPS] Implement CodeGen support for SW16 and LW16 instructions
Differential Revision: http://reviews.llvm.org/D6581

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228149 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Make MipsSubtarget::hasMips*() functions consistent. NFC.
Daniel Sanders [Wed, 4 Feb 2015 15:18:11 +0000 (15:18 +0000)]
[mips] Make MipsSubtarget::hasMips*() functions consistent. NFC.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7377

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228147 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Remove unused check prefix from tests. NFC.
Daniel Sanders [Wed, 4 Feb 2015 14:48:39 +0000 (14:48 +0000)]
[mips] Remove unused check prefix from tests. NFC.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7376

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228145 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFixing a -Wsign-compare warning; NFC
Aaron Ballman [Wed, 4 Feb 2015 14:01:08 +0000 (14:01 +0000)]
Fixing a -Wsign-compare warning; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228142 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdding support to LLVM for targeting Cortex-A72
Renato Golin [Wed, 4 Feb 2015 13:31:29 +0000 (13:31 +0000)]
Adding support to LLVM for targeting Cortex-A72

Currently, Cortex-A72 is modelled as an Cortex-A57 except the fp
load balancing pass isn't enabled for Cortex-A72 as it's not
profitable to have it enabled for this core.

Patch by Ranjeet Singh.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228140 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix warning: "function declaration isn’t a prototype"
Rafael Espindola [Wed, 4 Feb 2015 13:30:28 +0000 (13:30 +0000)]
Fix warning: "function declaration isn’t a prototype"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228139 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoInstrProf: std::to_string needs to #include <string>
Justin Bogner [Wed, 4 Feb 2015 11:19:16 +0000 (11:19 +0000)]
InstrProf: std::to_string needs to #include <string>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228136 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Give movss and movsd execution domains in the x86 backend.
Chandler Carruth [Wed, 4 Feb 2015 10:58:53 +0000 (10:58 +0000)]
[x86] Give movss and movsd execution domains in the x86 backend.

This associates movss and movsd with the packed single and packed double
execution domains (resp.). While this is largely cosmetic, as we now
don't have weird ping-pong-ing between single and double precision, it
is also useful because it avoids the domain fixing algorithm from seeing
domain breaks that don't actually exist. It will also be much more
important if we have an execution domain default other than packed
single, as that would cause us to mix movss and movsd with integer
vector code on a regular basis, a very bad mixture.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228135 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Remove a low-value test that was just checking how we cleared
Chandler Carruth [Wed, 4 Feb 2015 10:47:34 +0000 (10:47 +0000)]
[x86] Remove a low-value test that was just checking how we cleared
a register. We have lots of tests covering this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228133 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Mechanically update a bunch of tests' check lines using the latest
Chandler Carruth [Wed, 4 Feb 2015 10:46:53 +0000 (10:46 +0000)]
[x86] Mechanically update a bunch of tests' check lines using the latest
version of the script.

Changes include:
- Using the VEX prefix
- Skipping more detail when we have useful shuffle comments to match
- Matching more shuffle comments that have been added to the printer
  (yay!)
- Matching the destination registers of some AVX instructions
- Stripping trailing whitespace that crept in
- Fixing indentation issues

Nothing interesting going on here. I'm just trying really hard to ensure
these changes don't show up in the diffs with actual changes to the
backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228132 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Teach the test update script to strip trailing whitespace.
Chandler Carruth [Wed, 4 Feb 2015 10:46:48 +0000 (10:46 +0000)]
[x86] Teach the test update script to strip trailing whitespace.

This is done in a bit of a strange way to use a multiline RE instead of
looping over the lines. Suggestions welcome here for a more pythonic way
of doing this as long as its reasonably fast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228131 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoReverting VLD1/VST1 base-updating/post-incrementing combining
Renato Golin [Wed, 4 Feb 2015 10:11:59 +0000 (10:11 +0000)]
Reverting VLD1/VST1 base-updating/post-incrementing combining

This reverts patches 223862, 224198, 224203, and 224754, which were all
related to the vector load/store combining and were reverted/reaplied
a few times due to the same alignment problems we're seeing now.

Further tests, mainly self-hosting Clang, will be needed to reapply this
patch in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228129 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Include the destination register in the check-lines for AVX
Chandler Carruth [Wed, 4 Feb 2015 09:18:27 +0000 (09:18 +0000)]
[x86] Include the destination register in the check-lines for AVX
instructions.

No actual change here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228127 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Add some tests I missed in the prior commit to cover blends with
Chandler Carruth [Wed, 4 Feb 2015 09:15:46 +0000 (09:15 +0000)]
[x86] Add some tests I missed in the prior commit to cover blends with
zero for v8i16 as well.

These exhibit the same domain badness, but also exhibit other weaknesses
in our blend lowering. More fixes to come.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228126 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Start to introduce bit-masking based blend lowering.
Chandler Carruth [Wed, 4 Feb 2015 09:06:05 +0000 (09:06 +0000)]
[x86] Start to introduce bit-masking based blend lowering.

This is the simplest form of bit-math based blending which only fires
when we are blending with zero and is relatively profitable. I've only
enabled this path on very specific lowering strategies. I'm planning to
widen its applicability in subsequent patches, but so far you'll notice
that even though we get fewer shufps instructions, we *still* do the bit
math in the FP execution port. I'm looking into why this is still
happening.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228124 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Add missing patterns for andps, orps, xorps, and andnps.
Chandler Carruth [Wed, 4 Feb 2015 09:06:01 +0000 (09:06 +0000)]
[x86] Add missing patterns for andps, orps, xorps, and andnps.

Specifically, the existing patterns were scalar-only. These cover the
packed vector bitwise operations when specifically requested with pseudo
instructions. This is particularly important in SSE1 where we can't
actually emit a logical operation on a v2i64 as that isn't a legal type.

This will be tested in subsequent patches which form the floating point
and patterns in more places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228123 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Add tests for blends-with-zero on 4-element vectors.
Chandler Carruth [Wed, 4 Feb 2015 09:05:58 +0000 (09:05 +0000)]
[x86] Add tests for blends-with-zero on 4-element vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228122 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoReplace tabs with spaces from r228116. Oops.
Bill Schmidt [Wed, 4 Feb 2015 06:14:38 +0000 (06:14 +0000)]
Replace tabs with spaces from r228116.  Oops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228117 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Handle 32-bit targets properly in PPCTLSDynamicCall.cpp
Bill Schmidt [Wed, 4 Feb 2015 05:51:56 +0000 (05:51 +0000)]
[PowerPC] Handle 32-bit targets properly in PPCTLSDynamicCall.cpp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228116 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix a warning in non-asserts builds
Philip Reames [Wed, 4 Feb 2015 05:11:20 +0000 (05:11 +0000)]
Fix a warning in non-asserts builds

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228114 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix some unnoticed/unwanted behavior change from r222319.
Frederic Riss [Wed, 4 Feb 2015 03:10:03 +0000 (03:10 +0000)]
Fix some unnoticed/unwanted behavior change from r222319.

The ARM assembler allows register alias redefinitions as long as it
targets the same register. r222319 broke that. In the AArch64 case
it would just produce a new warning, but in the ARM case it would
error out on previously accepted assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228109 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[fuzzer]: fix exit code, add more diagnostics
Kostya Serebryany [Wed, 4 Feb 2015 01:22:57 +0000 (01:22 +0000)]
[fuzzer]: fix exit code, add more diagnostics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228103 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[sanitizer] add another workaround for PR 17409: when over a threshold emit coverage...
Kostya Serebryany [Wed, 4 Feb 2015 01:21:45 +0000 (01:21 +0000)]
[sanitizer] add another workaround for PR 17409: when over a threshold emit coverage instrumentation as calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228102 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd code to llvm-objdump so the -section option with -macho will disassemble sections
Kevin Enderby [Wed, 4 Feb 2015 01:01:38 +0000 (01:01 +0000)]
Add code to llvm-objdump so the -section option with -macho will disassemble sections
that have attributes indicating they contain instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228101 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Refresh the checks of a number of tests using
Chandler Carruth [Wed, 4 Feb 2015 00:58:42 +0000 (00:58 +0000)]
[x86] Refresh the checks of a number of tests using
update_llc_test_checks.py.

The exact format of the checks has changed over time. This includes
different indenting rules, new shuffle comments that have been added,
and more operand hiding behind regular expressions.

No functional change to the tests are expected here, but this will make
subsequent patches have a clean diff as they change shuffle lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228097 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Switch to using the long '--check-prefix' form which the
Chandler Carruth [Wed, 4 Feb 2015 00:58:40 +0000 (00:58 +0000)]
[x86] Switch to using the long '--check-prefix' form which the
update_llc_test_checks.py script uses, and refresh the checks in this
test.

No functionality changed here, just bringing this test up to work with
automated updates using the python script.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228096 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Port this test to use utils/update_llc_test_checks.py.
Chandler Carruth [Wed, 4 Feb 2015 00:58:37 +0000 (00:58 +0000)]
[x86] Port this test to use utils/update_llc_test_checks.py.

This will make it easy to update as I change some parts of the X86
backend, makes it more clear what instruction differences are
introduced, and I find it makes it a bit easier to read as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228095 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMisc documentation/comment fixes.
Peter Collingbourne [Wed, 4 Feb 2015 00:42:45 +0000 (00:42 +0000)]
Misc documentation/comment fixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228093 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoClang format of a file introduced in 228090 (NFC)
Philip Reames [Wed, 4 Feb 2015 00:39:57 +0000 (00:39 +0000)]
Clang format of a file introduced in 228090 (NFC)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228091 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd a pass for inserting safepoints into (nearly) arbitrary IR
Philip Reames [Wed, 4 Feb 2015 00:37:33 +0000 (00:37 +0000)]
Add a pass for inserting safepoints into (nearly) arbitrary IR

This pass is responsible for figuring out where to place call safepoints and safepoint polls. It doesn't actually make the relocations explicit; that's the job of the RewriteStatepointsForGC pass (http://reviews.llvm.org/D6975).

Note that this code is not yet finalized.  Its moving in tree for incremental development, but further cleanup is needed and will happen over the next few days.  It is not yet part of the standard pass order.

Planned changes in the near future:
 - I plan on restructuring the statepoint rewrite to use the functions add to the IRBuilder a while back.
 - In the current pass, the function "gc.safepoint_poll" is treated specially but is not an intrinsic. I plan to make identifying the poll function a property of the GCStrategy at some point in the near future.
 - As follow on patches, I will be separating a collection of test cases we have out of tree and submitting them upstream.
 - It's not explicit in the code, but these two patches are introducing a new state for a statepoint which looks a lot like a patchpoint. There's no a transient form which doesn't yet have the relocations explicitly represented, but does prevent reordering of memory operations. Once this is in, I need to update actually make this explicit by reserving the 'unused' argument of the statepoint as a flag, updating the docs, and making the code explicitly check for such a thing. This wasn't really planned, but once I split the two passes - which was done for other reasons - the intermediate state fell out. Just reminds us once again that we need to merge statepoints and patchpoints at some point in the not that distant future.

Future directions planned:
 - Identifying more cases where a backedge safepoint isn't required to ensure timely execution of a safepoint poll.
 - Tweaking the insertion process to generate easier to optimize IR. (For example, investigating making SplitBackedge) the default.
 - Adding opt-in flags for a GCStrategy to use this pass. Once done, add this pass to the actual pass ordering.

Differential Revision: http://reviews.llvm.org/D6981

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228090 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoimproved CHECK
Sanjay Patel [Wed, 4 Feb 2015 00:24:06 +0000 (00:24 +0000)]
improved CHECK

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228086 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdded missing header for the explicit dependency on MDNode.
Galina Kistanova [Wed, 4 Feb 2015 00:20:52 +0000 (00:20 +0000)]
Added missing header for the explicit dependency on MDNode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228085 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoInstrProf: Add some unit tests for CoverageMapping
Justin Bogner [Wed, 4 Feb 2015 00:15:12 +0000 (00:15 +0000)]
InstrProf: Add some unit tests for CoverageMapping

The llvm-level tests for coverage mapping need a binary input file,
which means they're hard to understand, hard to update, and it's
difficult to add new ones. By adding some unit tests that build up the
coverage data structures in C++, we can write more meaningful and
targeted tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228084 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoInstrProf: Use a stable sort when reading coverage regions
Justin Bogner [Wed, 4 Feb 2015 00:12:18 +0000 (00:12 +0000)]
InstrProf: Use a stable sort when reading coverage regions

Keeping regions that start at the same location in insertion order
makes this logic easier to test / more deterministic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228083 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Revert change to isCodeGenOnly = 1 in r228080
Colin LeMahieu [Wed, 4 Feb 2015 00:09:23 +0000 (00:09 +0000)]
[Hexagon] Revert change to isCodeGenOnly = 1 in r228080

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228082 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Changing some isCodeGenOnly to isAsmParserOnly since we want them to asm...
Colin LeMahieu [Wed, 4 Feb 2015 00:07:26 +0000 (00:07 +0000)]
[Hexagon] Changing some isCodeGenOnly to isAsmParserOnly since we want them to asm parse but not cause decode conflicts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228080 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove a gross usage of environment variables in MachineVerifier, replacing it with...
Owen Anderson [Wed, 4 Feb 2015 00:02:59 +0000 (00:02 +0000)]
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT.

This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228079 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoInstrProf: Make CounterMappingRegions less confusing to construct
Justin Bogner [Tue, 3 Feb 2015 23:59:33 +0000 (23:59 +0000)]
InstrProf: Make CounterMappingRegions less confusing to construct

Creating empty and expansion regions is awkward with the current API.
Expose static methods to make this simpler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228075 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PBQP] Provide more information in the debug prints
Arnaud A. de Grandmaison [Tue, 3 Feb 2015 23:40:24 +0000 (23:40 +0000)]
[PBQP] Provide more information in the debug prints

Based on a patch by Jonas Paulsson

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228068 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse ImmutableCallSite for statepoint verification.
Philip Reames [Tue, 3 Feb 2015 23:18:47 +0000 (23:18 +0000)]
Use ImmutableCallSite for statepoint verification.

Patch by: Igor Laevsky

"This change generalizes statepoint verification to use ImmutableCallSite instead of CallInst. This will allow to easily implement invoke statepoint verification (in a following change)."

Differential Revision: http://reviews.llvm.org/D7308

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228064 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LV] Split off memcheck block really at the first check
Adam Nemet [Tue, 3 Feb 2015 22:45:39 +0000 (22:45 +0000)]
[LV] Split off memcheck block really at the first check

I've noticed this while trying to move addRuntimeCheck to LoopAccessAnalysis.

I think that the intention was to early exit from the overflow checking before
the code for the memchecks.  This is the entire reason why we compute
FirstCheckInst but then we don't use that as the splitting instruction but the
final check.  Looks like an oversight.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228056 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Fix signed vs. unsigned comparison.
Chandler Carruth [Tue, 3 Feb 2015 22:43:30 +0000 (22:43 +0000)]
[x86] Fix signed vs. unsigned comparison.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228055 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFixed unused variable warning.
Simon Pilgrim [Tue, 3 Feb 2015 22:39:28 +0000 (22:39 +0000)]
Fixed unused variable warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228054 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Marking a bunch of non-encoded instructions with isCodeGenOnly = 1.
Colin LeMahieu [Tue, 3 Feb 2015 22:09:51 +0000 (22:09 +0000)]
[Hexagon] Marking a bunch of non-encoded instructions with isCodeGenOnly = 1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228050 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CMake] add_llvm_library: don't use .imp suffix for import libraries on Windows ...
Hans Wennborg [Tue, 3 Feb 2015 22:08:20 +0000 (22:08 +0000)]
[CMake] add_llvm_library: don't use .imp suffix for import libraries on Windows (PR22334)

This was added in r188351 to fix a naming conflict between the
profile_rt-static and profile_rt-shared who both ended up in
lib/profile_rt.lib.

The change also affected other libraries (like libclang), and
users are reporting that they find it surprising that there's
no longer a libclang.lib. Since the profile_rt naming conflict
doesn't seem to exist any more, I think we can remove this.

Differential Revision: http://reviews.llvm.org/D7391

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228049 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PBQP] Constify Graph::getEdgeNode1Id and Graph::getEdgeNode2Id
Arnaud A. de Grandmaison [Tue, 3 Feb 2015 22:02:45 +0000 (22:02 +0000)]
[PBQP] Constify Graph::getEdgeNode1Id and Graph::getEdgeNode2Id

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228048 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][SSE] psrl(w/d/q) and psll(w/d/q) bit shifts for SSE2
Simon Pilgrim [Tue, 3 Feb 2015 21:58:29 +0000 (21:58 +0000)]
[X86][SSE] psrl(w/d/q) and psll(w/d/q) bit shifts for SSE2

Patch to match cases where shuffle masks can be reduced to bit shifts. Similar to byte shift shuffle matching from D5699.

Differential Revision: http://reviews.llvm.org/D6649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228047 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Implement the vpopcnt instructions for POWER8
Bill Schmidt [Tue, 3 Feb 2015 21:58:23 +0000 (21:58 +0000)]
[PowerPC] Implement the vpopcnt instructions for POWER8

Patch by Kit Barton.

Add the vector population count instructions for byte, halfword, word,
and doubleword sizes.  There are two major changes here:

    PPCISelLowering.cpp: Make CTPOP legal for vector types.
    PPCRegisterInfo.td: Added v2i64 to the VRRC register
      definition. This is needed for the doubleword variations of the
      integer ops that were added in P8.

Test Plan

Test the instruction vpcnt* encoding/decoding in ppc64-encoding-vmx.s

Test the generation of the vpopcnt instructions for various vector
data types.  When adding the v2i64 type to the Vector Register set, I
also needed to add the appropriate bit conversion patterns between
v2i64 and the existing vector types.  Testing for these conversions
were also added in the test case by passing a different vector type as
a parameter into the test functions.  There is also a run step that
will ensure the vpopcnt instructions are generated when the vsx
feature is disabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228046 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[fuzzer] Add proper dependensices to the fuzzer tests
Kostya Serebryany [Tue, 3 Feb 2015 21:57:32 +0000 (21:57 +0000)]
[fuzzer] Add proper dependensices to the fuzzer tests

Summary: Make sure that FileCheck is built when running check-fuzzer

Test Plan:
run on bot:
lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fuzzer

Reviewers: samsonov

Reviewed By: samsonov

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7387

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228045 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Add two truly horrific test cases for the new vector shuffle
Chandler Carruth [Tue, 3 Feb 2015 21:56:28 +0000 (21:56 +0000)]
[x86] Add two truly horrific test cases for the new vector shuffle
lowering. I'm prepping patches to improve these, and this will let the
delta of those patches show the improvement. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228044 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Update the indent and layout of some tests in this file. NFC
Chandler Carruth [Tue, 3 Feb 2015 21:56:24 +0000 (21:56 +0000)]
[x86] Update the indent and layout of some tests in this file. NFC

This is just to remove voise from using the update_llc_test_checks
script.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228043 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAsmParser: Recognize DW_TAG_* constants
Duncan P. N. Exon Smith [Tue, 3 Feb 2015 21:56:01 +0000 (21:56 +0000)]
AsmParser: Recognize DW_TAG_* constants

Recognize `DW_TAG_` constants in assembly, and output it by default for
`GenericDebugNode`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228042 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIR: Assembly and bitcode for GenericDebugNode
Duncan P. N. Exon Smith [Tue, 3 Feb 2015 21:54:14 +0000 (21:54 +0000)]
IR: Assembly and bitcode for GenericDebugNode

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228041 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Remove the -CHECK suffix from all FileCheck prefixes in LIT tests
Marek Olsak [Tue, 3 Feb 2015 21:53:27 +0000 (21:53 +0000)]
R600/SI: Remove the -CHECK suffix from all FileCheck prefixes in LIT tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228040 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Remove useless patterns in VALU which are already covered by SALU
Marek Olsak [Tue, 3 Feb 2015 21:53:08 +0000 (21:53 +0000)]
R600/SI: Remove useless patterns in VALU which are already covered by SALU

Also remove hasPostISelHook=1 from V_LSHL_B32. It's defined by InstSI already.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228039 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Rewrite VOP1InstSI to contain a pseudo and _si opcode
Marek Olsak [Tue, 3 Feb 2015 21:53:05 +0000 (21:53 +0000)]
R600/SI: Rewrite VOP1InstSI to contain a pseudo and _si opcode

What this does is that if you accidentally select these instructions on VI,
the code generation will fail, because the pseudo -> _vi mapping will be
undefined.

The idea is to be able to catch possible future bugs easily.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228038 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Fix B64 VALU shifts on VI
Marek Olsak [Tue, 3 Feb 2015 21:53:01 +0000 (21:53 +0000)]
R600/SI: Fix B64 VALU shifts on VI

SI only has standard versions. VI only has REV versions.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228037 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoInstrProf: Remove CoverageMapping::HasCodeBefore, it isn't used
Justin Bogner [Tue, 3 Feb 2015 21:35:36 +0000 (21:35 +0000)]
InstrProf: Remove CoverageMapping::HasCodeBefore, it isn't used

It's not entirely clear to me what this field was meant for, but it's
always false. Remove it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228034 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Tweak my update script to use test case function names starting
Chandler Carruth [Tue, 3 Feb 2015 21:26:45 +0000 (21:26 +0000)]
[x86] Tweak my update script to use test case function names starting
with 'stress' to indicate that the specific output isn't interesting and
relax them to only check the last instruction (a ret).

I've updated the one test case that really uses this to name the one
'stress_test' which was actually producing output we can directly check.
With this, the script doesn't introduce noise when run over the v16 test
file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228033 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSupport: Add string => unsigned mapping for DW_TAG
Duncan P. N. Exon Smith [Tue, 3 Feb 2015 21:16:49 +0000 (21:16 +0000)]
Support: Add string => unsigned mapping for DW_TAG

Add `dwarf::getTag()` to translate from `StringRef` to `unsigned`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228031 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSupport: Re-implement dwarf::TagString() using a .def file, NFC
Duncan P. N. Exon Smith [Tue, 3 Feb 2015 21:13:16 +0000 (21:13 +0000)]
Support: Re-implement dwarf::TagString() using a .def file, NFC

Also re-implements the `dwarf::Tag` enumerator.  I've moved the mock
tags into the enumerator since there's no other way to do this.  Really
they shouldn't be used at all (they're just a hack to identify
`MDNode`s, but we have a class hierarchy for that now).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228030 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSupport: Stop stringifying DW_TAG_{lo,hi}_user
Duncan P. N. Exon Smith [Tue, 3 Feb 2015 21:08:33 +0000 (21:08 +0000)]
Support: Stop stringifying DW_TAG_{lo,hi}_user

`dwarf::TagString()` shouldn't stringify `DW_TAG_lo_user` or
`DW_TAG_hi_user`.  These aren't actual tags; they're markers for the
edge of vendor-specific tag regions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228029 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFixed signed/unsigned comparison warning.
Simon Pilgrim [Tue, 3 Feb 2015 20:54:01 +0000 (20:54 +0000)]
Fixed signed/unsigned comparison warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228027 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Converting XTYPE/SHIFT intrinsics. Cleaning out old intrinsic patterns...
Colin LeMahieu [Tue, 3 Feb 2015 20:40:52 +0000 (20:40 +0000)]
[Hexagon] Converting XTYPE/SHIFT intrinsics.  Cleaning out old intrinsic patterns and updating tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228026 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFixed unused variable warning.
Simon Pilgrim [Tue, 3 Feb 2015 20:38:52 +0000 (20:38 +0000)]
Fixed unused variable warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228025 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAllow PRE to insert no-cost phi nodes
Daniel Berlin [Tue, 3 Feb 2015 20:37:08 +0000 (20:37 +0000)]
Allow PRE to insert no-cost phi nodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228024 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][SSE] Added general integer shuffle matching for MOVQ instruction
Simon Pilgrim [Tue, 3 Feb 2015 20:09:18 +0000 (20:09 +0000)]
[X86][SSE] Added general integer shuffle matching for MOVQ instruction

This patch adds general shuffle pattern matching for the MOVQ zero-extend instruction (copy lower 64bits, zero upper) for all 128-bit integer vectors, it is added as a fallback test in lowerVectorShuffleAsZeroOrAnyExtend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228022 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Updating XTYPE/PRED intrinsics.
Colin LeMahieu [Tue, 3 Feb 2015 19:43:59 +0000 (19:43 +0000)]
[Hexagon] Updating XTYPE/PRED intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228019 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[fuzzer] update the include line to use the new header name
Kostya Serebryany [Tue, 3 Feb 2015 19:42:05 +0000 (19:42 +0000)]
[fuzzer] update the include line to use the new header name

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228018 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd straight-line strength reduction to LLVM
Jingyue Wu [Tue, 3 Feb 2015 19:37:06 +0000 (19:37 +0000)]
Add straight-line strength reduction to LLVM

Summary:
Straight-line strength reduction (SLSR) is implemented in GCC but not yet in
LLVM. It has proven to effectively simplify statements derived from an unrolled
loop, and can potentially benefit many other cases too. For example,

LLVM unrolls

  #pragma unroll
  foo (int i = 0; i < 3; ++i) {
    sum += foo((b + i) * s);
  }

into

  sum += foo(b * s);
  sum += foo((b + 1) * s);
  sum += foo((b + 2) * s);

However, no optimizations yet reduce the internal redundancy of the three
expressions:

  b * s
  (b + 1) * s
  (b + 2) * s

With SLSR, LLVM can optimize these three expressions into:

  t1 = b * s
  t2 = t1 + s
  t3 = t2 + s

This commit is only an initial step towards implementing a series of such
optimizations. I will implement more (see TODO in the file commentary) in the
near future. This optimization is enabled for the NVPTX backend for now.
However, I am more than happy to push it to the standard optimization pipeline
after more thorough performance tests.

Test Plan: test/StraightLineStrengthReduce/slsr.ll

Reviewers: eliben, HaoLiu, meheff, hfinkel, jholewinski, atrick

Reviewed By: jholewinski, atrick

Subscribers: karthikthecool, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D7310

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228016 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Updating XTYPE/PERM intrinsics.
Colin LeMahieu [Tue, 3 Feb 2015 19:36:59 +0000 (19:36 +0000)]
[Hexagon] Updating XTYPE/PERM intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228015 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][AVX2] Enabled shuffle matching for the AVX2 zero extension (128bit -> 256bit...
Simon Pilgrim [Tue, 3 Feb 2015 19:34:09 +0000 (19:34 +0000)]
[X86][AVX2] Enabled shuffle matching for the AVX2 zero extension (128bit -> 256bit) vpmovzx* instructions.

Differential Revision: http://reviews.llvm.org/D7251

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228014 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix duplicated symbol error.
Rafael Espindola [Tue, 3 Feb 2015 19:25:53 +0000 (19:25 +0000)]
Fix duplicated symbol error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228012 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix typo in test/CodeGen/X86/sibcall.ll (pr22331).
Rafael Espindola [Tue, 3 Feb 2015 19:20:26 +0000 (19:20 +0000)]
Fix typo in test/CodeGen/X86/sibcall.ll (pr22331).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228011 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding missing vector multiply instruction encodings. Converting multiply...
Colin LeMahieu [Tue, 3 Feb 2015 19:15:11 +0000 (19:15 +0000)]
[Hexagon] Adding missing vector multiply instruction encodings.  Converting multiply intrinsics and updating tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228010 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMerge consecutive 16-byte loads into one 32-byte load (PR22329)
Sanjay Patel [Tue, 3 Feb 2015 18:54:00 +0000 (18:54 +0000)]
Merge consecutive 16-byte loads into one 32-byte load (PR22329)

This patch detects consecutive vector loads using the existing
EltsFromConsecutiveLoads() logic. This fixes:
http://llvm.org/bugs/show_bug.cgi?id=22329

This patch effectively reverts the tablegen additions of D6492 /
http://reviews.llvm.org/rL224344 ...which in hindsight were a horrible hack.

The test cases that were added with that patch are simply modified to load
from varying offsets of a base pointer. These loads did not match the existing
tablegen patterns.

A happy side effect of doing this optimization earlier is that we can now fold
the load into a math op where possible; this is shown in some of the updated
checks in the test file.

Differential Revision: http://reviews.llvm.org/D7303

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228006 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoremove variable names from comments; NFC
Sanjay Patel [Tue, 3 Feb 2015 18:47:32 +0000 (18:47 +0000)]
remove variable names from comments; NFC

I didn't bother to fix the self-referential definitions and grammar
because my eyes started to bleed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228004 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LTO API] split lto_codegen_compile to lto_codegen_optimize and
Manman Ren [Tue, 3 Feb 2015 18:39:15 +0000 (18:39 +0000)]
[LTO API] split lto_codegen_compile to lto_codegen_optimize and
lto_codegen_compile_optimized. Also add lto_api_version.

Before this commit, we can only dump the optimized bitcode after running
lto_codegen_compile, but it includes some impacts of running codegen passes,
one example is StackProtector pass. We will get assertion failure when running
llc on the optimized bitcode, because StackProtector is effectively run twice.

After splitting lto_codegen_compile, the linker can choose to dump the bitcode
before running lto_codegen_compile_optimized.

lto_api_version is added so ld64 can check for runtime-availability of the new
API.

rdar://19565500

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228000 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix ProgramFiles path for 64-bit Windows installer
Hans Wennborg [Tue, 3 Feb 2015 18:31:29 +0000 (18:31 +0000)]
Fix ProgramFiles path for 64-bit Windows installer

If we are building an 64bit installer on Windows we have to adjust the
Program Files path otherwise it uses the wrong Program Files (x86)
directory. Related CMake bug report
http://public.kitware.com/Bug/view.php?id=14211

Patch by Ismail Dönmez!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227999 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Converting complex number intrinsics and adding tests.
Colin LeMahieu [Tue, 3 Feb 2015 18:16:28 +0000 (18:16 +0000)]
[Hexagon] Converting complex number intrinsics and adding tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227995 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding vector intrinsics for alu32/alu and xtype/alu.
Colin LeMahieu [Tue, 3 Feb 2015 18:01:45 +0000 (18:01 +0000)]
[Hexagon] Adding vector intrinsics for alu32/alu and xtype/alu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227993 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LoopVectorize] Fix rebase glitch in r227751
Adam Nemet [Tue, 3 Feb 2015 17:59:53 +0000 (17:59 +0000)]
[LoopVectorize] Fix rebase glitch in r227751

LoopVectorizationLegality::{getNumLoads,getNumStores} should forward to
LoopAccessAnalysis now.

Thanks to Takumi for noticing this!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227992 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove usernames from TODOs, NFC
Jingyue Wu [Tue, 3 Feb 2015 17:57:38 +0000 (17:57 +0000)]
Remove usernames from TODOs, NFC

making the style consistent with the rest

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227991 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI
Marek Olsak [Tue, 3 Feb 2015 17:38:12 +0000 (17:38 +0000)]
R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI

This can happen when a REV instruction is commuted.

The trick is not to define the _vi versions of instructions, which has these
consequences:
- code generation will always fail if a pseudo cannot be lowered
  (very useful to catch bugs where an unsupported instruction somehow makes
   it to the printer)
- ability to query if a pseudo can be lowered, which is done in commuteOpcode
  to prevent REV from commuting to non-REV on VI

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227990 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Remove VOP2_REV definitions from target-specific instructions
Marek Olsak [Tue, 3 Feb 2015 17:38:05 +0000 (17:38 +0000)]
R600/SI: Remove VOP2_REV definitions from target-specific instructions

The getCommute* functions are only used with pseudos, so this commit doesn't
change anything.

The issue with missing non-rev versions of shift instructions on VI will fixed
separately.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227989 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Trivial instruction definition corrections for VI (v2)
Marek Olsak [Tue, 3 Feb 2015 17:38:01 +0000 (17:38 +0000)]
R600/SI: Trivial instruction definition corrections for VI (v2)

- V_MAC_LEGACY_F32 exists on VI, but it's VOP3-only.

- Define CVT_PK opcodes which are different between SI and VI. These are
  unused. The idea is to define all chip differences.

v2: keep V_MUL_LO_U32

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227988 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2
Marek Olsak [Tue, 3 Feb 2015 17:37:57 +0000 (17:37 +0000)]
R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2

These are VOP2 on SI and VOP3 on VI, and their pseudos are neither, which can
be a problem. In order to make isVOP2 and isVOP3 queries behave as expected,
the encoding must be determined first.

This doesn't fix any known issue, but better safe than sorry.

v2: add and use getMCOpcodeFromPseudo

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227987 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Fix dependency between instruction writing M0 and S_SENDMSG on VI (v2)
Marek Olsak [Tue, 3 Feb 2015 17:37:52 +0000 (17:37 +0000)]
R600/SI: Fix dependency between instruction writing M0 and S_SENDMSG on VI (v2)

This fixes a hang when using an empty geometry shader.

v2: - don't add s_nop when followed by s_waitcnt
    - comestic changes

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227986 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix program crashes due to alignment exceptions generated for SSE memop instructions...
Sanjay Patel [Tue, 3 Feb 2015 17:13:04 +0000 (17:13 +0000)]
Fix program crashes due to alignment exceptions generated for SSE memop instructions (PR22371).

r224330 introduced a bug by misinterpreting the "FeatureVectorUAMem" bit.
The commit log says that change did not affect anything, but that's not correct.
That change allowed SSE instructions to have unaligned mem operands folded into
math ops, and that's not allowed in the default specification for any SSE variant.

The bug is exposed when compiling for an AVX-capable CPU that had this feature
flag but without enabling AVX codegen. Another mistake in r224330 was not adding
the feature flag to all AVX CPUs; the AMD chips were excluded.

This is part of the fix for PR22371 ( http://llvm.org/bugs/show_bug.cgi?id=22371 ).

This feature bit is SSE-specific, so I've renamed it to "FeatureSSEUnalignedMem".
Changed the existing test case for the feature bit to reflect the new name and
renamed the test file itself to better reflect the feature.
Added runs to fold-vex.ll to check for the failing codegen.

Note that the feature bit is not set by default on any CPU because it may require a
configuration register setting to enable the enhanced unaligned behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227983 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDisable 32-bit tests in tls-pic.ll until they can be repaired
Bill Schmidt [Tue, 3 Feb 2015 16:57:38 +0000 (16:57 +0000)]
Disable 32-bit tests in tls-pic.ll until they can be repaired

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227981 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFurther revise too-restrictive test CodeGen/PowerPC/tls-pic.ll
Bill Schmidt [Tue, 3 Feb 2015 16:33:55 +0000 (16:33 +0000)]
Further revise too-restrictive test CodeGen/PowerPC/tls-pic.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227980 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFurther revise too-restrictive test CodeGen/PowerPC/tls-pic.ll
Bill Schmidt [Tue, 3 Feb 2015 16:29:52 +0000 (16:29 +0000)]
Further revise too-restrictive test CodeGen/PowerPC/tls-pic.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227978 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevise too-restrictive test CodeGen/PowerPC/tls-pic.ll
Bill Schmidt [Tue, 3 Feb 2015 16:24:05 +0000 (16:24 +0000)]
Revise too-restrictive test CodeGen/PowerPC/tls-pic.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227977 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Yet another approach to __tls_get_addr
Bill Schmidt [Tue, 3 Feb 2015 16:16:01 +0000 (16:16 +0000)]
[PowerPC] Yet another approach to __tls_get_addr

This patch is a third attempt to properly handle the local-dynamic and
global-dynamic TLS models.

In my original implementation, calls to __tls_get_addr were hidden
from view until the asm-printer phase, at which point the underlying
branch-and-link instruction was created with proper relocations.  This
mostly worked well, but I used some repellent techniques to ensure
that the TLS_GET_ADDR nodes at the SD and MI levels correctly received
input from GPR3 and produced output into GPR3.  This proved to work
badly in the presence of multiple TLS variable accesses, with the
copies to and from GPR3 being scheduled incorrectly and generally
creating havoc.

In r221703, I addressed that problem by representing the calls to
__tls_get_addr as true calls during instruction lowering.  This had
the advantage of removing all of the bad hacks and relying on the
existing call machinery to properly glue the copies in place. It
looked like this was going to be the right way to go.

However, as a side effect of the recent discovery of problems with
linker optimizations for TLS, we discovered cases of suboptimal code
generation with this strategy.  The problem comes when tls_get_addr is
called for the same address, and there is a resulting CSE
opportunity.  It turns out that in such cases MachineCSE will common
the addis/addi instructions that set up the input value to
tls_get_addr, but will not common the calls themselves.  MachineCSE
does not have any machinery to common idempotent calls.  This is
perfectly sensible, since presumably this would be done at the IR
level, and introducing calls in the back end isn't commonplace.  In
any case, we end up with two calls to __tls_get_addr when one would
suffice, and that isn't good.

I presumed that the original design would have allowed commoning of
the machine-specific nodes that hid the __tls_get_addr calls, so as
suggested by Ulrich Weigand, I went back to that design and cleaned it
up so that the copies were properly held together by glue
nodes.  However, it turned out that this didn't work either...the
presence of copies to physical registers kept the machine-specific
nodes from being commoned also.

All of which leads to the design presented here.  This is a return to
the original design, except that no attempt is made to introduce
copies to and from GPR3 during instruction lowering.  Virtual registers
are used until prior to register allocation.  At that point, a special
pass is run that identifies the machine-specific nodes that hide the
tls_get_addr calls and introduces the copies to and from GPR3 around
them.  The register allocator then coalesces these copies away.  With
this design, MachineCSE succeeds in commoning tls_get_addr calls where
possible, and we get nice optimal code generation (better than GCC at
the moment, which does not common these calls).

One additional problem must be dealt with:  After introducing the
mentions of the physical register GPR3, the aggressive anti-dependence
breaker sees opportunities to improve scheduling by selecting a
different register instead.  Flags must be used on the instruction
descriptions to tell the anti-dependence breaker to keep its hands in
its pockets.

One thing missing from the original design was recording a definition
of the link register on the GET_TLS_ADDR nodes.  Doing this was found
to be insufficient to force a stack frame to be created, which led to
looping behavior because two different LR values were stored at the
same address.  This appears to have been an oversight in
PPCFrameLowering::determineFrameLayout(), which is repaired here.

Because MustSaveLR() returns true for calls to builtin_return_address,
this changed the expected behavior of
test/CodeGen/PowerPC/retaddr2.ll, which now stacks a frame but
formerly did not.  I've fixed the test case to reflect this.

There are existing TLS tests to catch regressions; the checks in
test/CodeGen/PowerPC/tls-store2.ll proved to be too restrictive in the
face of instruction scheduling with these changes, so I fixed that
up.

I've added a new test case based on the PrettyStackTrace module that
demonstrated the original problem. This checks that we get correct
code generation and that CSE of the calls to __get_tls_addr has taken
place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227976 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoImprove test to actually check for a folded load.
Sanjay Patel [Tue, 3 Feb 2015 15:37:18 +0000 (15:37 +0000)]
Improve test to actually check for a folded load.

This test was checking for lack of a "movaps" (an aligned load)
rather than a "movups" (an unaligned load). It also included
a store which complicated the checking.

Add specific CPU runs to prevent subtarget feature flag overrides
from inhibiting this optimization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227972 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][MMX] Improve transfer from mmx to i32
Bruno Cardoso Lopes [Tue, 3 Feb 2015 14:46:49 +0000 (14:46 +0000)]
[X86][MMX] Improve transfer from mmx to i32

Improve EXTRACT_VECTOR_ELT DAG combine to catch conversion patterns
between x86mmx and i32 with more layers of indirection.

Before:
  movq2dq %mm0, %xmm0
  movd %xmm0, %eax
After:
  movd %mm0, %eax

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227969 91177308-0d34-0410-b5e6-96231b3b80d8