Use getAnyExtOrTrunc helper instead of manually doing ext/trunc check. NFC.
[oota-llvm.git] / lib / Target /
2015-07-15 Pete CooperChange conditional to assert. NFC.
2015-07-14 Pete CooperUse more foreach loops in SelectionDAG. NFC
2015-07-14 JF BastienWebAssembly: fix build breakage.
2015-07-14 Hal Finkel[PowerPC] Support symbolic targets in patchpoints
2015-07-14 Hal Finkel[PowerPC] Use the ABI indirect-call protocol for patchp...
2015-07-14 Pete CooperAdd allnodes() iterator range to SelectionDAG. NFC.
2015-07-14 JF BastienWebAssembly: add basic int/fp instruction codegen.
2015-07-14 Krzysztof ParzyszekFix NDEBUG build warning
2015-07-14 Krzysztof ParzyszekFix Windows build: replace __func__ with LLVM_FUNCTION_NAME
2015-07-14 Bruno Cardoso Lopes[MMX] Use the appropriate instructions for GR64 <-...
2015-07-14 Hal Finkel[PowerPC] Fix the PPCInstrInfo::getInstrLatency impleme...
2015-07-14 Krzysztof Parzyszek[Hexagon] Generate instructions for operations on predi...
2015-07-14 Matt ArsenaultAMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
2015-07-14 Matt ArsenaultAMDGPU/SI: Fix read2 merging into a super register.
2015-07-14 Matthias BraunMachineRegisterInfo: Remove UsedPhysReg infrastructure
2015-07-14 Nemanja IvanovicAdd missing builtins to the PPC back end for ABI compli...
2015-07-14 Matthias BraunPrologEpilogInserter: Rewrite API to determine callee...
2015-07-14 Tim NorthoverAArch64: add rev64 alias for 64-bit rev instruction.
2015-07-14 Krzysztof Parzyszek[Hexagon] Generate "extract" instructions more aggressively
2015-07-14 Hans WennborgARMAsmParser: Take MCInst param by const-ref
2015-07-14 Tom StellardAMDGPU/SI: Add support for shrinking v_cndmask_b32_e32...
2015-07-14 Aaron BallmanSilencing two MSVC warnings; 'argument' : truncation...
2015-07-14 Daniel Sanders[mips] Fix li/la differences between IAS and GAS.
2015-07-14 Yaron KerenGenerate correct asm info for mingw and cygwin ARM...
2015-07-14 NAKAMURA TakumiPrune trailing whitespaces and CRs.
2015-07-13 Bill Schmidt[PPC64LE] More improvements to VSX swap optimization
2015-07-13 Benjamin Kramer[Hexagon] Move BitTracker into the llvm namespace and...
2015-07-13 Matt ArsenaultAMDGPU: Minor cleanups to always inline pass
2015-07-13 Mark HeffernanEnable partial and runtime loop unrolling for NVPTX.
2015-07-13 Reid Kleckner[WinEH] Strip the \01 character from the __CxxFrameHand...
2015-07-13 Tom StellardAMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 Logan ChienARM: Fix cttz expansion on vector types.
2015-07-13 Scott Douglass[ARM] Handle commutativity when converting to tADDhirr...
2015-07-13 Scott Douglass[ARM] Add Thumb2 ADD with SP narrowing from 3 operand...
2015-07-13 Scott Douglass[ARM] Small refactor of tryConvertingToTwoOperandForm...
2015-07-13 Aaron BallmanRemoving several -Wunused-but-set-variable warnings...
2015-07-13 Elena DemikhovskyAVX-512: Added all AVX-512 forms of Vector Convert...
2015-07-12 Renato Golin[ARM] Add support for nest attribute using r12
2015-07-12 Simon Pilgrim[X86][SSE] (V)PMINSB is commutable.
2015-07-12 Simon PilgrimTrim trailing whitespaces. NFC.
2015-07-12 Simon Pilgrim[X86][SSE] Vectorized v4i32 non-uniform shifts.
2015-07-12 Hal Finkel[PowerPC] Make use of the TargetRecip system
2015-07-12 Hal Finkel[PowerPC] Support the nest parameter attribute
2015-07-10 Duncan P. N. Exon... MC: Only allow changing feature bits in MCSubtargetInfo
2015-07-10 Matt ArsenaultAMDGPU: Fix chains for memory ops dependent on argument...
2015-07-10 Duncan P. N. Exon... MC: Remove MCSubtargetInfo() default constructor
2015-07-10 Duncan P. N. Exon... MC: Remove MCSubtargetInfo::InitCPUSched()
2015-07-10 Matt ArsenaultAMDGPU: Use requested chain when lowering arguments
2015-07-10 Matthias BraunARM: Use SpecificBumpPtrAllocator to fix leak introduce...
2015-07-10 Evgeniy StepanovFix AArch64 prologue for empty frame with dynamic allocas.
2015-07-10 Jingyue Wu[TTI] BasicTTIImpl assumes no vector registers
2015-07-10 Matthias BraunARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor...
2015-07-10 Matthias BraunARMLoadStoreOptimizer: Create LDRD/STRD on thumb2
2015-07-10 JF BastienWebAssembly: basic instructions todo, and basic registe...
2015-07-10 JF BastienTarget RegisterInfo: devirtualize TargetFrameLowering
2015-07-10 Matthias BraunARMLoadStoreOptimizer: Rewrite LDM/STM matching logic.
2015-07-10 Eli BenderskyActually support volatile memcpys in NVPTX lowering
2015-07-10 Nemanja IvanovicNFC. Added a blank line for consistency.
2015-07-10 Nemanja IvanovicAdd missing builtins to the PPC back end for ABI compli...
2015-07-10 Jingyue Wu[NVPTX] declare no vector registers
2015-07-10 Reid Kleckner[WinEH] Make sure LSDA tables are 4 byte aligned
2015-07-09 Eli BenderskyReplace index-loops by range-based loops
2015-07-09 Sanjay Patel[x86] enable machine combiner reassociations for scalar...
2015-07-09 Sanjay Patel[x86] enable machine combiner reassociations for scalar...
2015-07-09 Reid Kleckner[WinEH] Give up on using CSRs across 32-bit invokes...
2015-07-09 Tom StellardAMDGPU: Add helper function for implicit parameter...
2015-07-09 JF BastienUnbreak WebAssembly build
2015-07-09 Matt ArsenaultAMDGPU/R600: Return correct chain when lowering loads
2015-07-09 Pat GavlinAllow {e,r}bp as the target of {read,write}_register.
2015-07-09 Tom StellardAMDGPU/SI: The SIShrinkInstructions pass should only...
2015-07-09 Tom StellardAMDGPU/SI: Fix crash on physical registers in SIInstrIn...
2015-07-09 Krzysztof Parzyszek[Hexagon] Add missing preamble to a source file
2015-07-09 Mehdi AminiRe-instate the EVT parameter to getScalarShiftAmountTy...
2015-07-09 Pawel BylicaReapply fixed r241790: Fix shift legalization and lower...
2015-07-09 Krzysztof Parzyszek[Hexagon] Add support for atomic RMW operations
2015-07-09 Arnaud A. de Grand... [AArch64] Select SBFIZ or UBFIZ instead of left + right...
2015-07-09 Scott Douglass[ARM] Thumb1 3 to 2 operand convertion for commutative...
2015-07-09 Scott Douglass[ARM] Don't be overzealous converting Thumb1 3 to 2...
2015-07-09 Scott Douglass[ARM] Add Thumb2 ADD with PC narrowing from 3 operand...
2015-07-09 Scott Douglass[ARM] Refactor converting Thumb1 from 3 to 2 operand...
2015-07-09 Renato GolinAdd support for nest attribute to AArch64 backend
2015-07-09 Pawel BylicaRevert r241790: Fix shift legalization and lowering...
2015-07-09 Pawel BylicaFix shift legalization and lowering for big constants.
2015-07-09 Mehdi AminiRemove getDataLayout() from TargetSelectionDAGInfo...
2015-07-09 Mehdi AminiRemove getDataLayout() from TargetLowering
2015-07-09 Mehdi AminiMake isLegalAddressingMode() taking DataLayout as an...
2015-07-09 Mehdi AminiMake getByValTypeAlignment() taking DataLayout as an...
2015-07-09 Mehdi AminiMake TargetLowering::getShiftAmountTy() taking DataLayo...
2015-07-09 Mehdi AminiMake TargetLowering::getPointerTy() taking DataLayout...
2015-07-09 Mehdi AminiMake TargetTransformInfo keeping a reference to the...
2015-07-09 Mehdi AminiRedirect DataLayout from TargetMachine to Module in...
2015-07-08 Sanjay Patel[x86] enable machine combiner reassociations for scalar...
2015-07-08 Diego NovilloAdd missing dependency to Hexagon target.
2015-07-08 Reid Kleckner[Win64] Only treat some functions as having the Win64...
2015-07-08 Krzysztof Parzyszek[Hexagon] Implement commoning of GetElementPtr instructions
2015-07-08 Reid Kleckner[SEH] Ensure that empty __except blocks have their...
2015-07-08 Duncan P. N. Exon... MC: Constify MCSubtargetInfo in getDeprecationInfo...
2015-07-08 Eli BenderskyCosmetic cleanups - NFC
2015-07-08 James Y Knight[SPARC] Cleanup handling of the Y/ASR registers.
2015-07-08 Krzysztof Parzyszek[Hexagon] Generate "insert" instructions more aggressively
next