Enabling 3DNow! prefetch instruction for a few AMD processors: bobcat, jaguar,
[oota-llvm.git] / lib / Target / X86 / X86.td
2009-09-20 Chris Lattnerremove a temporary hack.
2009-09-13 Chris Lattnersplit MCInst printing out of the X86ATTInstPrinter
2009-09-02 Chris LattnerAdd support for modeling whether or not the processor...
2009-08-11 Daniel Dunbarllvm-mc/AsmParser: Allow target to specific a comment...
2009-07-29 Daniel DunbarMatch X86 register names to number.
2009-06-29 David GreeneAdd processor descriptions for Istanbul and Shanghai.
2009-06-26 David GreeneAdd feature flags for AVX and FMA and fix some SSE4A...
2009-06-02 Dale JohannesenRevert 72707 and 72709, for the moment.
2009-06-01 Dale JohannesenAdd missing file.
2009-05-26 Stefanus Du ToitUpdate CPU capabilities for AMD machines
2009-02-03 Dan GohmanChange Feature64Bit to not imply FeatureSSE2. All x86...
2009-01-03 Evan ChengAdd Intel processors core i7 and atom.
2009-01-02 Evan ChengDo not isel load folding bt instructions for pentium...
2008-11-24 Evan ChengMove target independent td files from lib/Target/ to...
2008-10-14 Dale JohannesenAccept -march=i586, because gcc does (a synonym
2008-10-11 Anton KorobeynikovAdd ability to override segment (mostly for code emitte...
2008-03-01 Andrew LenharthAdd lock prefix support to x86. Also add the instructi...
2008-02-15 Dale Johannesennocona, core2 and penryn support 64 bit.
2008-02-03 Nate BegemanSSE 4.1 Intrinsics and detection
2007-12-29 Chris LattnerRemove attribution from file headers, per discussion...
2007-10-12 Arnold SchwaighoferCorrected many typing errors. And removed 'nest' parame...
2007-05-22 Bill WendlingWe only need to specify the most-implied feature for...
2007-05-06 Bill Wendling3DNowA implies 3DNow. 64-bit implies SSE1, SSE2, and...
2007-05-04 Bill WendlingAdd an "implies" field to features. This indicates...
2007-04-25 Bill WendlingAdd SSSE3 as a feature of Core2. Add MMX registers...
2007-04-10 Bill WendlingAdd support for our first SSSE3 instruction "pmulhrsw".
2007-02-26 Chris LattnerAdd a description of the X86-64 calling convention...
2006-10-06 Evan ChengStill need to support -mcpu=<> or cross compilation...
2006-10-06 Evan ChengDo away with CPU feature list. Just use CPUID to detect...
2006-09-08 Evan ChengCommitting X86-64 support.
2006-05-18 Evan ChengImmMask should be 3 for a two-bit field; Compact X86II
2006-05-18 Evan ChenggetCalleeSaveRegs and getCalleeSaveRegClasses are no...
2006-05-17 Evan ChengRemove PointerType from class Target
2006-02-01 Evan Cheng- Use xor to clear integer registers (set R, 0).
2006-01-31 Chris Lattner* Fix 80-column violations
2006-01-29 Jeff CohenFix typo.
2006-01-27 Evan Chengx86 CPU detection and proper subtarget support
2006-01-27 Chris LattnerPHI and INLINEASM are now built-in instructions provide...
2006-01-26 Evan ChengAdded preliminary x86 subtarget support.
2005-07-15 Nate BegemanGet closer to fully working scalar FP in SSE regs....
2005-07-06 Nate BegemanFirst round of support for doing scalar FP using the...
2004-10-03 Chris LattnerAdd support for the -x86-asm-syntax flag, which can...
2004-08-11 Chris LattnerRemove a bunch of ad-hoc target-specific flags that...
2004-08-01 Chris LattnerEliminate 3 of the X86 printImplicit* flags.
2004-04-13 Chris LattnerAdd support for the printImplicitDefsBefore flag
2004-04-08 John CriswellAdded the llvm.readport and llvm.writeport intrinsics...
2004-03-31 Chris LattnerAdd FP conditional move instructions, which annoyingly...
2004-02-28 Alkis EvlogimenosEach instruction now has both an ImmType and a MemType...
2003-10-21 John CriswellAdded LLVM copyright header.
2003-08-06 Chris LattnerCompletely eliminate the isVoid TSFlag, shifting over...
2003-08-04 Chris LattnerThere is nothing special about noops anymore
2003-08-04 Chris Lattnertransition to using let instead of set
2003-08-03 Chris LattnerAdd new TableGen instruction definitions
2003-08-03 Chris LattnerAdd Target class for X86 target
2003-08-03 Chris LattnerInitial checkin of X86.td file