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[X86][SSE] Vector integer/float conversion memory folding
[oota-llvm.git]
/
lib
/
Target
/
R600
/
EvergreenInstructions.td
2014-09-11
Aaron Watry
R600: Add cmpxchg instruction for evergreen
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2014-09-11
Aaron Watry
R600: Add LDS_WRXCHG[_RET] instructions for Evergreen.
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2014-09-11
Aaron Watry
R600: Add LDS_MIN_[U]INT[_RET] instructions for Evergreen
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2014-09-11
Aaron Watry
R600: Add LDS_XOR[_RET] instructions for Evergreen
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2014-09-11
Aaron Watry
R600: Add LDS_OR[_RET] instructions for Evergreen
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2014-09-11
Aaron Watry
R600: Add LDS_AND[_RET] instructions for Evergreen
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2014-09-11
Aaron Watry
R600: Add LDS_MAX_[U]INT[_RET] instructions for Evergreen
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2014-09-05
Jan Vesely
R600: Fix FROUND
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2014-07-24
Matt Arsenault
R600: Add FMA instructions for Evergreen
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2014-07-24
Matt Arsenault
R600: Match rcp node on pre-SI
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2014-07-15
Jan Vesely
R600: Implement zero undef variants of ctlz/cttz
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2014-06-17
Tom Stellard
R600/SI: Add a pattern for llvm.AMDGPU.barrier.global
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2014-06-11
Tom Stellard
R600: BCNT_INT is a vector only instruction
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2014-06-10
Matt Arsenault
R600: Use BCNT_INT for evergreen
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2014-06-10
Matt Arsenault
R600: Handle fcopysign
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2014-05-22
Matt Arsenault
R600: Expand mul24 for GPUs without it
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2014-05-22
Matt Arsenault
R600: Expand mad24 for GPUs without it
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2014-04-16
Matt Arsenault
R600: Expand sign extension of vectors.
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2014-04-07
Tom Stellard
R600: Match 24-bit arithmetic patterns in a Target...
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2014-04-03
Tom Stellard
R600: Correct opcode for BFE_INT
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2014-03-31
Matt Arsenault
R600: Add BFE, BFI, and BFM intrinsics to help with...
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2014-03-31
Matt Arsenault
R600: Add target nodes for BFM and BFI
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2014-03-24
Tom Stellard
R600: Reorganize tablegen instruction definitions
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