Make CR spill and restore use a reserved register. These operations cannot use the...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146318 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 3a69f9da284d56b852225dbbc2cfe7103fbcab05..27f7f4a1d723393ce334fc9085974995affb6870 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -464,12 +464,16 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
   MachineBasicBlock &MBB = *MI.getParent();
   DebugLoc dl = MI.getDebugLoc();
 
-  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
-  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
-  const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
-  unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
-  unsigned SrcReg = MI.getOperand(0).getReg();
+  // FIXME: Once LLVM supports creating virtual registers here, or the register
+  // scavenger can return multiple registers, stop using reserved registers
+  // here.
+  (void) SPAdj;
+  (void) RS;
+
   bool LP64 = Subtarget.isPPC64();
+  unsigned Reg = Subtarget.isDarwinABI() ?  (LP64 ? PPC::X2 : PPC::R2) :
+                                            (LP64 ? PPC::X0 : PPC::R0);
+  unsigned SrcReg = MI.getOperand(0).getReg();
 
   // We need to store the CR in the low 4-bits of the saved value. First, issue
   // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
@@ -503,14 +507,18 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
   MachineBasicBlock &MBB = *MI.getParent();
   DebugLoc dl = MI.getDebugLoc();
 
-  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
-  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
-  const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
-  unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
+  // FIXME: Once LLVM supports creating virtual registers here, or the register
+  // scavenger can return multiple registers, stop using reserved registers
+  // here.
+  (void) SPAdj;
+  (void) RS;
+
+  bool LP64 = Subtarget.isPPC64();
+  unsigned Reg = Subtarget.isDarwinABI() ?  (LP64 ? PPC::X2 : PPC::R2) :
+                                            (LP64 ? PPC::X0 : PPC::R0);
   unsigned DestReg = MI.getOperand(0).getReg();
   assert(MI.definesRegister(DestReg) &&
     "RESTORE_CR does not define its destination");
-  bool LP64 = Subtarget.isPPC64();
 
   addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
                               Reg), FrameIndex);

diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
index 62fb71a7497c68b30f381671b0d0afda440e5860..3c0193891e00e934c48682da330cff36ca15d42f 100644 (file)
--- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
+++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
@@ -6,11 +6,11 @@ target triple = "powerpc-apple-darwin9.6"
 
 define void @foo() nounwind {
 entry:
-;CHECK:  lis r4, 1
-;CHECK:  ori r4, r4, 34524
-;CHECK:  mfcr r3
-;CHECK:  rlwinm r3, r3, 8, 0, 31
-;CHECK:  stwx r3, r1, r4
+;CHECK:  lis r3, 1
+;CHECK:  ori r3, r3, 34524
+;CHECK:  mfcr r2
+;CHECK:  rlwinm r2, r2, 8, 0, 31
+;CHECK:  stwx r2, r1, r3
   %x = alloca [100000 x i8]                       ; <[100000 x i8]*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
   %x1 = bitcast [100000 x i8]* %x to i8*          ; <i8*> [#uses=1]
@@ -21,9 +21,9 @@ entry:
 return:                                           ; preds = %entry
 ;CHECK:  lis r3, 1
 ;CHECK:  ori r3, r3, 34524
-;CHECK:  lwzx r3, r1, r3
-;CHECK:  rlwinm r3, r3, 24, 0, 31
-;CHECK:  mtcrf 32, r3
+;CHECK:  lwzx r2, r1, r3
+;CHECK:  rlwinm r2, r2, 24, 0, 31
+;CHECK:  mtcrf 32, r2
   ret void
 }
 

diff --git a/test/CodeGen/PowerPC/ppc32-vaarg.ll b/test/CodeGen/PowerPC/ppc32-vaarg.ll
index 05bbd0148d1eddb1079542c947bf59475617cff5..725c106dd6e42e0b74f342266b0b871f02dfc4c6 100644 (file)
--- a/test/CodeGen/PowerPC/ppc32-vaarg.ll
+++ b/test/CodeGen/PowerPC/ppc32-vaarg.ll
@@ -37,8 +37,8 @@ define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
 ; CHECK-NEXT: stw 3, -24(1)
 ; CHECK-NEXT: stw 8, -28(1)
 ; CHECK-NEXT: stw 6, -32(1)
-; CHECK-NEXT: mfcr 3                          # cr0
-; CHECK-NEXT: stw 3, -36(1)
+; CHECK-NEXT: mfcr 0                          # cr0
+; CHECK-NEXT: stw 0, -36(1)
 ; CHECK-NEXT: blt 0, .LBB0_4
 ; CHECK-NEXT: # BB#3:                                 # %entry
 ; CHECK-NEXT: lwz 3, -20(1)
@@ -52,8 +52,8 @@ define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
 ; CHECK-NEXT: slwi 5, 3, 2
 ; CHECK-NEXT: lwz 6, -16(1)
 ; CHECK-NEXT: add 5, 6, 5
-; CHECK-NEXT: lwz 3, -36(1)
-; CHECK-NEXT: mtcrf 128, 3
+; CHECK-NEXT: lwz 0, -36(1)
+; CHECK-NEXT: mtcrf 128, 0
 ; CHECK-NEXT: stw 5, -40(1)
 ; CHECK-NEXT: blt 0, .LBB0_6
 ; CHECK-NEXT: # BB#5:                                 # %entry
@@ -82,8 +82,8 @@ define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
 ; CHECK-NEXT: stw 4, -52(1)
 ; CHECK-NEXT: stw 6, -56(1)
 ; CHECK-NEXT: stw 8, -60(1)
-; CHECK-NEXT: mfcr 3                          # cr0
-; CHECK-NEXT: stw 3, -64(1)
+; CHECK-NEXT: mfcr 0                          # cr0
+; CHECK-NEXT: stw 0, -64(1)
 ; CHECK-NEXT: blt 0, .LBB0_8
 ; CHECK-NEXT: # BB#7:                                 # %entry
 ; CHECK-NEXT: lwz 3, -48(1)
@@ -97,8 +97,8 @@ define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
 ; CHECK-NEXT: lwz 6, -56(1)
 ; CHECK-NEXT: add 5, 6, 5
 ; CHECK-NEXT: addi 5, 5, 32
-; CHECK-NEXT: lwz 3, -64(1)
-; CHECK-NEXT: mtcrf 128, 3
+; CHECK-NEXT: lwz 0, -64(1)
+; CHECK-NEXT: mtcrf 128, 0
 ; CHECK-NEXT: stw 5, -68(1)
 ; CHECK-NEXT: blt 0, .LBB0_10
 ; CHECK-NEXT: # BB#9:                                 # %entry
@@ -122,8 +122,8 @@ define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
 ; CHECK-NEXT: mr 8, 5
 ; CHECK-NEXT: stw 4, -72(1)
 ; CHECK-NEXT: stw 6, -76(1)
-; CHECK-NEXT: mfcr 3                          # cr0
-; CHECK-NEXT: stw 3, -80(1)
+; CHECK-NEXT: mfcr 0                          # cr0
+; CHECK-NEXT: stw 0, -80(1)
 ; CHECK-NEXT: stw 5, -84(1)
 ; CHECK-NEXT: stw 8, -88(1)
 ; CHECK-NEXT: stw 7, -92(1)
@@ -139,8 +139,8 @@ define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
 ; CHECK-NEXT: slwi 5, 3, 2
 ; CHECK-NEXT: lwz 6, -76(1)
 ; CHECK-NEXT: add 5, 6, 5
-; CHECK-NEXT: lwz 3, -80(1)
-; CHECK-NEXT: mtcrf 128, 3
+; CHECK-NEXT: lwz 0, -80(1)
+; CHECK-NEXT: mtcrf 128, 0
 ; CHECK-NEXT: stw 5, -96(1)
 ; CHECK-NEXT: blt 0, .LBB0_14
 ; CHECK-NEXT: # BB#13:                                # %entry