One ppc32-darwin, a i64 inside a structure can have 32 bit alignment.

Thanks for Iain Sandoe for testing this with the original gcc.

Clang was already getting this right.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197572 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index 3d8fa1c195dc7628681b5829f9246bcbd7f0a0de..9e3f14ccaf01313bc7f87c79bd4be23e0ceddc7c 100644 (file)
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -47,7 +47,8 @@ static std::string getDataLayoutString(const PPCSubtarget &ST) {
 
   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
   // documentation are wrong; these are correct (i.e. "what gcc does").
 
   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
   // documentation are wrong; these are correct (i.e. "what gcc does").

-  Ret += "-i64:64";
+  if (ST.isPPC64() || ST.isSVR4ABI())
+    Ret += "-i64:64";

 
   // Set support for 128 floats depending on the ABI.
   if (!ST.isPPC64() || !ST.isSVR4ABI())
 
   // Set support for 128 floats depending on the ABI.
   if (!ST.isPPC64() || !ST.isSVR4ABI())

diff --git a/test/CodeGen/PowerPC/anon_aggr.ll b/test/CodeGen/PowerPC/anon_aggr.ll
index 94b73aba8ada3614b17c789c1798d1d2b0f98c61..3bae5c6516c989617a27aab33ebcf317f7078550 100644 (file)
--- a/test/CodeGen/PowerPC/anon_aggr.ll
+++ b/test/CodeGen/PowerPC/anon_aggr.ll
@@ -119,9 +119,9 @@ unequal:
 ; CHECK: ld 3, -[[OFFSET1]](1)
 
 ; DARWIN32: _func3:
 ; CHECK: ld 3, -[[OFFSET1]](1)
 
 ; DARWIN32: _func3:

-; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 40
+; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 36

 ; DARWIN32: addi r[[REG2:[0-9]+]], r[[REGSP]], 24
 ; DARWIN32: addi r[[REG2:[0-9]+]], r[[REGSP]], 24

-; DARWIN32: lwz r[[REG3:[0-9]+]], 48(r[[REGSP]])
+; DARWIN32: lwz r[[REG3:[0-9]+]], 44(r[[REGSP]])

 ; DARWIN32: lwz r[[REG4:[0-9]+]], 32(r[[REGSP]])
 ; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
 ; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]
 ; DARWIN32: lwz r[[REG4:[0-9]+]], 32(r[[REGSP]])
 ; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
 ; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]