Sparc backend:

 Rename FLUSH to FLUSHW.
 Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123997 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp
index f78d5fa5070fd071374b0f8cef188ac1018960e2..2767862dc321da3d2cfd57d9d281faaf1438430e 100644 (file)
--- a/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/lib/Target/Sparc/SparcISelLowering.cpp
@@ -721,7 +721,7 @@ const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case SPISD::CALL:       return "SPISD::CALL";
   case SPISD::RET_FLAG:   return "SPISD::RET_FLAG";
   case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
-  case SPISD::FLUSH:      return "SPISD::FLUSH";
+  case SPISD::FLUSHW:     return "SPISD::FLUSHW";
   }
 }
 
@@ -969,9 +969,9 @@ static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
 }
 
 
-static SDValue getFLUSH(SDValue Op, SelectionDAG &DAG) {
+static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
   DebugLoc dl = Op.getDebugLoc();
-  SDValue Chain = DAG.getNode(SPISD::FLUSH,
+  SDValue Chain = DAG.getNode(SPISD::FLUSHW,
                               dl, MVT::Other, DAG.getEntryNode());
   return Chain;
 }
@@ -987,19 +987,19 @@ static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
   uint64_t depth = Op.getConstantOperandVal(0);
 
   SDValue FrameAddr;
-  if (depth == 0) 
+  if (depth == 0)
     FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
   else {
     // flush first to make sure the windowed registers' values are in stack
-    SDValue Chain = getFLUSH(Op, DAG);
+    SDValue Chain = getFLUSHW(Op, DAG);
     FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
-    
+
     for (uint64_t i = 0; i != depth; ++i) {
-      SDValue Ptr = DAG.getNode(ISD::ADD, 
+      SDValue Ptr = DAG.getNode(ISD::ADD,
                                 dl, MVT::i32,
                                 FrameAddr, DAG.getIntPtrConstant(56));
-      FrameAddr = DAG.getLoad(MVT::i32, dl, 
-                              Chain, 
+      FrameAddr = DAG.getLoad(MVT::i32, dl,
+                              Chain,
                               Ptr,
                               MachinePointerInfo(), false, false, 0);
     }
@@ -1018,20 +1018,20 @@ static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
   uint64_t depth = Op.getConstantOperandVal(0);
 
   SDValue RetAddr;
-  if (depth == 0) 
+  if (depth == 0)
     RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
   else {
     // flush first to make sure the windowed registers' values are in stack
-    SDValue Chain = getFLUSH(Op, DAG);
+    SDValue Chain = getFLUSHW(Op, DAG);
     RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT);
-    
+
     for (uint64_t i = 0; i != depth; ++i) {
-      SDValue Ptr = DAG.getNode(ISD::ADD, 
+      SDValue Ptr = DAG.getNode(ISD::ADD,
                                 dl, MVT::i32,
-                                RetAddr, 
+                                RetAddr,
                                 DAG.getIntPtrConstant((i == depth-1)?60:56));
-      RetAddr = DAG.getLoad(MVT::i32, dl, 
-                            Chain, 
+      RetAddr = DAG.getLoad(MVT::i32, dl,
+                            Chain,
                             Ptr,
                             MachinePointerInfo(), false, false, 0);
     }

diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h
index 8b2be7a6b4f943169d9382be1a6df446dbd1bf1e..849e4010af6bcff97738a38bf9900bb38069c633 100644 (file)
--- a/lib/Target/Sparc/SparcISelLowering.h
+++ b/lib/Target/Sparc/SparcISelLowering.h
@@ -37,7 +37,7 @@ namespace llvm {
       CALL,        // A call instruction.
       RET_FLAG,    // Return with a flag operand.
       GLOBAL_BASE_REG, // Global base reg for PIC
-      FLUSH        // FLUSH registers to stack
+      FLUSHW       // FLUSH register windows to stack
     };
   }
 

diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 4f7b7c57680b659d92168e760f0da3d8653723db..ffeb8b55bda7a438fdecfae057641d4502eed178 100644 (file)
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -127,7 +127,7 @@ def call          : SDNode<"SPISD::CALL", SDT_SPCall,
 def retflag       : SDNode<"SPISD::RET_FLAG", SDTNone,
                            [SDNPHasChain, SDNPOptInGlue]>;
 
-def flush         : SDNode<"SPISD::FLUSH", SDTNone,
+def flushw        : SDNode<"SPISD::FLUSHW", SDTNone,
                            [SDNPHasChain]>;
 
 def getPCX        : Operand<i32> {
@@ -221,11 +221,16 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                             [(callseq_end timm:$amt1, timm:$amt2)]>;
 }
 
-let hasSideEffects = 1, mayStore = 1 in
-  let rs2 = 0 in
-    def FLUSH : F3_1<0b10, 0b101011, (outs), (ins),
-                     "flushw",
-                     [(flush)]>;
+let hasSideEffects = 1, mayStore = 1 in {
+  let rd = 0, rs1 = 0, rs2 = 0 in
+    def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
+                      "flushw",
+                      [(flushw)]>, Requires<[HasV9]>;
+  let rd = 0, rs1 = 1, simm13 = 3 in
+    def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
+                   "ta 3",
+                   [(flushw)]>;
+}
 
 // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 
 // fpmover pass.

diff --git a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
index 6c821f3ce96b8bb2628cf2207470fb331d26e834..fbf724270566f9c185f2f98320d270f358f94b19 100644 (file)
--- a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
+++ b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
@@ -1,21 +1,30 @@
-;RUN: llc -march=sparc < %s | FileCheck %s
-
+;RUN: llc -march=sparc < %s | FileCheck %s -check-prefix=V8
+;RUN: llc -march=sparc -mattr=v9 < %s | FileCheck %s -check-prefix=V9
 
 define i8* @frameaddr() nounwind readnone {
 entry:
-;CHECK: frameaddr
-;CHECK: or %g0, %fp, {{.+}}
+;V8: frameaddr
+;V8: or %g0, %fp, {{.+}}
+
+;V9: frameaddr
+;V9: or %g0, %fp, {{.+}}
   %0 = tail call i8* @llvm.frameaddress(i32 0)
   ret i8* %0
 }
 
 define i8* @frameaddr2() nounwind readnone {
 entry:
-;CHECK: frameaddr2
-;CHECK: flushw
-;CHECK: ld [%fp+56], {{.+}}
-;CHECK: ld [{{.+}}+56], {{.+}}
-;CHECK: ld [{{.+}}+56], {{.+}}
+;V8: frameaddr2
+;V8: ta 3
+;V8: ld [%fp+56], {{.+}}
+;V8: ld [{{.+}}+56], {{.+}}
+;V8: ld [{{.+}}+56], {{.+}}
+
+;V9: frameaddr2
+;V9: flushw
+;V9: ld [%fp+56], {{.+}}
+;V9: ld [{{.+}}+56], {{.+}}
+;V9: ld [{{.+}}+56], {{.+}}
   %0 = tail call i8* @llvm.frameaddress(i32 3)
   ret i8* %0
 }
@@ -26,19 +35,28 @@ declare i8* @llvm.frameaddress(i32) nounwind readnone
 
 define i8* @retaddr() nounwind readnone {
 entry:
-;CHECK: retaddr
-;CHECK: or %g0, %i7, {{.+}}
+;V8: retaddr
+;V8: or %g0, %i7, {{.+}}
+
+;V9: retaddr
+;V9: or %g0, %i7, {{.+}}
   %0 = tail call i8* @llvm.returnaddress(i32 0)
   ret i8* %0
 }
 
 define i8* @retaddr2() nounwind readnone {
 entry:
-;CHECK: retaddr2
-;CHECK: flushw
-;CHECK: ld [%fp+56], {{.+}}
-;CHECK: ld [{{.+}}+56], {{.+}}
-;CHECK: ld [{{.+}}+60], {{.+}}
+;V8: retaddr2
+;V8: ta 3
+;V8: ld [%fp+56], {{.+}}
+;V8: ld [{{.+}}+56], {{.+}}
+;V8: ld [{{.+}}+60], {{.+}}
+
+;V9: retaddr2
+;V9: flushw
+;V9: ld [%fp+56], {{.+}}
+;V9: ld [{{.+}}+56], {{.+}}
+;V9: ld [{{.+}}+60], {{.+}}
   %0 = tail call i8* @llvm.returnaddress(i32 3)
   ret i8* %0
 }