Get rid of more dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77227 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h
index e91d1ebf0e5a6321ad6e7edb56281c2a1e1938bc..52f55a88b602f5a6c01b6b30bd4b1309dc662581 100644 (file)
--- a/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -165,9 +165,7 @@ namespace ARMII {
     ADDri,
     ADDrs,
     ADDrr,
-    LDRri,
     MOVr,
-    STRri,
     SUBri,
     SUBrs,
     SUBrr

diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 6ef1fff8d81c5d074dfcf9275c4fbc10f58ea6be..dfad80b56ef834dd7a9cec2828175e76b68f261b 100644 (file)
--- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -1368,7 +1368,7 @@ static bool isCSRestore(MachineInstr *MI,
 
 void ARMBaseRegisterInfo::
 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
-  assert(!STI.isThumb1Only &&
+  assert(!STI.isThumb1Only() &&
          "This emitEpilogue should not be executed for Thumb1!");
 
   MachineBasicBlock::iterator MBBI = prior(MBB.end());

diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index fda9fc23eb294a9221e81019e5108fcc0afa7ab7..e5eb7bc8991d4dc40b3dd985deda1768f556038a 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -68,9 +68,7 @@ getOpcode(ARMII::Op Op) const {
   case ARMII::ADDri: return ARM::ADDri;
   case ARMII::ADDrs: return ARM::ADDrs;
   case ARMII::ADDrr: return ARM::ADDrr;
-  case ARMII::LDRri: return 0;
   case ARMII::MOVr: return ARM::MOVr;
-  case ARMII::STRri: return 0;
   case ARMII::SUBri: return ARM::SUBri;
   case ARMII::SUBrs: return ARM::SUBrs;
   case ARMII::SUBrr: return ARM::SUBrr;

diff --git a/lib/Target/ARM/Thumb1InstrInfo.cpp b/lib/Target/ARM/Thumb1InstrInfo.cpp
index a4e8e9ce7058ca91031d756cc429a3b04369eabc..43381a31525a440efc71fc528dd1b227a7cbe920 100644 (file)
--- a/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -35,9 +35,7 @@ unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const {
   case ARMII::ADDri: return ARM::tADDi8;
   case ARMII::ADDrs: return 0;
   case ARMII::ADDrr: return ARM::tADDrr;
-  case ARMII::LDRri: return 0;
   case ARMII::MOVr: return ARM::tMOVr;
-  case ARMII::STRri: return 0;
   case ARMII::SUBri: return ARM::tSUBi8;
   case ARMII::SUBrs: return 0;
   case ARMII::SUBrr: return ARM::tSUBrr;

diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp
index 45eb29cbb3a2220133597f9dbabefae016eaa877..acb82320df017e87b169a0fb520e108570a71446 100644 (file)
--- a/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -36,9 +36,7 @@ unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const {
   case ARMII::ADDri: return ARM::t2ADDri;
   case ARMII::ADDrs: return ARM::t2ADDrs;
   case ARMII::ADDrr: return ARM::t2ADDrr;
-  case ARMII::LDRri: return ARM::t2LDRi12;
   case ARMII::MOVr: return ARM::t2MOVr;
-  case ARMII::STRri: return ARM::t2STRi12;
   case ARMII::SUBri: return ARM::t2SUBri;
   case ARMII::SUBrs: return ARM::t2SUBrs;
   case ARMII::SUBrr: return ARM::t2SUBrr;