1. In ppc64 mode we need only use one GPR.

2. Float values need to be promoted to double when they are vararg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32074 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index d564ff7b688cf1c78eab6f8aa42ef012510a3a1a..d5129d568871104531b113d2fff88e0314d8fdf4 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1377,6 +1377,12 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
       break;
     case MVT::f32:
     case MVT::f64:
+      if (isVarArg && isPPC64) {
+        // Float varargs need to be promoted to double.
+        if (Arg.getValueType() == MVT::f32)
+          Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
+      }
+    
       if (FPR_idx != NumFPRs) {
         RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
 
@@ -1390,7 +1396,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
             MemOpChains.push_back(Load.getValue(1));
             RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
           }
-          if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) {
+          if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
             SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
             PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
             SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);