+
+/// Add standard target-independent passes that are tightly coupled with
+/// register allocation, including coalescing, machine instruction scheduling,
+/// and register allocation itself.
+///
+/// FIXME: This will become the register allocation "super pass" pipeline.
+void TargetPassConfig::addRegAlloc() {
+ // Perform register allocation.
+ PM.add(createRegisterAllocator(getOptLevel()));
+ printAndVerify("After Register Allocation");
+
+ // Perform stack slot coloring and post-ra machine LICM.
+ if (getOptLevel() != CodeGenOpt::None) {
+ // FIXME: Re-enable coloring with register when it's capable of adding
+ // kill markers.
+ if (!DisableSSC)
+ addPass(StackSlotColoringID);
+
+ // Run post-ra machine LICM to hoist reloads / remats.
+ //
+ // FIXME: can this move into MachineLateOptimization?
+ if (!DisablePostRAMachineLICM)
+ addPass(MachineLICMID);
+
+ printAndVerify("After StackSlotColoring and postra Machine LICM");
+ }
+}
+
+//===---------------------------------------------------------------------===//
+/// Post RegAlloc Pass Configuration
+//===---------------------------------------------------------------------===//
+
+/// Add passes that optimize machine instructions after register allocation.
+void TargetPassConfig::addMachineLateOptimization() {
+ // Branch folding must be run after regalloc and prolog/epilog insertion.
+ if (!DisableBranchFold) {
+ addPass(BranchFolderPassID);
+ printNoVerify("After BranchFolding");
+ }
+
+ // Tail duplication.
+ if (!DisableTailDuplicate) {
+ addPass(TailDuplicateID);
+ printNoVerify("After TailDuplicate");
+ }
+
+ // Copy propagation.
+ if (!DisableCopyProp) {
+ addPass(MachineCopyPropagationID);
+ printNoVerify("After copy propagation pass");
+ }
+}
+
+/// Add standard basic block placement passes.
+void TargetPassConfig::addBlockPlacement() {
+ if (EnableBlockPlacement) {
+ // MachineBlockPlacement is an experimental pass which is disabled by
+ // default currently. Eventually it should subsume CodePlacementOpt, so
+ // when enabled, the other is disabled.
+ addPass(MachineBlockPlacementID);
+ printNoVerify("After MachineBlockPlacement");
+ } else {
+ addPass(CodePlacementOptID);
+ printNoVerify("After CodePlacementOpt");
+ }
+
+ // Run a separate pass to collect block placement statistics.
+ if (EnableBlockPlacementStats) {
+ addPass(MachineBlockPlacementStatsID);
+ printNoVerify("After MachineBlockPlacementStats");
+ }
+}