Fix loop conditionals (MO.isDef() asserts that it's a reg) and

move some constraints around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111594 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index a61fca1f2529184fd59a4dd22db31b20c2ce5fae..6281c3a3b0b3c899ea066eb9fb13d1fbeb403e2e 100644 (file)
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -122,7 +122,8 @@ bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
   // Look to see if our OptionalDef is defining CPSR or CCR.
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    if (MO.isDef() && MO.isReg() && MO.getReg() == ARM::CPSR)
+    if (!MO.isReg() || !MO.isDef()) continue;
+    if (MO.getReg() == ARM::CPSR)
       *CPSR = true;
   }
   return true;