Thumb parsing and encoding for SUB (SP minu immediate).

Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138494 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index a5ddec3d23ed8c584dd2b00449269b4df8fa85e9..837d853f378cac055022ffd0e4e07f8177f309e6 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -335,10 +335,6 @@ def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
   let DecoderMethod = "DecodeThumbAddSPImm";
 }
 
-// Can optionally specify SP as a three operand instruction.
-def : tInstAlias<"add${p} sp, sp, $imm",
-                 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
-
 // SUB sp, sp, #<imm7>
 // FIXME: The encoding and the ASM string don't match up.
 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
@@ -350,6 +346,12 @@ def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
   let DecoderMethod = "DecodeThumbAddSPImm";
 }
 
+// Can optionally specify SP as a three operand instruction.
+def : tInstAlias<"add${p} sp, sp, $imm",
+                 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
+def : tInstAlias<"sub${p} sp, sp, $imm",
+                 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
+
 // ADD <Rm>, sp
 def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$sp), IIC_iALUr,
                   "add", "\t$Rdn, $sp, $Rn", []>,

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 965b39412c8f80abc8c9583e9ce880709f9543c9..50fa8eaa2df18d07ec4b0f927356ac81d7616c92 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -2923,9 +2923,13 @@ bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
       static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
       static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
     return true;
-  // Register-register 'add' for thumb does not have a cc_out operand
-  // when it's an ADD SP, #imm.
-  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
+  // Register-register 'add/sub' for thumb does not have a cc_out operand
+  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
+  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
+  // right, this will result in better diagnostics (which operand is off)
+  // anyway.
+  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
+      (Operands.size() == 5 || Operands.size() == 6) &&
       static_cast<ARMOperand*>(Operands[3])->isReg() &&
       static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
       static_cast<ARMOperand*>(Operands[1])->getReg() == 0)

diff --git a/test/MC/ARM/basic-thumb-instructions.s b/test/MC/ARM/basic-thumb-instructions.s
index ba02ec2902d1a9b9d0d5809a260b9713cbdc61b6..91f8e15c1f4935649f3ed387246ef4bfd292758d 100644 (file)
--- a/test/MC/ARM/basic-thumb-instructions.s
+++ b/test/MC/ARM/basic-thumb-instructions.s
@@ -538,11 +538,13 @@ _func:
 
 
 @------------------------------------------------------------------------------
-@ FIXME: SUB (SP minus immediate)
-@------------------------------------------------------------------------------
-@------------------------------------------------------------------------------
-@ FIXME: SUB (SP minus register)
+@ SUB (SP minus immediate)
 @------------------------------------------------------------------------------
+        sub sp, #12
+        sub sp, sp, #508
+
+@ CHECK: sub   sp, #12                 @ encoding: [0x83,0xb0]
+@ CHECK: sub   sp, #508                @ encoding: [0xff,0xb0]
 
 
 @------------------------------------------------------------------------------