ARM push of a single register encodes as pre-indexed STR.

Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 0b049e911368a4c7497ec42a4f2a7c328c1c48a2..806c384bea96b00cdd538f3b1560eb0c180253cb 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -2879,6 +2879,22 @@ processInstruction(MCInst &Inst,
       Inst = TmpInst;
     }
     break;
+  case ARM::STMDB_UPD:
+    // If this is a store of a single register via a 'push', then we should use
+    // a pre-indexed STR instruction instead, per the ARM ARM.
+    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
+        Inst.getNumOperands() == 5) {
+      MCInst TmpInst;
+      TmpInst.setOpcode(ARM::STR_PRE_IMM);
+      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
+      TmpInst.addOperand(Inst.getOperand(4)); // Rt
+      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
+      TmpInst.addOperand(MCOperand::CreateImm(-4));
+      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
+      TmpInst.addOperand(Inst.getOperand(3));
+      Inst = TmpInst;
+    }
+    break;
   }
 }
 

diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index a8008faa84036319efb1c38ff89a15b1d3add1d4..af04355e94f6b9189077b9496bab5f083f701927 100644 (file)
--- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -88,6 +88,13 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
     printRegisterList(MI, 4, O);
     return;
   }
+  if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
+      MI->getOperand(3).getImm() == -4) {
+    O << '\t' << "push";
+    printPredicateOperand(MI, 4, O);
+    O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
+    return;
+  }
 
   // A8.6.122 POP
   if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&

diff --git a/test/CodeGen/ARM/str_pre-2.ll b/test/CodeGen/ARM/str_pre-2.ll
index 8d0c7a5fe16fd6d576fe5433d9271e55a43bb18c..f4e3a44d56e3ac47df074deee852b9690650f819 100644 (file)
--- a/test/CodeGen/ARM/str_pre-2.ll
+++ b/test/CodeGen/ARM/str_pre-2.ll
@@ -7,7 +7,7 @@
 
 define i64 @t(i64 %a) nounwind readonly {
 entry:
-; CHECK: str lr, [sp, #-4]!
+; CHECK: push {lr}
 ; CHECK: pop {lr}
        %0 = load i64** @b, align 4
        %1 = load i64* %0, align 4

diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index adcecb5b38293b7cdd0b74c077fbf113219adf07..2cec28494548af6a2fcd1bae5cfb876f646bb35b 100644 (file)
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -1071,8 +1071,7 @@ Lforward:
         push {r7}
         push {r7, r8, r9, r10}
 
-@ FIXME: push of a single register should encode as "str r7, [sp, #-4]!"
-@ CHECK-FIXME: push    {r7}                    @ encoding: [0x04,0x70,0x2d,0xe5]
+@ CHECK: push  {r7}                    @ encoding: [0x04,0x70,0x2d,0xe5]
 @ CHECK: push  {r7, r8, r9, r10}       @ encoding: [0x80,0x07,0x2d,0xe9]