Revert r114703 and r114702, removing the isConditionalMove flag from instructions...

reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index 7d53123877b9f65930dd9c4e69e2a144b79156f0..b141a77df4f20539e2b1f6b55c85e668bc40f77c 100644 (file)
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -201,7 +201,6 @@ class Instruction {
   bit isCompare    = 0;     // Is this instruction a comparison instruction?
   bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
-  bit isConditionalMove = 0; // Is this instruction a conditional move instr?
   bit canFoldAsLoad = 0;    // Can this be folded as a simple memory operand?
   bit mayLoad      = 0;     // Is it possible for this inst to read memory?
   bit mayStore     = 0;     // Is it possible for this inst to write memory?

diff --git a/include/llvm/Target/TargetInstrDesc.h b/include/llvm/Target/TargetInstrDesc.h
index ee1ac5ff5d88a601ea86602d6f7966bbd418545b..a127aed8f6dfcd59e266e976e416f6b1db44cf73 100644 (file)
--- a/include/llvm/Target/TargetInstrDesc.h
+++ b/include/llvm/Target/TargetInstrDesc.h
@@ -99,7 +99,6 @@ namespace TID {
     HasOptionalDef,
     Return,
     Call,
-    ConditionalMove,
     Barrier,
     Terminator,
     Branch,
@@ -353,12 +352,6 @@ public:
     return Flags & (1 << TID::Compare);
   }
   
-  /// isConditionalMove - Return true if this instruction can be considered a
-  /// conditional move, like CMOV on X86 or MOVCC on ARM.
-  bool isConditionalMove() const {
-    return Flags & (1 << TID::ConditionalMove);
-  }
-  
   /// isNotDuplicable - Return true if this instruction cannot be safely
   /// duplicated.  For example, if the instruction has a unique labels attached
   /// to it, duplicating it would cause multiple definition errors.

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index e26586e7522e9b87fc874309f440398ebfeb3934..c467df8295339132e1b3251d463a319478cbf882 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -2391,7 +2391,7 @@ def BCCZi64 : PseudoInst<(outs),
 // Conditional moves
 // FIXME: should be able to write a pattern for ARMcmov, but can't use
 // a two-value operand where a dag node expects two operands. :(
-let neverHasSideEffects = 1, isConditionalMove = 1 in {
+let neverHasSideEffects = 1 in {
 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
                 IIC_iCMOVr, "mov", "\t$dst, $true",
       [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
@@ -2415,7 +2415,7 @@ def MOVCCi : AI1<0b1101, (outs GPR:$dst),
                 RegConstraint<"$false = $dst">, UnaryDP {
   let Inst{25} = 1;
 }
-} // neverHasSideEffects, isConditionalMove
+} // neverHasSideEffects
 
 //===----------------------------------------------------------------------===//
 // Atomic operations intrinsics

diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 362d92dd0b921a00d1c17b656e2562b38b37114a..015054b3da27c29a87a55b6ab5e2031a6a110868 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -866,7 +866,7 @@ let usesCustomInserter = 1 in  // Expanded after instruction selection.
 
 
 // 16-bit movcc in IT blocks for Thumb2.
-let neverHasSideEffects = 1, isConditionalMove = 1 in {
+let neverHasSideEffects = 1 in {
 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
                     "mov", "\t$dst, $rhs", []>,
               T1Special<{1,0,?,?}>;
@@ -874,7 +874,7 @@ def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
                     "mov", "\t$dst, $rhs", []>,
               T1General<{1,0,0,?,?}>;
-} // neverHasSideEffects, isConditionalMove
+} // neverHasSideEffects
 
 // tLEApcrel - Load a pc-relative address into a register without offending the
 // assembler.

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 868815774ba9555858aa6a9ea21dac75d2a6e7e1..6a5078c21b677f490ec39caa57445d587d7de5f8 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -2169,7 +2169,7 @@ defm t2TEQ  : T2I_cmp_irs<0b0100, "teq",
 // Conditional moves
 // FIXME: should be able to write a pattern for ARMcmov, but can't use
 // a two-value operand where a dag node expects two operands. :(
-let neverHasSideEffects = 1, isConditionalMove = 1 in {
+let neverHasSideEffects = 1 in {
 def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr,
                    "mov", ".w\t$dst, $true",
    [/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>,
@@ -2221,7 +2221,7 @@ def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$dst),
                              (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
                              IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
                  RegConstraint<"$false = $dst">;
-} // neverHasSideEffects, isConditionalMove
+} // neverHasSideEffects
 
 //===----------------------------------------------------------------------===//
 // Atomic operations intrinsics

diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td
index f892ff7227668ee5b769c9964f85982f9e373dda..1d3f6c8f08c06b96dc8ea72b1200d27c5d5c02c6 100644 (file)
--- a/lib/Target/X86/X86Instr64bit.td
+++ b/lib/Target/X86/X86Instr64bit.td
@@ -1366,7 +1366,7 @@ def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
 } // Defs = [EFLAGS]
 
 // Conditional moves
-let isConditionalMove = 1, Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
+let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
 let isCommutable = 1 in {
 def CMOVB64rr : RI<0x42, MRMSrcReg,       // if <u, GR64 = GR64
                    (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
@@ -1530,7 +1530,7 @@ def CMOVNO64rm : RI<0x41, MRMSrcMem,       // if !overflow, GR64 = [mem64]
                    "cmovno{q}\t{$src2, $dst|$dst, $src2}",
                     [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
                                      X86_COND_NO, EFLAGS))]>, TB;
-} // isConditionalMove, Constraints = "$src1 = $dst"
+} // Constraints = "$src1 = $dst"
 
 // Use sbb to materialize carry flag into a GPR.
 // FIXME: This are pseudo ops that should be replaced with Pat<> patterns.

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index bc3212255f645c6d91ea83cf6e0a2f5711fe17a2..e8669070b8398f0b56e541839c82212db7ff6edb 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -1269,7 +1269,7 @@ let Constraints = "$src1 = $dst" in {
 // Conditional moves
 let Uses = [EFLAGS] in {
 
-let isConditionalMove = 1, Predicates = [HasCMov] in {
+let Predicates = [HasCMov] in {
 let isCommutable = 1 in {
 def CMOVB16rr : I<0x42, MRMSrcReg,       // if <u, GR16 = GR16
                   (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
@@ -1657,7 +1657,7 @@ def CMOVNO32rm : I<0x41, MRMSrcMem,       // if !overflow, GR32 = [mem32]
                    [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
                                     X86_COND_NO, EFLAGS))]>,
                   TB;
-} // isConditionalMove, Predicates = [HasCMov]
+} // Predicates = [HasCMov]
 
 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,

diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp
index b36cf983a5f4da40ede12e742cc11c7948850cba..01a1fe11f5318f0218b04a30cface0830f4290d6 100644 (file)
--- a/utils/TableGen/CodeGenInstruction.cpp
+++ b/utils/TableGen/CodeGenInstruction.cpp
@@ -103,7 +103,6 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
   isBranch     = R->getValueAsBit("isBranch");
   isIndirectBranch = R->getValueAsBit("isIndirectBranch");
   isCompare    = R->getValueAsBit("isCompare");
-  isConditionalMove = R->getValueAsBit("isConditionalMove");
   isBarrier    = R->getValueAsBit("isBarrier");
   isCall       = R->getValueAsBit("isCall");
   canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");

diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h
index e2e29b16cf07236667018f0e88ec08b9588acba2..b02d0d38f975dbae0ef2604537e369351eea4ce7 100644 (file)
--- a/utils/TableGen/CodeGenInstruction.h
+++ b/utils/TableGen/CodeGenInstruction.h
@@ -124,7 +124,6 @@ namespace llvm {
     bool isBranch;
     bool isIndirectBranch;
     bool isCompare;
-    bool isConditionalMove;
     bool isBarrier;
     bool isCall;
     bool canFoldAsLoad;

diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index ce066b96c0e5bba0fd95840dc8eb0653c9ddfcae..4d3aa5e621c9c749347ed86d1d66fd6ce756019f 100644 (file)
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -274,7 +274,6 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   if (Inst.isBarrier)          OS << "|(1<<TID::Barrier)";
   if (Inst.hasDelaySlot)       OS << "|(1<<TID::DelaySlot)";
   if (Inst.isCall)             OS << "|(1<<TID::Call)";
-  if (Inst.isConditionalMove)  OS << "|(1<<TID::ConditionalMove)";
   if (Inst.canFoldAsLoad)      OS << "|(1<<TID::FoldableAsLoad)";
   if (Inst.mayLoad)            OS << "|(1<<TID::MayLoad)";
   if (Inst.mayStore)           OS << "|(1<<TID::MayStore)";