Revert r140097, working on a better approach

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140203 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 4a8b76651102f8dd416c6bcaf5006453a4f1356a..3d0525ca6ada764413ed2cf6d17749f026223959 100644 (file)
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -157,21 +157,6 @@ def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
           (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
 
-// Inserting a 128-bit undef vector into the high part of a 256-bit
-// vector should return the 256-bit vector itself.
-def : Pat<(insert_subvector (v8i32 VR256:$src), undef, (i32 4)),
-          (v8i32 VR256:$src)>;
-def : Pat<(insert_subvector (v8f32 VR256:$src), undef, (i32 4)),
-          (v8f32 VR256:$src)>;
-def : Pat<(insert_subvector (v4i64 VR256:$src), undef, (i32 4)),
-          (v4i64 VR256:$src)>;
-def : Pat<(insert_subvector (v4f64 VR256:$src), undef, (i32 4)),
-          (v4f64 VR256:$src)>;
-def : Pat<(insert_subvector (v16i16 VR256:$src), undef, (i32 4)),
-          (v16i16 VR256:$src)>;
-def : Pat<(insert_subvector (v32i8 VR256:$src), undef, (i32 4)),
-          (v32i8 VR256:$src)>;
-
 // Implicitly promote a 32-bit scalar to a vector.
 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
           (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;

diff --git a/test/CodeGen/X86/avx-vinsertf128.ll b/test/CodeGen/X86/avx-vinsertf128.ll
index 8813a7f6ab8215b7dd4852e53ebf9e87759c20bf..2b2f7e54116973e425a50da59d751fd7ebf95edc 100644 (file)
--- a/test/CodeGen/X86/avx-vinsertf128.ll
+++ b/test/CodeGen/X86/avx-vinsertf128.ll
@@ -37,10 +37,3 @@ allocas:
   ret void
 }
 
-; CHECK: _C
-; CHECK-NOT: vinsertf128 $1
-define <4 x i32> @C(<4 x i32> %v1) nounwind readonly {
-  %1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-  %2 = shufflevector <8 x i32> %1, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-  ret <4 x i32> %2
-}