Further revise too-restrictive test CodeGen/PowerPC/tls-pic.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227978 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/PowerPC/tls-pic.ll b/test/CodeGen/PowerPC/tls-pic.ll
index 2a5babef09aa1eb3802a7b38c904bf6774d343c5..ed8b981e24e533f87883bcca11a6e0e8fc2d4ef6 100644 (file)
--- a/test/CodeGen/PowerPC/tls-pic.ll
+++ b/test/CodeGen/PowerPC/tls-pic.ll
@@ -30,7 +30,7 @@ entry:
 ; OPT0-32:        addis [[REG:[0-9]+]], 3, a@dtprel@ha
 ; OPT0-32:        addi  {{[0-9]+}}, [[REG]], a@dtprel@l
 ; OPT1-32-LABEL: main
 ; OPT0-32:        addis [[REG:[0-9]+]], 3, a@dtprel@ha
 ; OPT0-32:        addi  {{[0-9]+}}, [[REG]], a@dtprel@l
 ; OPT1-32-LABEL: main

-; OPT1-32:        addi 3, {{[0-9]+}}, a@got@tlsld
+; OPT1-32:        addi {{[0-9]+}}, {{[0-9]+}}, a@got@tlsld

 ; OPT1-32:        bl __tls_get_addr(a@tlsld)@PLT
 ; OPT1-32:        addis [[REG:[0-9]+]], 3, a@dtprel@ha
 ; OPT1-32:        addi  {{[0-9]+}}, [[REG]], a@dtprel@l
 ; OPT1-32:        bl __tls_get_addr(a@tlsld)@PLT
 ; OPT1-32:        addis [[REG:[0-9]+]], 3, a@dtprel@ha
 ; OPT1-32:        addi  {{[0-9]+}}, [[REG]], a@dtprel@l