LegalizeIntegerTypes: Reorder operations in the "big shift by small amount" optimizat...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151722 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index cdc5d5c4b6459d584463529a09f4e65e76a0ecaa..41506d17b7c3ff596ab9a2a3bd601dec613e07bc 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1419,10 +1419,10 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
       std::swap(InL, InH);
 
     // Use a little trick to get the bits that move from Lo to Hi. First
-    // calculate the shift with amount-1.
-    SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, Amt2);
-    // Then shift one bit further to get the right result.
-    SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, DAG.getConstant(1, ShTy));
+    // shift by one bit.
+    SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, ShTy));
+    // Then compute the remaining shift with amount-1.
+    SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
 
     Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
     Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);

diff --git a/test/CodeGen/X86/legalize-shift-64.ll b/test/CodeGen/X86/legalize-shift-64.ll
index 66d9a6df0b2f1dd5bdb3ea272743730717bbe285..2026472692095dd04043eb1cde45b7808e7ee3b1 100644 (file)
--- a/test/CodeGen/X86/legalize-shift-64.ll
+++ b/test/CodeGen/X86/legalize-shift-64.ll
@@ -8,9 +8,9 @@ define i64 @test1(i32 %xx, i32 %test) nounwind {
   ret i64 %shl
 ; CHECK: test1:
 ; CHECK: shll  %cl, %eax
+; CHECK: shrl  %edx
 ; CHECK: xorb  $31
 ; CHECK: shrl  %cl, %edx
-; CHECK: shrl  %edx
 }
 
 define i64 @test2(i64 %xx, i32 %test) nounwind {
@@ -20,9 +20,9 @@ define i64 @test2(i64 %xx, i32 %test) nounwind {
   ret i64 %shl
 ; CHECK: test2:
 ; CHECK: shll  %cl, %esi
+; CHECK: shrl  %edx
 ; CHECK: xorb  $31
 ; CHECK: shrl  %cl, %edx
-; CHECK: shrl  %edx
 ; CHECK: orl   %esi, %edx
 ; CHECK: shll  %cl, %eax
 }
@@ -34,9 +34,9 @@ define i64 @test3(i64 %xx, i32 %test) nounwind {
   ret i64 %shr
 ; CHECK: test3:
 ; CHECK: shrl  %cl, %esi
+; CHECK: leal  (%edx,%edx), %eax
 ; CHECK: xorb  $31, %cl
 ; CHECK: shll  %cl, %eax
-; CHECK: addl  %eax, %eax
 ; CHECK: orl   %esi, %eax
 ; CHECK: shrl  %cl, %edx
 }
@@ -48,9 +48,9 @@ define i64 @test4(i64 %xx, i32 %test) nounwind {
   ret i64 %shr
 ; CHECK: test4:
 ; CHECK: shrl  %cl, %esi
+; CHECK: leal  (%edx,%edx), %eax
 ; CHECK: xorb  $31, %cl
 ; CHECK: shll  %cl, %eax
-; CHECK: addl  %eax, %eax
 ; CHECK: orl   %esi, %eax
 ; CHECK: sarl  %cl, %edx
 }