}
}
+ if (InVT.isVector() && OutVT.isInteger()) {
+ // Handle cases like i64 = BIT_CONVERT v1i64 on x86, where the operand
+ // is legal but the result is not.
+ MVT NVT = MVT::getVectorVT(TLI.getTypeToTransformTo(OutVT), 2);
+
+ if (isTypeLegal(NVT)) {
+ SDValue CastInOp = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, InOp);
+ MVT EltNVT = NVT.getVectorElementType();
+ Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltNVT, CastInOp,
+ DAG.getIntPtrConstant(0));
+ Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltNVT, CastInOp,
+ DAG.getIntPtrConstant(1));
+
+ if (TLI.isBigEndian())
+ std::swap(Lo, Hi);
+
+ return;
+ }
+ }
+
// Lower the bit-convert to a store/load from the stack.
assert(NOutVT.isByteSized() && "Expanded type not byte sized!");
--- /dev/null
+; RUN: llvm-as < %s | llc | grep movl | count 2
+
+define i64 @a(i32 %a, i32 %b) nounwind readnone {
+entry:
+ %0 = insertelement <2 x i32> undef, i32 %a, i32 0 ; <<2 x i32>> [#uses=1]
+ %1 = insertelement <2 x i32> %0, i32 %b, i32 1 ; <<2 x i32>> [#uses=1]
+ %conv = bitcast <2 x i32> %1 to i64 ; <i64> [#uses=1]
+ ret i64 %conv
+}
+