Allow targets to select source order pre-RA scheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148033 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 456966b5de1adced7bd4f8ec2fa301169d593fb5..5c891e940ed6a40f5e794a7244bc3bd987ba5fa3 100644 (file)
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -56,6 +56,7 @@ namespace llvm {
   namespace Sched {
     enum Preference {
       None,             // No preference
+      Source,           // Follow source order.
       RegPressure,      // Scheduling for lowest register pressure.
       Hybrid,           // Scheduling for both latency and register pressure.
       ILP               // Scheduling for ILP in low register pressure mode.

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index bfb6dfa0b17917c66522e54cfe66cda872223a82..9f3969959b6c519d812e3b8b4e19709509fca6e6 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -218,7 +218,8 @@ namespace llvm {
                                              CodeGenOpt::Level OptLevel) {
     const TargetLowering &TLI = IS->getTargetLowering();
 
-    if (OptLevel == CodeGenOpt::None)
+    if (OptLevel == CodeGenOpt::None ||
+        TLI.getSchedulingPreference() == Sched::Source)
       return createSourceListDAGScheduler(IS, OptLevel);
     if (TLI.getSchedulingPreference() == Sched::RegPressure)
       return createBURRListDAGScheduler(IS, OptLevel);