R600: Add a SubtargetFeatture for disabling the ifcvt pass.

This is useful when writing test cases for the AMDIL structurizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195029 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/R600/AMDGPU.td b/lib/Target/R600/AMDGPU.td
index e9304c2261261e2cc26230265a1ec4b8cd7efa49..37ff6b143a03266623947581ab60db47af6ec695 100644 (file)
--- a/lib/Target/R600/AMDGPU.td
+++ b/lib/Target/R600/AMDGPU.td
@@ -28,6 +28,11 @@ def FeatureIRStructurizer : SubtargetFeature <"enable-irstructurizer",
 
 // Target features
 
+def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
+        "EnableIfCvt",
+        "false",
+        "Disable the if conversion pass">;
+
 def FeatureFP64     : SubtargetFeature<"fp64",
         "FP64",
         "true",

diff --git a/lib/Target/R600/AMDGPUSubtarget.cpp b/lib/Target/R600/AMDGPUSubtarget.cpp
index 1e21c8e8b5c024dabf5d9938bba01c58d4a04717..4e97e6e83bb8bfb6e98b76da6cf7de9cd450e60b 100644 (file)
--- a/lib/Target/R600/AMDGPUSubtarget.cpp
+++ b/lib/Target/R600/AMDGPUSubtarget.cpp
@@ -37,6 +37,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
   FP64 = false;
   CaymanISA = false;
   EnableIRStructurizer = false;
+  EnableIfCvt = true;
   ParseSubtargetFeatures(GPU, FS);
   DevName = GPU;
 }
@@ -70,6 +71,10 @@ AMDGPUSubtarget::IsIRStructurizerEnabled() const {
   return EnableIRStructurizer;
 }
 bool
+AMDGPUSubtarget::isIfCvtEnabled() const {
+  return EnableIfCvt;
+}
+bool
 AMDGPUSubtarget::isTargetELF() const {
   return false;
 }

diff --git a/lib/Target/R600/AMDGPUSubtarget.h b/lib/Target/R600/AMDGPUSubtarget.h
index c08cd6a6b8566985e88560a9e248e7b24f52b62f..4288d275c99e8004360fb433acbf121709a4f7ec 100644 (file)
--- a/lib/Target/R600/AMDGPUSubtarget.h
+++ b/lib/Target/R600/AMDGPUSubtarget.h
@@ -50,6 +50,7 @@ private:
   bool FP64;
   bool CaymanISA;
   bool EnableIRStructurizer;
+  bool EnableIfCvt;
 
   InstrItineraryData InstrItins;
 
@@ -66,6 +67,7 @@ public:
   bool hasHWFP64() const;
   bool hasCaymanISA() const;
   bool IsIRStructurizerEnabled() const;
+  bool isIfCvtEnabled() const;
 
   virtual bool enableMachineScheduler() const {
     return getGeneration() <= NORTHERN_ISLANDS;

diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp
index b19277d97be9d829dbbadcd370fdd03a27ab4965..9186c9df3abf89c71bf0f363dada6b84f6766314 100644 (file)
--- a/lib/Target/R600/AMDGPUTargetMachine.cpp
+++ b/lib/Target/R600/AMDGPUTargetMachine.cpp
@@ -169,7 +169,8 @@ bool AMDGPUPassConfig::addPreSched2() {
 
   if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
     addPass(createR600EmitClauseMarkers(*TM));
-  addPass(&IfConverterID);
+  if (ST.isIfCvtEnabled())
+    addPass(&IfConverterID);
   if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
     addPass(createR600ClauseMergePass(*TM));
   return false;