Don't put IT instruction before conditional branches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75361 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Thumb2ITBlockPass.cpp b/lib/Target/ARM/Thumb2ITBlockPass.cpp
index f6f75a1a4b80eb621521a3bdad73b6827455340a..3ff31aa28bfaaa826c555bac28a415dfad0eebe0 100644 (file)
--- a/lib/Target/ARM/Thumb2ITBlockPass.cpp
+++ b/lib/Target/ARM/Thumb2ITBlockPass.cpp
@@ -9,8 +9,8 @@
 
 #define DEBUG_TYPE "thumb2-it"
 #include "ARM.h"
-#include "ARMInstrInfo.h"
 #include "ARMMachineFunctionInfo.h"
+#include "Thumb2InstrInfo.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
@@ -25,7 +25,7 @@ namespace {
     static char ID;
     Thumb2ITBlockPass() : MachineFunctionPass(&ID) {}
 
-    const ARMBaseInstrInfo *TII;
+    const Thumb2InstrInfo *TII;
     ARMFunctionInfo *AFI;
 
     virtual bool runOnMachineFunction(MachineFunction &Fn);
@@ -40,13 +40,21 @@ namespace {
   char Thumb2ITBlockPass::ID = 0;
 }
 
+ARMCC::CondCodes getPredicate(const MachineInstr *MI,
+                              const Thumb2InstrInfo *TII) {
+  unsigned Opc = MI->getOpcode();
+  if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
+    return ARMCC::AL;
+  return TII->getPredicate(MI);
+}
+
 bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
   bool Modified = false;
 
   MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
   while (MBBI != E) {
     MachineInstr *MI = &*MBBI;
-    ARMCC::CondCodes CC = TII->getPredicate(MI);
+    ARMCC::CondCodes CC = getPredicate(MI, TII);
     if (CC == ARMCC::AL) {
       ++MBBI;
       continue;
@@ -64,7 +72,7 @@ bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
     ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
     unsigned Mask = 0x8;
     while (MBBI != E || (Mask & 1)) {
-      ARMCC::CondCodes NCC = TII->getPredicate(&*MBBI);
+      ARMCC::CondCodes NCC = getPredicate(&*MBBI, TII);
       if (NCC == CC) {
         Mask >>= 1;
         Mask |= 0x8;
@@ -86,7 +94,7 @@ bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
 bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
   const TargetMachine &TM = Fn.getTarget();
   AFI = Fn.getInfo<ARMFunctionInfo>();
-  TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
+  TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
 
   if (!AFI->isThumbFunction())
     return false;

diff --git a/test/CodeGen/Thumb2/thumb2-bcc.ll b/test/CodeGen/Thumb2/thumb2-bcc.ll
new file mode 100644 (file)
index 0000000..bd40e3b
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-bcc.ll
@@ -0,0 +1,19 @@
+; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | not grep it
+
+define i32 @t1(i32 %a, i32 %b, i32 %c) {
+; CHECK: t1
+; CHECK: beq
+       %tmp2 = icmp eq i32 %a, 0
+       br i1 %tmp2, label %cond_false, label %cond_true
+
+cond_true:
+       %tmp5 = add i32 %b, 1
+        %tmp6 = and i32 %tmp5, %c
+       ret i32 %tmp6
+
+cond_false:
+       %tmp7 = add i32 %b, -1
+        %tmp8 = xor i32 %tmp7, %c
+       ret i32 %tmp8
+}