Handle i32->f32 bitconvert results.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54315 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index b4c795b7d9f43525a9e86e4150219458f4f310d9..04ef9588a6b3b2f855e1866ca0f4c95c1061822a 100644 (file)
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -138,7 +138,7 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
   setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);
   setOperationAction(ISD::MEMBARRIER,        MVT::Other, Expand);
 
-  if (Subtarget->isSingleFloat()) 
+  if (Subtarget->isSingleFloat())
     setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
 
   if (!Subtarget->hasSEInReg()) {

diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td
index 312cc0b2adb5258d2c3eb9a682be91cd7dc06273..8e05ac50a9acd2e40b1b328c343ed9eff9c8d55b 100644 (file)
--- a/lib/Target/Mips/MipsInstrFPU.td
+++ b/lib/Target/Mips/MipsInstrFPU.td
@@ -339,3 +339,8 @@ def : Pat<(i32 (fp_to_sint AFGR32:$src)), (MFC1A (TRUNC_W_AS32 AFGR32:$src))>;
 
 def : Pat<(i32 (bitconvert FGR32:$src)),  (MFC1 FGR32:$src)>;
 def : Pat<(i32 (bitconvert AFGR32:$src)), (MFC1A AFGR32:$src)>;
+
+def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1 CPURegs:$src)>,
+      Requires<[IsSingleFloat]>;
+def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1A CPURegs:$src)>,
+      Requires<[In32BitMode]>;