[mips] Improve error/warning messages and testing for the .cpload assembler directive.

Summary:
Improved warning message when using .cpload inside a reorder section and added an error message for using .cpload with Mips16 enabled.
Modified the tests to fit with the changes mentioned above, added a test-case for the N32 ABI in cpload.s and did some reformatting to make the tests easier to read.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5465

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221447 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index f78eec5fdaa40d2172bd0941a61819b3817d24d4..bf28368a7f53935639467dc96f3e90b12589d863 100644 (file)
--- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -3030,9 +3030,12 @@ bool MipsAsmParser::eatComma(StringRef ErrorStr) {
 
 bool MipsAsmParser::parseDirectiveCpLoad(SMLoc Loc) {
   if (AssemblerOptions.back()->isReorder())
-    Warning(Loc, ".cpload in reorder section");
+    Warning(Loc, ".cpload should be inside a noreorder section");
 
-  // FIXME: Warn if cpload is used in Mips16 mode.
+  if (inMips16Mode()) {
+    reportParseError(".cpload is not supported in Mips16 mode");
+    return false;
+  }
 
   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Reg;
   OperandMatchResultTy ResTy = parseAnyRegister(Reg);
@@ -3047,6 +3050,12 @@ bool MipsAsmParser::parseDirectiveCpLoad(SMLoc Loc) {
     return false;
   }
 
+  // If this is not the end of the statement, report an error.
+  if (getLexer().isNot(AsmToken::EndOfStatement)) {
+    reportParseError("unexpected token, expected end of statement");
+    return false;
+  }
+
   getTargetStreamer().emitDirectiveCpLoad(RegOpnd.getGPR32Reg());
   return false;
 }

diff --git a/test/MC/Mips/cpload-bad.s b/test/MC/Mips/cpload-bad.s
index 7d186f66f72859b9942cadbde9e50c6b9dd00f1a..803610af922ff6dceb60576e6647b21a7d545026 100644 (file)
--- a/test/MC/Mips/cpload-bad.s
+++ b/test/MC/Mips/cpload-bad.s
@@ -3,13 +3,25 @@
 
         .text
         .option pic2
+        .set noreorder
+        .set mips16
+        .cpload $25
+# ASM: :[[@LINE-1]]:17: error: .cpload is not supported in Mips16 mode
+
+        .set nomips16
         .set reorder
         .cpload $25
-# ASM: :[[@LINE-1]]:9: warning: .cpload in reorder section
+# ASM: :[[@LINE-1]]:9: warning: .cpload should be inside a noreorder section
+
         .set noreorder
         .cpload $32
 # ASM: :[[@LINE-1]]:17: error: invalid register
+
         .cpload $foo
 # ASM: :[[@LINE-1]]:17: error: expected register containing function address
+
         .cpload bar
 # ASM: :[[@LINE-1]]:17: error: expected register containing function address
+
+        .cpload $25 foobar
+# ASM: :[[@LINE-1]]:21: error: unexpected token, expected end of statement

diff --git a/test/MC/Mips/cpload.s b/test/MC/Mips/cpload.s
index bc5e79787ba32c610c441f34017c5a63cf86e1c9..99b020a3c8f2c701f1c6036c6bd1fdb150aa516c 100644 (file)
--- a/test/MC/Mips/cpload.s
+++ b/test/MC/Mips/cpload.s
@@ -1,12 +1,16 @@
 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ASM
 #
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -filetype=obj -o -| \
-# RUN: llvm-objdump -d -r -arch=mips - | \
-# RUN: FileCheck %s -check-prefix=OBJ
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+o32 -filetype=obj -o -| \
+# RUN:  llvm-objdump -d -r -arch=mips - | \
+# RUN:    FileCheck %s -check-prefix=OBJ-O32
 
-# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -filetype=obj -o -| \
-# RUN: llvm-objdump -d -r -arch=mips - | \
-# RUN: FileCheck %s -check-prefix=OBJ64
+# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=-n64,+n32 -filetype=obj -o -| \
+# RUN:  llvm-objdump -d -r -arch=mips - | \
+# RUN:    FileCheck %s -check-prefix=OBJ-N32
+
+# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+n64 -filetype=obj -o -| \
+# RUN:  llvm-objdump -d -r -arch=mips - | \
+# RUN:    FileCheck %s -check-prefix=OBJ-N64
 
 # ASM:    .text
 # ASM:    .option pic2
@@ -14,17 +18,22 @@
 # ASM:    .cpload $25
 # ASM:    .set reorder
 
-# OBJ:    .text
-# OBJ:    lui $gp, 0
-# OBJ: R_MIPS_HI16 _gp_disp
-# OBJ:    addiu $gp, $gp, 0
-# OBJ: R_MIPS_LO16 _gp_disp
-# OBJ:    addu $gp, $gp, $25
+# OBJ-O32:    .text
+# OBJ-O32:    lui $gp, 0
+# OBJ-O32: R_MIPS_HI16 _gp_disp
+# OBJ-O32:    addiu $gp, $gp, 0
+# OBJ-O32: R_MIPS_LO16 _gp_disp
+# OBJ-O32:    addu $gp, $gp, $25
+
+# OBJ-N32:     .text
+# OBJ-N32-NOT: lui   $gp, 0
+# OBJ-N32-NOT: addiu $gp, $gp, 0
+# OBJ-N32-NOT: addu  $gp, $gp, $25
 
-# OBJ64: .text
-# OBJ64-NOT: lui $gp, 0
-# OBJ64-NOT: addiu $gp, $gp, 0
-# OBJ64-NOT: addu $gp, $gp, $25
+# OBJ-N64:     .text
+# OBJ-N64-NOT: lui   $gp, 0
+# OBJ-N64-NOT: addiu $gp, $gp, 0
+# OBJ-N64-NOT: addu  $gp, $gp, $25
 
         .text
         .option pic2