Remove a bunch more SparcV9 specific stuff

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28093 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 818331d2521792c849d6f88fbfb0db193f3ecd9b..d2988f05ab00ed7460323b0b9da12217d4500023 100644 (file)
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -58,9 +58,6 @@ typedef short MachineOpCode;
 //   - Reg will be of virtual register type MO_MInstrVirtualReg.  The field
 //     MachineInstr* minstr will point to the instruction that computes reg.
 //
-//   - %sp will be of virtual register type MO_MachineReg.
-//     The field regNum identifies the machine register.
-//
 //   - NumElements will be of virtual register type MO_VirtualReg.
 //     The field Value* value identifies the value.
 //
@@ -75,7 +72,6 @@ private:
   enum {
     DEFFLAG     = 0x01,       // this is a def of the operand
     USEFLAG     = 0x02,       // this is a use of the operand
-    PCRELATIVE  = 0x40        // Operand is relative to PC, not a global address
   };
 
 public:
@@ -93,7 +89,6 @@ public:
 
   enum MachineOperandType {
     MO_VirtualRegister,         // virtual register for *value
-    MO_MachineRegister,         // pre-assigned machine register `regNum'
     MO_SignExtendedImmed,
     MO_UnextendedImmed,
     MO_MachineBasicBlock,       // MachineBasicBlock reference
@@ -152,18 +147,9 @@ private:
     extra.regNum = Reg;
   }
 
-  MachineOperand(Value *V, MachineOperandType OpTy, UseType UseTy,
-                 bool isPCRelative = false)
-    : flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) {
-    assert(OpTy != MachineOperand::MO_GlobalAddress);
-    zeroContents();
-    contents.value = V;
-    extra.regNum = -1;
-  }
-
   MachineOperand(GlobalValue *V, MachineOperandType OpTy, UseType UseTy,
-                 bool isPCRelative = false, int Offset = 0)
-    : flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) {
+                 int Offset = 0)
+    : flags(UseTy), opType(OpTy) {
     assert(OpTy == MachineOperand::MO_GlobalAddress);
     zeroContents ();
     contents.value = (Value*)V;
@@ -177,8 +163,8 @@ private:
     extra.regNum = -1;
   }
 
-  MachineOperand(const char *SymName, bool isPCRelative, int Offset)
-    : flags(isPCRelative?PCRELATIVE:0), opType(MO_ExternalSymbol) {
+  MachineOperand(const char *SymName, int Offset)
+    : flags(0), opType(MO_ExternalSymbol) {
     zeroContents ();
     contents.SymbolName = SymName;
     extra.offset = Offset;
@@ -192,7 +178,6 @@ public:
     extra = M.extra;
   }
 
-
   ~MachineOperand() {}
 
   const MachineOperand &operator=(const MachineOperand &MO) {
@@ -218,7 +203,7 @@ public:
   /// Note: The sparc backend should not use this method.
   ///
   bool isRegister() const {
-    return opType == MO_MachineRegister || opType == MO_VirtualRegister;
+    return opType == MO_VirtualRegister;
   }
 
   /// Accessors that tell you what kind of MachineOperand you're looking at.
@@ -247,10 +232,6 @@ public:
     assert(opType == MO_VirtualRegister && "Wrong MachineOperand accessor");
     return contents.value;
   }
-  int getMachineRegNum() const {
-    assert(opType == MO_MachineRegister && "Wrong MachineOperand accessor");
-    return extra.regNum;
-  }
   int64_t getImmedValue() const {
     assert(isImmediate() && "Wrong MachineOperand accessor");
     return contents.immedVal;
@@ -301,8 +282,7 @@ public:
   /// allocated to this operand.
   ///
   bool hasAllocatedReg() const {
-    return (extra.regNum >= 0 &&
-            (opType == MO_VirtualRegister || opType == MO_MachineRegister));
+    return extra.regNum >= 0 && opType == MO_VirtualRegister;
   }
 
   /// getReg - Returns the register number. It is a runtime error to call this
@@ -445,28 +425,6 @@ public:
   // Accessors to add operands when building up machine instructions
   //
 
-  /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
-  /// operands list...
-  ///
-  void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
-    assert(!OperandsComplete() &&
-           "Trying to add an operand to a machine instr that is already done!");
-    operands.push_back(
-      MachineOperand(V, MachineOperand::MO_VirtualRegister,
-                     !isDef ? MachineOperand::Use :
-                     (isDefAndUse ? MachineOperand::UseAndDef :
-                      MachineOperand::Def)));
-  }
-
-  void addRegOperand(Value *V,
-                     MachineOperand::UseType UTy = MachineOperand::Use,
-                     bool isPCRelative = false) {
-    assert(!OperandsComplete() &&
-           "Trying to add an operand to a machine instr that is already done!");
-    operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
-                                      UTy, isPCRelative));
-  }
-
   /// addRegOperand - Add a symbolic virtual register reference...
   ///
   void addRegOperand(int reg, bool isDef) {
@@ -487,26 +445,6 @@ public:
       MachineOperand(reg, MachineOperand::MO_VirtualRegister, UTy));
   }
 
-  /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
-  ///
-  void addMachineRegOperand(int reg, bool isDef) {
-    assert(!OperandsComplete() &&
-           "Trying to add an operand to a machine instr that is already done!");
-    operands.push_back(
-      MachineOperand(reg, MachineOperand::MO_MachineRegister,
-                     isDef ? MachineOperand::Def : MachineOperand::Use));
-  }
-
-  /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
-  ///
-  void addMachineRegOperand(int reg,
-                            MachineOperand::UseType UTy = MachineOperand::Use) {
-    assert(!OperandsComplete() &&
-           "Trying to add an operand to a machine instr that is already done!");
-    operands.push_back(
-      MachineOperand(reg, MachineOperand::MO_MachineRegister, UTy));
-  }
-
   /// addZeroExtImmOperand - Add a zero extended constant argument to the
   /// machine instruction.
   ///
@@ -569,18 +507,18 @@ public:
     operands.push_back(MachineOperand(I, MachineOperand::MO_JumpTableIndex));
   }
   
-  void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative, int Offset) {
+  void addGlobalAddressOperand(GlobalValue *GV, int Offset) {
     assert(!OperandsComplete() &&
            "Trying to add an operand to a machine instr that is already done!");
     operands.push_back(
       MachineOperand(GV, MachineOperand::MO_GlobalAddress,
-                     MachineOperand::Use, isPCRelative, Offset));
+                     MachineOperand::Use, Offset));
   }
 
   /// addExternalSymbolOperand - Add an external symbol operand to this instr
   ///
-  void addExternalSymbolOperand(const char *SymName, bool isPCRelative) {
-    operands.push_back(MachineOperand(SymName, isPCRelative, 0));
+  void addExternalSymbolOperand(const char *SymName) {
+    operands.push_back(MachineOperand(SymName, 0));
   }
 
   //===--------------------------------------------------------------------===//

diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h
index c267c77da29efdd01864af51e89c5074f3b96d24..c2944c0369630cdcfbf9b1085433a6afdbfa2b4f 100644 (file)
--- a/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -46,22 +46,6 @@ public:
     return *this;
   }
 
-  /// addReg - Add an LLVM value that is to be used as a register...
-  ///
-  const MachineInstrBuilder &addReg(
-    Value *V,
-    MachineOperand::UseType Ty = MachineOperand::Use) const {
-    MI->addRegOperand(V, Ty);
-    return *this;
-  }
-
-  /// addRegDef - Add an LLVM value that is to be defined as a register... this
-  /// is the same as addReg(V, MachineOperand::Def).
-  ///
-  const MachineInstrBuilder &addRegDef(Value *V) const {
-    return addReg(V, MachineOperand::Def);
-  }
-
   /// addImm - Add a new immediate operand.
   ///
   const MachineInstrBuilder &addImm(int Val) const {
@@ -112,15 +96,13 @@ public:
   }
 
   const MachineInstrBuilder &addGlobalAddress(GlobalValue *GV,
-                                              bool isPCRelative = false,
                                               int Offset = 0) const {
-    MI->addGlobalAddressOperand(GV, isPCRelative, Offset);
+    MI->addGlobalAddressOperand(GV, Offset);
     return *this;
   }
 
-  const MachineInstrBuilder &addExternalSymbol(const char *FnName,
-                                               bool isPCRelative = false) const{
-    MI->addExternalSymbolOperand(FnName, isPCRelative);
+  const MachineInstrBuilder &addExternalSymbol(const char *FnName) const{
+    MI->addExternalSymbolOperand(FnName);
     return *this;
   }
 };

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 3d65dfd31bde51402377e8a8ffe913c4946005b3..367631c60ec5157ea59f681e8489065f90880136 100644 (file)
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -141,7 +141,7 @@ MachineInstr::SetMachineOperandConst(unsigned i,
 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
   assert(i < getNumOperands());          // must be explicit op
 
-  operands[i].opType = MachineOperand::MO_MachineRegister;
+  operands[i].opType = MachineOperand::MO_VirtualRegister;
   operands[i].contents.value = NULL;
   operands[i].extra.regNum = regNum;
 }
@@ -187,9 +187,6 @@ static void print(const MachineOperand &MO, std::ostream &OS,
     if (MO.hasAllocatedReg())
       OutputReg(OS, MO.getReg(), MRI);
     break;
-  case MachineOperand::MO_MachineRegister:
-    OutputReg(OS, MO.getMachineRegNum(), MRI);
-    break;
   case MachineOperand::MO_SignExtendedImmed:
     OS << (long)MO.getImmedValue();
     break;
@@ -297,9 +294,6 @@ std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) {
       OutputValue(OS, MO.getVRegValue());
     }
     break;
-  case MachineOperand::MO_MachineRegister:
-    OutputReg(OS, MO.getMachineRegNum());
-    break;
   case MachineOperand::MO_SignExtendedImmed:
     OS << (long)MO.getImmedValue();
     break;

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 3509b16b6ab43ff16a8556a2f290781c7408063c..2b7b877cb174aeea692ca1257be945d02542feb6 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -110,7 +110,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
     MI->addRegOperand(R->getReg(), MachineOperand::Use);
   } else if (GlobalAddressSDNode *TGA =
              dyn_cast<GlobalAddressSDNode>(Op)) {
-    MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset());
+    MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
   } else if (BasicBlockSDNode *BB =
              dyn_cast<BasicBlockSDNode>(Op)) {
     MI->addMachineBasicBlockOperand(BB->getBasicBlock());
@@ -143,7 +143,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
     MI->addConstantPoolIndexOperand(Idx, Offset);
   } else if (ExternalSymbolSDNode *ES = 
              dyn_cast<ExternalSymbolSDNode>(Op)) {
-    MI->addExternalSymbolOperand(ES->getSymbol(), false);
+    MI->addExternalSymbolOperand(ES->getSymbol());
   } else {
     assert(Op.getValueType() != MVT::Other &&
            Op.getValueType() != MVT::Flag &&
@@ -296,7 +296,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
       // Add the asm string as an external symbol operand.
       const char *AsmStr =
         cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
-      MI->addExternalSymbolOperand(AsmStr, false);
+      MI->addExternalSymbolOperand(AsmStr);
       
       // Add all of the operand registers to the instruction.
       for (unsigned i = 2; i != NumOps;) {
@@ -311,13 +311,13 @@ void ScheduleDAG::EmitNode(SDNode *Node,
         case 1:  // Use of register.
           for (; NumVals; --NumVals, ++i) {
             unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
-            MI->addMachineRegOperand(Reg, MachineOperand::Use);
+            MI->addRegOperand(Reg, MachineOperand::Use);
           }
           break;
         case 2:   // Def of register.
           for (; NumVals; --NumVals, ++i) {
             unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
-            MI->addMachineRegOperand(Reg, MachineOperand::Def);
+            MI->addRegOperand(Reg, MachineOperand::Def);
           }
           break;
         case 3: { // Immediate.

diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp
index 435e8e84d89fab5f6298b1147b820e6fef09f0dd..1e360676b6d80b08b952437eef335bdfc7b59eb8 100644 (file)
--- a/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -77,7 +77,7 @@ FunctionPass *llvm::createAlphaCodePrinterPass (std::ostream &o,
 void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
 {
   const MachineOperand &MO = MI->getOperand(opNum);
-  if (MO.getType() == MachineOperand::MO_MachineRegister) {
+  if (MO.getType() == MachineOperand::MO_VirtualRegister) {
     assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
     O << TM.getRegisterInfo()->get(MO.getReg()).Name;
   } else if (MO.isImmediate()) {
@@ -94,12 +94,6 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
 
   switch (MO.getType()) {
   case MachineOperand::MO_VirtualRegister:
-    if (Value *V = MO.getVRegValueOrNull()) {
-      O << "<" << V->getName() << ">";
-      return;
-    }
-    // FALLTHROUGH
-  case MachineOperand::MO_MachineRegister:
     O << RI.get(MO.getReg()).Name;
     return;
 

diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 8f6310e4398f69c1efb01c73fab6ca2421efe6a2..85c9da8e6427b7e2841d5d783038a68460cce80a 100644 (file)
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -263,7 +263,8 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
     .addReg(Alpha::R29).addImm(curgpdist);
 
   //evil const_cast until MO stuff setup to handle const
-  BuildMI(MBB, MBBI, Alpha::ALTENT, 1).addGlobalAddress(const_cast<Function*>(MF.getFunction()), true);
+  BuildMI(MBB, MBBI, Alpha::ALTENT, 1)
+    .addGlobalAddress(const_cast<Function*>(MF.getFunction()));
 
   // Get the number of bytes to allocate from the FrameInfo
   long NumBytes = MFI->getStackSize();

diff --git a/lib/Target/IA64/IA64AsmPrinter.cpp b/lib/Target/IA64/IA64AsmPrinter.cpp
index 6895d328da6890591fd2e267d2cb1cddd569e52b..087fcc32d80be9bab6bb0edaea06f7b7ea2aeffe 100644 (file)
--- a/lib/Target/IA64/IA64AsmPrinter.cpp
+++ b/lib/Target/IA64/IA64AsmPrinter.cpp
@@ -66,7 +66,7 @@ namespace {
     // This method is used by the tablegen'erated instruction printer.
     void printOperand(const MachineInstr *MI, unsigned OpNo){
       const MachineOperand &MO = MI->getOperand(OpNo);
-      if (MO.getType() == MachineOperand::MO_MachineRegister) {
+      if (MO.getType() == MachineOperand::MO_VirtualRegister) {
         assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
         //XXX Bug Workaround: See note in Printer::doInitialization about %.
         O << TM.getRegisterInfo()->get(MO.getReg()).Name;
@@ -174,12 +174,6 @@ void IA64AsmPrinter::printOp(const MachineOperand &MO,
   const MRegisterInfo &RI = *TM.getRegisterInfo();
   switch (MO.getType()) {
   case MachineOperand::MO_VirtualRegister:
-    if (Value *V = MO.getVRegValueOrNull()) {
-      O << "<" << V->getName() << ">";
-      return;
-    }
-    // FALLTHROUGH
-  case MachineOperand::MO_MachineRegister:
     O << RI.get(MO.getReg()).Name;
     return;
 

diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 2cf10a2f9d4db44f15bc2091c3a87a197b5062fa..e85ce9fd6fd174b1f68d1624c4925325cc26cde1 100644 (file)
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -86,7 +86,7 @@ namespace {
 
     void printOperand(const MachineInstr *MI, unsigned OpNo) {
       const MachineOperand &MO = MI->getOperand(OpNo);
-      if (MO.getType() == MachineOperand::MO_MachineRegister) {
+      if (MO.getType() == MachineOperand::MO_VirtualRegister) {
         assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
         O << TM.getRegisterInfo()->get(MO.getReg()).Name;
       } else if (MO.isImmediate()) {
@@ -353,13 +353,6 @@ void PPCAsmPrinter::printOp(const MachineOperand &MO) {
   int new_symbol;
 
   switch (MO.getType()) {
-  case MachineOperand::MO_VirtualRegister:
-    if (Value *V = MO.getVRegValueOrNull()) {
-      O << "<" << V->getName() << ">";
-      return;
-    }
-    // FALLTHROUGH
-  case MachineOperand::MO_MachineRegister:
     O << RI.get(MO.getReg()).Name;
     return;
 

diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp
index ced2b3dd0c17ec5f99f29479c85f8c45fd461743..2d81bbd6700e8d16cb0786fc6425bff021af3c1a 100644 (file)
--- a/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -147,12 +147,6 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
   }
   switch (MO.getType()) {
   case MachineOperand::MO_VirtualRegister:
-    if (Value *V = MO.getVRegValueOrNull()) {
-      O << "<" << V->getName() << ">";
-      break;
-    }
-    // FALLTHROUGH
-  case MachineOperand::MO_MachineRegister:
     if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
       O << "%" << LowercaseString (RI.get(MO.getReg()).Name);
     else
@@ -195,8 +189,7 @@ void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
   
   MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType();
   
-  if ((OpTy == MachineOperand::MO_VirtualRegister ||
-       OpTy == MachineOperand::MO_MachineRegister) &&
+  if (OpTy == MachineOperand::MO_VirtualRegister &&
       MI->getOperand(opNum+1).getReg() == SP::G0)
     return;   // don't print "+%g0"
   if ((OpTy == MachineOperand::MO_SignExtendedImmed ||

diff --git a/lib/Target/X86/X86ATTAsmPrinter.cpp b/lib/Target/X86/X86ATTAsmPrinter.cpp
index b7f5b6c8a693625c38350c6961b676f58b37c518..5283ddd79e30ad55403056172f1e7261498dc7d9 100755 (executable)
--- a/lib/Target/X86/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/X86ATTAsmPrinter.cpp
@@ -109,7 +109,6 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
   const MRegisterInfo &RI = *TM.getRegisterInfo();
   switch (MO.getType()) {
   case MachineOperand::MO_VirtualRegister:
-  case MachineOperand::MO_MachineRegister:
     assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
            "Virtual registers should not make it this far!");
     O << '%';

diff --git a/lib/Target/X86/X86InstrBuilder.h b/lib/Target/X86/X86InstrBuilder.h
index 95d7f927d8f531dba3914973c2595582da69cd03..6a3c116f6d4e959d6c75fb82f54f9916db8da278 100644 (file)
--- a/lib/Target/X86/X86InstrBuilder.h
+++ b/lib/Target/X86/X86InstrBuilder.h
@@ -93,7 +93,7 @@ inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
     assert (0);
   MIB.addZImm(AM.Scale).addReg(AM.IndexReg);
   if (AM.GV)
-    return MIB.addGlobalAddress(AM.GV, false, AM.Disp);
+    return MIB.addGlobalAddress(AM.GV, AM.Disp);
   else
     return MIB.addSImm(AM.Disp);
 }

diff --git a/lib/Target/X86/X86IntelAsmPrinter.cpp b/lib/Target/X86/X86IntelAsmPrinter.cpp
index f3213b64f415fc76627dec06a60b38aa40c31548..f9093da36d8d863289d70c1fcfabc869cdc34040 100755 (executable)
--- a/lib/Target/X86/X86IntelAsmPrinter.cpp
+++ b/lib/Target/X86/X86IntelAsmPrinter.cpp
@@ -115,12 +115,6 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
   const MRegisterInfo &RI = *TM.getRegisterInfo();
   switch (MO.getType()) {
   case MachineOperand::MO_VirtualRegister:
-    if (Value *V = MO.getVRegValueOrNull()) {
-      O << "<" << V->getName() << ">";
-      return;
-    }
-    // FALLTHROUGH
-  case MachineOperand::MO_MachineRegister:
     if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
       O << RI.get(MO.getReg()).Name;
     else

diff --git a/lib/Target/X86/X86IntelAsmPrinter.h b/lib/Target/X86/X86IntelAsmPrinter.h
index b408ea3903b5718067f7e995830736842e9a1111..28ccfc9ed0948622da3d107e7d0093c8ff616eb8 100755 (executable)
--- a/lib/Target/X86/X86IntelAsmPrinter.h
+++ b/lib/Target/X86/X86IntelAsmPrinter.h
@@ -37,8 +37,8 @@ struct X86IntelAsmPrinter : public X86SharedAsmPrinter {
   void printOperand(const MachineInstr *MI, unsigned OpNo,
                     const char *Modifier = 0) {
     const MachineOperand &MO = MI->getOperand(OpNo);
-    if (MO.getType() == MachineOperand::MO_MachineRegister) {
-      assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
+    if (MO.getType() == MachineOperand::MO_VirtualRegister) {
+      assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Not physreg??");
       O << TM.getRegisterInfo()->get(MO.getReg()).Name;
     } else {
       printOp(MO, Modifier);

diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 383529a0eb4f8ada05414ba12165f408184a3013..a9e345fc68a0321bc4cace0849445d19132a753a 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -150,7 +150,7 @@ static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
   else if (MI->getOperand(1).isGlobalAddress())
     return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
       .addGlobalAddress(MI->getOperand(1).getGlobal(),
-                        false, MI->getOperand(1).getOffset());
+                        MI->getOperand(1).getOffset());
   else if (MI->getOperand(1).isJumpTableIndex())
     return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
       .addJumpTableIndex(MI->getOperand(1).getJumpTableIndex());