; RUN: llc -mtriple=arm64-apple-darwin -mcpu=cyclone -enable-misched=false < %s | FileCheck %s
; RUN: llc -O0 -mtriple=arm64-apple-darwin < %s | FileCheck --check-prefix=FAST %s
-; REQUIRES: asserts
; rdar://9932559
define i64 @i8i16callee(i64 %a1, i64 %a2, i64 %a3, i8 signext %a4, i16 signext %a5, i64 %a6, i64 %a7, i64 %a8, i8 signext %b1, i16 signext %b2, i8 signext %b3, i8 signext %b4) nounwind readnone noinline {
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
; RUN: llc %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t
; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA
-; REQUIRES: asserts
; CHECK-SSA-LABEL: Machine code for function t1
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -verify-machineinstrs < %s
-; REQUIRES: asserts
; Test that the Machine Instruction PHI node doesn't have more than one operand
; from the same predecessor.
;RUN: llc < %s -march=r600 -mcpu=cedar
-;REQUIRES: asserts
;This test ensures that R600 backend can handle ifcvt properly
;and do not generate ALU clauses with more than 128 instructions.
;RUN: llc < %s -march=r600 -mcpu=cayman
-;REQUIRES: asserts
define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 {
main_body:
;RUN: llc < %s -march=r600 -mcpu=cayman
-;REQUIRES: asserts
define void @main(<4 x float> inreg, <4 x float> inreg) #0 {
main_body:
;RUN: llc < %s -march=r600 -mcpu=redwood
-;REQUIRES: asserts
define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
main_body:
; RUN: llc < %s -fast-isel -verify-machineinstrs -mtriple=x86_64-apple-darwin10
; RUN: llc < %s -fast-isel -verify-machineinstrs -mtriple=x86_64-pc-win32 | FileCheck %s -check-prefix=WIN32
; RUN: llc < %s -fast-isel -verify-machineinstrs -mtriple=x86_64-pc-win64 | FileCheck %s -check-prefix=WIN64
-; REQUIRES: asserts
; Previously, this would cause an assert.
define i31 @t1(i31 %a, i31 %b, i31 %c) {