- Enable x86 isel preprocessing by default unless -fast is specified.

- Also disable isel load folding if -fast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29956 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h
index e6deda620e24384ebdad7e8969c8e6e931e06e63..11a63868d989b16766b2d1dd45ad369a90eb2f20 100644 (file)
--- a/lib/Target/X86/X86.h
+++ b/lib/Target/X86/X86.h
@@ -28,7 +28,7 @@ class MachineCodeEmitter;
 /// createX86ISelDag - This pass converts a legalized DAG into a 
 /// X86-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *createX86ISelDag(X86TargetMachine &TM);
+FunctionPass *createX86ISelDag(X86TargetMachine &TM, bool Fast);
 
 /// createX86FloatingPointStackifierPass - This function returns a pass which
 /// converts floating point register references and pseudo instructions into

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 0ca063bbae107afade6e93e4a2c04f56d3fd785d..9697f2591314f9a174c09458f95dc18f4e5dcfa8 100644 (file)
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -92,6 +92,10 @@ namespace {
     /// register should set this to true.
     bool ContainsFPCode;
 
+    /// FastISel - Enable fast(er) instruction selection.
+    ///
+    bool FastISel;
+
     /// X86Lowering - This object fully describes how to lower LLVM code to an
     /// X86-specific SelectionDAG.
     X86TargetLowering X86Lowering;
@@ -103,8 +107,9 @@ namespace {
     unsigned GlobalBaseReg;
 
   public:
-    X86DAGToDAGISel(X86TargetMachine &TM)
+    X86DAGToDAGISel(X86TargetMachine &TM, bool fast)
       : SelectionDAGISel(X86Lowering),
+        ContainsFPCode(false), FastISel(fast), 
         X86Lowering(*TM.getTargetLowering()),
         Subtarget(&TM.getSubtarget<X86Subtarget>()) {}
 
@@ -237,7 +242,7 @@ bool X86DAGToDAGISel::CanBeFoldedBy(SDNode *N, SDNode *U) {
   //      /        [X]
   //      |         ^
   //     [U]--------|
-  return !isNonImmUse(U, N);
+  return !FastISel && !isNonImmUse(U, N);
 }
 
 /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
@@ -370,7 +375,7 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
   DEBUG(BB->dump());
   MachineFunction::iterator FirstMBB = BB;
 
-  if (X86ISelPreproc)
+  if (!FastISel)
     InstructionSelectPreprocess(DAG);
 
   // Codegen the basic block.
@@ -1071,6 +1076,6 @@ SelectInlineAsmMemoryOperand(const SDOperand &Op, char ConstraintCode,
 /// createX86ISelDag - This pass converts a legalized DAG into a 
 /// X86-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM) {
-  return new X86DAGToDAGISel(TM);
+FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool Fast) {
+  return new X86DAGToDAGISel(TM, Fast);
 }

diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index 9616dc18f27c91d89297f95080a7d1f4a040217f..ca2651b17e6a0a042f94f2db35fc527addb8a12a 100644 (file)
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -103,7 +103,7 @@ bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
   PM.add(createUnreachableBlockEliminationPass());
 
   // Install an instruction selector.
-  PM.add(createX86ISelDag(*this));
+  PM.add(createX86ISelDag(*this, Fast));
 
   // Print the instruction selected machine code...
   if (PrintMachineCode)
@@ -168,7 +168,7 @@ void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
   PM.add(createUnreachableBlockEliminationPass());
 
   // Install an instruction selector.
-  PM.add(createX86ISelDag(TM));
+  PM.add(createX86ISelDag(TM, false));
 
   // Print the instruction selected machine code...
   if (PrintMachineCode)